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@Philogy
Philogy / VRGDA.ipynb
Created September 14, 2022 18:35
Simple VRGDA simulator
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@Philogy
Philogy / EvenOdd.huff
Created August 17, 2022 21:45
Huff Challenge #2
#define macro MAIN() = takes(0) returns(0) {
returndatasize calldataload // [x]
not // [~x]
0x1 and // [even]
returndatasize mstore // []
msize returndatasize return // []
}
@Philogy
Philogy / ReturnBlock.huff
Created August 16, 2022 21:53
Huff Challenge #1
#define macro MAIN() = takes(0) returns(0) {
number returndatasize mstore
0x20 returndatasize return
}
@Philogy
Philogy / Duplicator.huff
Last active August 1, 2022 10:51
Cell Division - 24 bytes
#define constant CNSTR_CODE = 0x601834818180333cf3
#define constant CNSTR_CODE_SIZE = 0x9
#define constant CNSTR_CODE_OFFSET = 0x17 // 0x20 - [CNSTR_CODE_SIZE]
#define macro MAIN() = takes(0) returns(0) {
[CNSTR_CODE_SIZE] [CNSTR_CODE_OFFSET] // [cc_offset, cc_size]
returndatasize // [0, cc_offset, cc_size]
[CNSTR_CODE] dup2 mstore // [0, cc_offset, cc_size]
dup3 dup3 dup3 create // [addr1, 0, cc_offset, cc_size]
pop create // [addr2]