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Created August 15, 2015 15:14
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linino one 20150816
linino> tftpboot 80020000 netbsd.bin.linino1 ; go 80020000
dup 1 speed 100
Using eth0 device
TFTP from server 192.168.0.9; our IP address is 192.168.0.111
Filename 'netbsd.bin.linino1'.
Load address: 0x80020000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
########################
done
Bytes transferred = 1452112 (162850 hex)
## Starting application at 0x80020000 ...
@00000111,00000011,Early console started!
freqs: cpu=400000000 bus=200000000 mem=400000000 ref=25000000 pll=400000000
MIPS32/64 params: cpu arch: 128
MIPS32/64 params: TLB entries: 16
MIPS32/64 params: Icache: line = 32, total = 65536, ways = 4
sets = 512
MIPS32/64 params: Dcache: line = 32, total = 32768, ways = 4
sets = 256
picache_stride = 4096
picache_loopcount = 16
mips_fixup_stubs: 3242 fixups done in 2675702 cycles
Memory size: 0x04000000
phys segment: 0x3fff000 @ 0x1000
adding 0x3e6f000 @ 0x191000 to freelist 0
pmap_steal_memory: seg 0: 0x191 0x191 0x3fff 0x3fff
pmap_steal_memory: seg 0: 0x1b4 0x1b4 0x3fff 0x3fff
pmap_steal_memory: seg 0: 0x1b6 0x1b6 0x3fff 0x3fff
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 7.99.20 (LININO1) #11: Sat Aug 15 15:10:28 UTC 2015
root@aug:/export/o/20150812/evbmips/sys/arch/evbmips/compile/LININO1
Atheros AR9331
total memory = 65536 KB
avail memory = 62508 KB
mainbus0 (root)
cpu0 at mainbus0: 400.00MHz (hz cycles = 2000000, delay divisor = 200)
cpu0: MIPS 24K (0x19374) Rev. 116 with software emulated floating point
cpu0: 16 TLB entries, 256MB max page size
cpu0: 64KB/32B 4-way set-associative L1 instruction cache
cpu0: 32KB/32B 4-way set-associative write-back L1 data cache
wdog0 at mainbus0: 5 second period
arbus0 at mainbus0
uart0 at arbus0 addr 0x18020000 cpu irq 4 misc irq 3
ehci at arbus0 addr 0x1b000100 cpu irq 1 not configured
ae at arbus0 addr 0x19000000 cpu irq 2 not configured
ae at arbus0 addr 0x1a000000 cpu irq 3 not configured
rn_init: radix functions require max_keylen be set
root device:
use one of: ddb halt reboot
root device:
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