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@aquynh
aquynh / gist:cf6f1726128a5d1ce998
Created September 24, 2014 15:12
Changes from "next" to "v3" - with changes on instruction REMOVED (to keep it short)
diff -Nurp capstone-next.git/include/arm.h capstone-v3.git/include/arm.h
--- capstone-next.git/include/arm.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/arm.h 2014-09-24 22:57:32.000000000 +0800
@@ -50,6 +50,53 @@ typedef enum arm_cc {
ARM_CC_AL // Always (unconditional) Always (unconditional)
} arm_cc;
+typedef enum arm_sysreg {
+ //> Special registers for MSR
+ ARM_SYSREG_INVALID = 0,
@aquynh
aquynh / gist:6819d20658a847f728e2
Last active August 29, 2015 14:06
Changes between "next" & "v3" - including all changes on instructions
diff -Nurp capstone-next.git/include/arm.h capstone-v3.git/include/arm.h
--- capstone-next.git/include/arm.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/arm.h 2014-09-24 22:57:32.000000000 +0800
@@ -50,6 +50,53 @@ typedef enum arm_cc {
ARM_CC_AL // Always (unconditional) Always (unconditional)
} arm_cc;
+typedef enum arm_sysreg {
+ //> Special registers for MSR
+ ARM_SYSREG_INVALID = 0,
--- ptrace/disasm.c 2014-04-10 10:30:33.000000000 +1200
+++ ptrace/disasm2.c 2014-09-04 12:52:53.425315639 +1200
@@ -4,28 +4,21 @@
try:
from ptrace.cpu_info import CPU_I386, CPU_X86_64
- try:
- from distorm3 import Decode
- if CPU_X86_64:
- from distorm3 import Decode64Bits as DecodeBits
@aquynh
aquynh / gist:9391743
Created March 6, 2014 15:08
Remove string check & stack protector functions for Capstone
diff --git a/Makefile b/Makefile
index 3087e30..6d82dfa 100644
--- a/Makefile
+++ b/Makefile
@@ -15,6 +15,10 @@ RANLIB = $(CROSS)ranlib
STRIP = $(CROSS)strip
endif
+# remove string check & stack protector functions
+CFLAGS += -D_FORTIFY_SOURCE=0