axayjha

import { NgModule } from '@angular/core';
import {MatCheckboxModule} from '@angular/material/checkbox';
import {MatButtonModule} from '@angular/material/button';
import {MatInputModule} from '@angular/material/input';
import {MatAutocompleteModule} from '@angular/material/autocomplete';
import {MatDatepickerModule} from '@angular/material/datepicker';
import {MatFormFieldModule} from '@angular/material/form-field';
import {MatRadioModule} from '@angular/material/radio';
import {MatSelectModule} from '@angular/material/select';
import {MatSliderModule} from '@angular/material/slider';

axayjha

#include <Servo.h>
#include <LiquidCrystal.h>
#include "DHT.h"
#define DHTPIN 2
int threshold;
int ac=3;
int curtain=5;
Servo myservo;
#define DHTTYPE DHT11 
// initialize the library with the numbers of the interface pins

axayjha

module mul_test_bench;
	reg [15:0] data_in;
	reg clk, start;
	wire done;

	datapath DP (eqz, LdA, LdB, LdP, clrP, decB, data_in, clk);
	controller CON (LdA, LdB, LdP, clrP, decB, done, clk, eqz, start);

	initial
		begin

axayjha

module controller (LdA, LdB, LdP, clrP, decB, done, clk, eqz, start);
	input clk, eqz, start;
	output reg LdA, LdB, LdP, clrP, decB, done;
	reg [2:0] state;
	parameter s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100;

	always @(posedge clk)
		begin
			case (state)
				s0: if (start) state <= s1;

axayjha

module datapath (eqz, LdA, LdB, LdP, clrP, decB, data_in, clk);
	input LdA, LdB, LdP, clrP, decB, clk;
	input [15:0] data_in;
	output eqz;
	wire [15:0] x, y, z, Bout, Bus;

	PIPO_R1 A (x, data_in, LdA, clk);
	PIPO_R2 P (y, z, LdP, clrP, clk);
	counter B (Bout, data_in, LdB, decB, clk);
	add AD (z, x, y);

axayjha

module counter (dout, din, ld, dec, clk);
	input [15:0] din;
	input ld, dec, clk;
	output reg [15:0] dout;

	always @(posedge clk)
		if (ld) dout <= din;
		else if (dec) dout <= dout - 1;
		
endmodule		

axayjha

module comparator (eqz, data);
	input [15:0] data;
	output eqz;
	assign eqz = (data == 0);
endmodule

axayjha

module add (out, in1, in2);
	input [15:0] in1, in2;
	output reg [15:0] out;
	always @(*)
		out = in1 + in2;
endmodule		

axayjha

module PIPO_R2 (dout, din, ld, clr, clk);
	input [15:0] din;
	input ld, clr, clk;
	output reg [15:0] dout;

	always @(posedge clk)
                // if clear signal is on, set register value to 0
		if (clr) dout <= 16'b0;
                // else if load signal is on, load new data
		else if (ld) dout <= din;

axayjha

module PIPO_R1 (dout, din, ld, clk);
	input [15:0] din;
	input ld, clk;
	output reg [15:0] dout;

	always @(posedge clk)
                // if load signal is on, load new data
		if (ld) dout <= din;
endmodule