Starting point: In IREE/Linalg,
- There ultimately won't be any packing ops (because anything resembling a packing op will get fused into the producer).
- But there will still be a packed layout (because the repeated N^3 accesses to N^2 data mean that it is an optimization to materialize the ultimate matmul lhs/rhs operands as buffers, and efficiency considerations mean that the layout of these buffers will have some block structure).
So a priori, at some stage of lowering just before codegen, our matmuls have as lhs/rhs inputs some materialized buffers in some possibly nontrivial layouts.
I started thinking about how much we can restrict layouts. If you look at classic GEMM papers like the BLIS papers, it can scare you because they make it sound like you need N nested levels of blocks, and some of that may need to reflect the CPU cache hierarchy.
And so in particular that makes it sound like the introduction of packed layouts is adding new degrees of freedom, new dimensions to the search space in th