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@bjacob
bjacob / README.md
Last active July 6, 2026 18:53
DBI-SuperCollider

DBI SuperCollider MVP Plan

Goal

Demonstrate SuperCollider-style instrumentation of AMDGPU LDS accesses under rocJITsu DBI.

The concrete deliverable is an opt-in rocJITsu instrumentation mode that can catch at least some LDS races on selected tests. This is intentionally a race-exposure MVP, not a full happens-before sanitizer.

@bjacob
bjacob / dbi.md
Created July 3, 2026 19:29
DBI plan

rocJITsu DBI / waitcheck exploratory digest

Date: 2026-07-03

Repo inspected: /home/benoit/workspace/TheRock/rocm-systems

Refs checked

  • Current local HEAD: 63c36973da
  • Jakub's waitcheck branch: origin/users/kuhar/waitcheck
[2690860.263792] Out of memory: Killed process 2436488 (code) total-vm:1522820760kB, anon-rss:43396kB, file-rss:8kB, shmem-rss:32704kB, UID:1000 pgtables:4404kB oom_score_adj:300
[2690862.359207] systemd-journald[842]: Under memory pressure, flushing caches.
[2690862.382811] oom_reaper: reaped process 2436488 (code), now anon-rss:0kB, file-rss:0kB, shmem-rss:25832kB
[2690865.062934] systemd-journald[842]: Under memory pressure, flushing caches.
[2690894.206910] audit: type=1107 audit(1783106387.900:49786): pid=1990 uid=101 auid=4294967295 ses=4294967295 subj=unconfined msg='apparmor="DENIED" operation="dbus_method_call" bus="system" path="/org/freedesktop/NetworkManager" interface="org.freedesktop.DBus.Properties" member="GetAll" mask="send" name=":1.13" pid=2446835 label="snap.firefox.firefox" peer_pid=2107 peer_label="unconfined"
exe="/usr/bin/dbus-daemon" sauid=101 hostname=? addr=? terminal=?'
[2690954.211506] audit: type=1107 audit(1783106447.905:49787): pid=1990 uid=101 auid=429496729

How algebraic-fpsan represents transcendentals

Scratch discussion notes. Answers: "if transcendentals get no reserved slots, how are they represented at all?"

Short answer

A transcendental result is represented by an ordinary ring residue — a number in $[0,p)$ — produced by a stateless keyed hash of (which transcendental, input residue). It is not stored in any reserved/sentinel

An algebraic alternative to FPSan: the residue homomorphism $\mathbb{Z}[1/2] \to \mathbb{F}_p$

Working notes. Audience: us. Builds on understanding-fpsan.md.

0. The one-sentence difference from FPSan

FPSan encodes a float by a scrambling bijection $\varphi$ of its bit pattern and then does arithmetic in the payload ring $\mathbb{Z}/2^{w}$. That map is not a ring homomorphism: $\varphi(x{+}y) \neq \varphi(x){+}\varphi(y)$. The ring laws hold because the payload operations are the ring operations and the

New project: FPSan.
Create a fpsan directory under workspace/.
In it, clone out the Triton git repository: https://github.com/triton-lang/triton.git
Stick to https for the remote.
We want to study a new sanitizer developed there, named fpsan. It rewrites floating-point arithmetic into purely integer-arithmetic, in a way that completely alters the numerical outputs, so this is not at all trying to be useful computationally. Instead, the motivation comes from a key property that this compiler rewrite satisfies: if the input floating-point programs only differ by "fast-math-style" rewrites like rewriting a+(b+c) into (a+b)+c (which is not a technically correct rewrite of a floating-point program, due to lack of associativity of FP addition) then the fpsan-rewritten programs are exactly equivalent integer-arithmetic programs: they may only differ by a rewrite of the form a+(b+c) into (a+b)+c but now on modular integer arithmetic, where this rewrite is exact.

[mlir][vector] Gather1DToConditionalLoads emits ~8x more integer ops per lane for rank>1 memrefs after #184706

Summary

Commit 305dc4e5a9a6 (PR #184706, "Lower vector.gather with delinearization approach") makes Gather1DToConditionalLoads unconditionally compute load indices for rank > 1 memrefs as

@bjacob
bjacob / DATA-TILING-CPU-VS-GPU.md
Last active April 9, 2026 16:28
IREE data-tiling: CPU vs GPU differences, April 9 snapshot

Data-tiling: CPU (llvm-cpu, znver5) vs GPU (rocm, gfx950)

The commands in README.md build the same matmul_bf16.mlir with --iree-dispatch-creation-data-tiling and full --mlir-print-ir-before-all / --mlir-print-ir-after-all logs redirected to log-cpu.mlir and log-gpu.mlir in the parent directory.

This folder (ai-generated/) holds the extracted slice files, the extractor script, and this note.

Common front end (shared pass sequence)

For the first 347 paired Before/After dumps, CPU and GPU logs list the same passes in the same order. Through that region, both targets see the same data-tiling story in the dispatch/stream pipeline:

Hello,

1. The preexisting potential undefined behavior in FP conversions.

There is an edge case in the specification potentially allowing for value-dependent undefined behavior (henceforth UB) in floating-point conversions:

7.3.10 [conv.double] #2 says:

If the source value can be exactly represented in the destination type, the result of the conversion is that exact representation. If the source value is between two adjacent destination values, the result of the conversion is an implementation-defined choice of either of those values. Otherwise, the behavior is undefined.

Hello,
1. The preexisting potential undefined behavior in FP conversions.
There is an edge case in the specification potentially allowing for value-dependent undefined behavior (henceforth UB) in floating-point conversions:
7.3.10 [conv.double] #2 says:
If the source value can be exactly represented in the destination type, the result of the conversion is that exact representation. If the source value is between two adjacent destination values, the result of the conversion is an implementation-defined choice of either of those values. Otherwise, the behavior is undefined.