Olaf Bernstein camel-cdr

The implementation complexity of vcompress.vm for large vector length and higher LMUL has been somewhat debated.

Existing implementations exhibit very poor scaling when dealing with larger operands:

	VLEN	e8m1	e8m2	e8m4	e8m8
c906	128	3	10	32	136
c908	128	3	10	32	139
c920	128	0.5	2.4	5.4	20.0
X60	256	3	10	32	139

cycles for 128 iterations of a spilling function (see complex_reduction):

                  XiangShan            XuanTie C908           SpacemiT X60
             5 spills | 14 spills | 5 spills | 14 spills | 5 spills | 14 spills
stack:           2309 |      3439 |     6898 |     18220 |     6693 |     17734
fp:              3193 |      7037 |     8483 |     32325 |     8248 |     31434
rvv_best:        3210 |      7095 |     8459 |     32343 |     8250 |     31448
rvv_zvl128b:      N/A |      7837 |     9532 |     36685 |     9290 |     35550
rvv_worst_merge: 4572 |     23013 |    12042 |     50894 |    11722 |     49232
rvv_worst_slide: N/A | 36385 | 12975 | 55166 | 12379 | 53113

RISC-V Vector Extension for Integer Workloads: An Informal Gap Analysis

Note: To verify my RVI membership and idenity on this otherwise semi anonymous account: I'm Olaf Bernstein, you should be able to view my sig-vector profile, if you are a member of the vector SIG.

The goal of this document is to explore gaps in the current RISC-V Vector extensions (standard V, Zvbb, Zvbc, Zvkg, Zvkn, Zvks), and suggest instructions to fill these gaps. My focus lies on application class processors, with the expectation that suggested instructions would be suitable to become mandatory or optional instructions in future profiles.

I'll assume you are already familiar with RVV, if not, here is a great introduction and here the latest RISC-V ISA manual.

RVA23 vs ARMv9 a Small Experiment

I was curious to see how RISC-V and ARM compare in terms of dynamic instruction count and code density, so I devised a small experiment to compare the ISAs.

As a test codebase, I choose the chibicc C compiler, because it's a medium size project and is quite easy to compile. To benchmark chibicc I just used it to compile itself, which should be a quite realistic workload to simulate a complex non-regular application. I merged all files into one and did some minor modifications, the code can be found at: https://godbolt.org/z/xr3nEW8Wf

You may notice that I added unoptimized scalar implementations of the mem* and str* functions from musl-libc. This is because I decided to not include SIMD code in this experiment, in an effort to remove more unknown variables and focus on comparing the base ISAs.

Visualizing the RISC-V Instruction Set

Earlier today, I came across the blog post "Visualizing the ARM64 Instruction Set" and got inspired to give it a shot my self.

After hacking together a quick script and fiddling with the bit order and colors for way too long, I managed to create a decent visualization of the RISC-V instruction encoding. You can find my code below.

The following graphics cover the 64-bit part of the RISC-V ISA, including all ratified 64-bit extensions, with opcodes extracted from the riscv/riscv-opcodes repo.

I mapped the opcodes to 2D coordinates with a Morton space-filling curve.

	FROM continuumio/miniconda3

	RUN apt-get update \
	&& apt-get install -y build-essential wget git unzip python3 sudo file python3-vcstools libboost-dev vim cpio binutils \
	&& apt-get clean \
	&& rm -rf /var/lib/apt/lists/*

	RUN conda install conda-lock=1.4

	RUN git clone https://github.com/tenstorrent/chipyard/

	/*
	* Using the Ziggurat Method for Sampling Random Coordinates From a Unit Circle
	* by Olaf Bernstein <camel-cdr@protonmail.com>.
	* Distributed under the MIT license, see license at the end of the file.
	* New versions available at https://github.com/camel-cdr/cauldron
	*
	* Table of contents ===========================================================
	*
	* 1. Introduction
	* 1.1 API Overview

	git clone --depth=1 https://github.com/llvm/llvm-project
	cd llvm-project
	mkdir build
	cd build
	cmake -DCOMPILER_RT_BUILD_BUILTINS=ON -DCOMPILER_RT_BUILD_SANITIZERS=ON -DCOMPILER_RT_BUILD_XRAY=OFF -DCOMPILER_RT_BUILD_LIBFUZZER=ON -DCOMPILER_RT_BUILD_PROFILE=OFF -DCMAKE_C_COMPILER=$(which riscv64-linux-gnu-gcc) -DCMAKE_CXX_COMPILER=$(which riscv64-linux-gnu-g++) -DCMAKE_AR=$(which riscv64-linux-gnu-ar) -DCMAKE_NM=$(which riscv64-linux-gnu-nm) -DCMAKE_RANLIB=$(which riscv64-linux-gnu-ranlib) -DCMAKE_C_COMPILER_TARGET="riscv64-linux-gnu" -DCOMPILER_RT_DEFAULT_TARGET_ONLY=ON -DCMAKE_C_FLAGS="-march=rv64gcv" -DCMAKE_CXX_FLAGS="-march=rv64gcv" -DCMAKE_BUILD_TYPE=Release ../compiler-rt
	make -j$(nproc)