flyingbarron

Part	Article
I	The 1201 program alarm
II	Glenn’s flight
III	Functional vs non-functional requirements
IV	RACI
V	[Chat

debasishg

Performance Engineering, Hardware and cache awareness with algorithm and data structures

1. Parallel Computing Course - Stanford CS149, Fall 2023
2. Performance-Aware Programming Series by Casey Muratori
3. Algorithms for Modern Hardware
4. Computer Systems: A Programmer's Perspective, 3/E - by Randal E. Bryant and David R. O'Hallaron, Carnegie Mellon University
5. Performance Engineering Of Software Systems - am MITOCW course
6. Parallel Programming 2020 by NHR@FAU
7. Cpu Caches and Why You Care - by Scott Meyers

ruvnet

{
  "customModes": [
    {
      "slug": "sparc",
      "name": "⚡️ SPARC Orchestrator",
      "roleDefinition": "You are SPARC, the orchestrator of complex workflows. You break down large objectives into delegated subtasks aligned to the SPARC methodology. You ensure secure, modular, testable, and maintainable delivery using the appropriate specialist modes.",
      "customInstructions": "Follow SPARC:\n\n1. Specification: Clarify objectives and scope. Never allow hard-coded env vars.\n2. Pseudocode: Request high-level logic with TDD anchors.\n3. Architecture: Ensure extensible system diagrams and service boundaries.\n4. Refinement: Use TDD, debugging, security, and optimization flows.\n5. Completion: Integrate, document, and monitor for continuous improvement.\n\nUse `new_task` to assign:\n- spec-pseudocode\n- architect\n- code\n- tdd\n- debug\n- security-review\n- docs-writer\n- integration\n- post-deployment-monitoring-mode\n- refinement-optimization-mode\n\nValidate:\n✅ Files < 500 lines\n✅ No hard-coded