daxfohl’s gists

daxfohl / fs_async.fs

Last active August 29, 2015 14:10

	open System.Diagnostics

	let N = 100000
	let calc_sync i = i % 10

	let sum_sync() =
	async {
	let ints = Seq.initInfinite calc_sync \|> Seq.take N
	return Seq.sum ints
	}

daxfohl / gist:328641f74b00aa7124c5

Created November 4, 2014 13:54

regex for f# too many params

let \w+ (\w+ |\(.*\) ){4,}=

daxfohl / gist:6143558

Last active December 20, 2015 13:59

Speed test

	using System;
	using System.Collections.Generic;
	using System.Diagnostics;
	using System.Linq;

	namespace ConsoleApplication195
	{
	static class Program
	{
	static void Main()

daxfohl / processor.v

Last active December 17, 2015 07:48

Verilog sample for reversing an array

	module processor(clk, rxReady, rxData, txBusy, txStart, txData);
	input clk;
	input[7:0] rxData;
	input rxReady;
	input txBusy;
	output reg txStart;
	output reg[7:0] txData;

	localparam READ=0, SOLVING=1, WRITE1=2, WRITE2=3;
	localparam LEN = 10;

daxfohl / SudokuProcedural.cs

Last active December 10, 2015 11:39

	using System;

	// ReSharper disable JoinDeclarationAndInitializer
	// ReSharper disable InconsistentNaming

	namespace SudokuProcedural
	{
	static class Program
	{
	static void Main()

daxfohl / gist:4414011

Last active December 10, 2015 09:28

sudoku all

	module trigger(clk, rxReady, rxData, txBusy, txStart, txData);
	input clk;
	input[7:0] rxData;
	input rxReady;
	input txBusy;
	output reg txStart;
	output reg[7:0] txData;

	localparam READ=0, SOLVING=1, WRITE1=2, WRITE2=3;
	localparam ROW=0, COL=1, SQ=2;

daxfohl / gist:4375461

Last active December 10, 2015 03:38

9-row LR and SI all regions in one-shot (51K logic elements, 2hr compile)

	module trigger(clk, rxReady, rxData, txBusy, txStart, txData);
	input clk;
	input[7:0] rxData;
	input rxReady;
	input txBusy;
	output reg txStart;
	output reg[7:0] txData;

	integer countIO;
	reg[8:0] data[0:8][0:8];

daxfohl / gist:4010101

Created November 4, 2012 03:57

fpga reverse memory

	module trigger(clk, rxReady, rxData, txBusy, txStart, txData, memAddr, memWriteEnable, memWrite, memRead);
	input clk;
	input [7:0] rxData;
	input rxReady;
	input txBusy;
	output reg txStart;
	output reg[7:0] txData;
	output reg[24:0] memWrite;
	output reg[9:0] memAddr;
	output reg memWriteEnable;

daxfohl / postsave.bat

Created October 26, 2012 16:22

Postsave that distinguishes prints and regular images

	set str1=%1
	if x%str1:prints=%==x%str1% goto :regular
	:prints
	copy %1.jpg "D:\smilebooth\network\eventfolder\prints\"
	goto :end
	:regular
	resizer titos.png %1.jpg %1_overlay.jpg
	copy %1_overlay.jpg "D:\smilebooth\network\eventfolder\"
	goto :end
	:end

daxfohl / ants.clj

Created October 10, 2012 20:10 — forked from dribnet/ants.clj

Clojure ant sim from Rich Hickey

	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Ant sim ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	; Copyright (c) Rich Hickey. All rights reserved.
	; The use and distribution terms for this software are covered by the
	; Common Public License 1.0 (http://opensource.org/licenses/cpl.php)
	; which can be found in the file CPL.TXT at the root of this distribution.
	; By using this software in any fashion, you are agreeing to be bound by
	; the terms of this license.
	; You must not remove this notice, or any other, from this software.

	; Note: This code cannot run for very long on clojure 1.3 because

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