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instruction test sequences "scraped" from https://github.com/dougallj/applecpu / https://dougallj.github.io/applecpu/firestorm.html
A53 A520 A720 X4
1.00 1.00 0.50 0.50 STR_reg_uxtw_64.html Test 2: throughput
3.00 4.00 2.00 2.00 SQSUB_v_4S.html Test 2: Latency 1->2
3.00 4.00 2.00 2.00 SQSUB_v_4S.html Test 3: Latency 1->3
1.00 0.50 0.50 0.25 SQSUB_v_4S.html Test 4: throughput
3.00 8.01 6.00 7.00 FCVTZS_s_fp_D_to_W.html Test 2: Latency 1->2 roundtrip
1.00 1.00 1.00 1.00 FCVTZS_s_fp_D_to_W.html Test 3: throughput
1.00 3.00 2.00 2.00 SLI_s_D.html Test 2: Latency 1->1
@dzaima
dzaima / generate.c
Last active February 20, 2026 12:44 — forked from camel-cdr/README.md
Visualizing the RISC-V Instruction Set
#ifndef SEL
#define SEL 2 // select between first and second image
#endif
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <immintrin.h>