jboner

Latency Comparison Numbers (~2012)
----------------------------------
L1 cache reference                           0.5 ns
Branch mispredict                            5   ns
L2 cache reference                           7   ns                      14x L1 cache
Mutex lock/unlock                           25   ns
Main memory reference                      100   ns                      20x L2 cache, 200x L1 cache
Compress 1K bytes with Zippy             3,000   ns        3 us
Send 1K bytes over 1 Gbps network       10,000   ns       10 us
Read 4K randomly from SSD*             150,000   ns      150 us          ~1GB/sec SSD

tlberglund

Distributed Systems Reading List

Links for Further Reading

• You Can't Sacrifice Partition Tolerance
• Twitter conversation with Jay Kreps about Vector Clocks
• Why Cassandra Doesn't Need Vector Clocks
• Why Vector Clocks are Easy
• Why Vector Clocks are Hard
• Cache is the New RAM
• Neat Algorithms: Paxos

vasanthk

System Design Cheatsheet

Picking the right architecture = Picking the right battles + Managing trade-offs

Basic Steps

1. Clarify and agree on the scope of the system

• User cases (description of sequences of events that, taken together, lead to a system doing something useful)
  • Who is going to use it?
  • How are they going to use it?