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Febriyanto Nugroho febnug

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; generate random numbers
in al,40h
rdtsc
xadd ax,bp
imul ax, -7
@febnug
febnug / gabeut.asm
Last active February 19, 2022 08:31
X: les dx,[bx+si]
xchg ax,cx
stosw
jmp X-8
aad -1 ; add al,-1*ah
xor dx,dx ; zf = 0
div sp ; or any other reg that <> 0
jnz .AMD ; on any div/idiv operation ZF flag will not be changed on Intel but will be set on AMD
.Intel:
adc ax,[bx+si] ; dw 0x13
xchg bx,ax
mov es,[si]
lodsb
int 0x10
@febnug
febnug / x.asm
Last active April 14, 2022 00:07
let's RE this stuff
org 0x100
xchg bp,ax
imul dx,[bp+si+101],58*457 ; maybe playing with that value
inc di
outsb
add sp,[si]
mov dx,si
int 33
@febnug
febnug / lol.asm
Created April 18, 2022 12:49
wut?
org 100h
xchg bp,ax
imul ax,[bp+si+400],50*10
sub ax,14
int 29h
ret
@febnug
febnug / transgender.asm
Created April 26, 2022 01:14
a transgender flag
org 100h
mov al,0x13
int 0x10
les bp,[bx]
mov al,11
mov ch,50
rep stosb
mov al,13
mov ch,50
org 100h
mov al,12h
int 10h
;mov ax,0001h
xchg si,ax
xchg ah,al
int 33h