Legend:
- (K)ernel or (U)ser
- (S)hared or (P)rivate
- (F)irmware or (G)PU or (X)Both
- (KSF): Buffer info struct (maybe should be KPF?)
- (KSF): Block control pointers
- (KSF): Use counter
Hoshino Lina hoshinolina
hoshinolina
/ agx_core_mV_mW.txt
Created
November 1, 2022 10:25
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hoshinolina
/ agx_sram_mW_mV.txt
Last active
October 31, 2022 08:32
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hoshinolina
/ agx-coherency-and-tlbs.md
Last active
December 1, 2025 12:30
These are just some notes on my current understanding of the subtleties of the AGX memory model and the TLB/caching issues I'm seeing.
TLBI instructions do not broadcast to the GPU from EL1 with stage 2 translation enabled. That's it. That's what the bug was.
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