| #!/bin/bash | |
| # A script to configure Lattice iCE40 FPGA by SPI from Raspberry Pi | |
| # | |
| # Copyright (C) 2015 Jan Marjanovic <[email protected]> | |
| # | |
| # This program is free software: you can redistribute it and/or modify | |
| # it under the terms of the GNU General Public License as published by | |
| # the Free Software Foundation, either version 3 of the License, or | |
| # (at your option) any later version. |
| Jan@Jan-PC /tmp | |
| $ nios2-newlib-gen --custom "-O3" --verbose ./build ./lib | |
| Building Newlib may take a few minutes... Please be patient. | |
| Newlib Source Dir: /cygdrive/c/altera/14.1/nios2eds/bin/gnu/src/newlib-1.18 | |
| Newlib Build Dir: /tmp/build | |
| Newlib Install Dir: /tmp/lib | |
| Configuring newlib to build a smallc C library in /tmp/build/smallc... |
| #!/usr/bin/env python3 | |
| # -*- coding: utf-8 -*- | |
| ''' | |
| BMP Inspector: Prints BPM file information and pixel array statistics | |
| Copyright (C) 2015 Jan Marjanovic <[email protected]> | |
| This program is free software: you can redistribute it and/or modify | |
| it under the terms of the GNU General Public License as published by |
| // Copyright (C) 2014 Jan Marjanovic | |
| //`define DEBUG | |
| module filter #( | |
| parameter IO_B = #I0_B#, // input and output data width | |
| parameter INT_B = #INT_B#, // integer part of internal quotient | |
| parameter FRAC_B = #FRAC_B# // integer part of internal quotient | |
| ) ( |
This code snippet demonstrates a co-simulation of Verilog code and MyHDL code. The three modules here presents the absolute minimum for a co-simulation.
The counter_top.v is the top level module. It instantiates the counter module (found in file counter.v), which is the module we would like to evaluate. Also instantiated are the signals which are feed from and to MyHDL.
| #! /usr/bin/env python3 | |
| # -*- coding: utf-8 -*- | |
| ''' | |
| The VerilogBits provides Verilog-style representation of the numbers. | |
| Copyright (C) 2015 Jan Marjanovic <[email protected]> | |
| This program is free software: you can redistribute it and/or modify | |
| it under the terms of the GNU General Public License as published by |
| #include <linux/netlink.h> | |
| #include <linux/rtnetlink.h> | |
| #include <net/if.h> | |
| #include <stdio.h> | |
| #include <stdlib.h> | |
| #include <string.h> | |
| #include <sys/socket.h> | |
| #include <sys/types.h> | |
| #include <unistd.h> |
| A small example demonstrating issue when generating LaTeX (HTML is generated | |
| without any problems) with doxverilog. | |
| with line 7 in simple_submodule.v commented out: | |
| ------------------------------------------------ | |
| ➜ latex_bug git:(master) ✗ ls -l latex |
| #! /usr/bin/env python3 | |
| import dataclasses | |
| import enum | |
| import re | |
| from typing import List, Optional | |
| @dataclasses.dataclass | |
| class StratixVPart: |