jgibbard

import select, socket, sys, queue, time
from threading import Thread
from threading import Event
import logging

class TcpClient(Thread):
    def __init__(self, ipAddress, port, recvQueue, sendQueue, stopEvent):
        
        Thread.__init__(self)

jgibbard

jgibbard

from mmap import mmap
import time
import struct

LWFPGASLVS_OFST = 0xFF200000
LED_PIO_BASE = 0x3000
LED_SPAN = 0x10
KEY_BASE = 0x5000
KEY_SPAN = 0x10

jgibbard

#!/bin/bash 

# Python 2.7 and 2.6 install script for CentOS 7 
# Instructions mainly taken from tutorial by Daniel Eriksson
# https://danieleriksson.net/2017/02/08/how-to-install-latest-python-on-centos/ 

python27_version=2.7.15
python36_version=3.6.6
build_dir=python_build_temp
example_environment_dir=pythonEnv

jgibbard

# Functions to calculate APPROXIMATE range, bearing, and XY offset between two lat/long positions
# Uses the Haversine Formula 
# See http://www.movable-type.co.uk/scripts/latlong.html for more details

# Math library needed for cos, sine, atan2, sqrt, degrees, and radians
import math 

# This is the mean radius of the earth in metres
EARTH_RADIUS = 6371000.0

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//Emulates the output of a WWII German Enigma encryption machine

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

//#define DEBUG
#define MAX_MESSAGE_LENGTH 100

//Strut Prototypes

jgibbard

--VHDL VGA PONG demo
--An FPGA version of the classic pong game
--Score counts up to 9
--Right player uses buttons 0 and 1
--Left player uses Switch 0 (Much harder!)
--Button 2 resets the game and score

library ieee; use ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

entity FPGA_VGA is 

jgibbard

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all;

--This example shows how different speed signals can be created using both a counter method and a PLL
--PLL are very powerful and can be used to generate both fast or slower clk speeds as well as changing the phase of the signal.
--There are a limited amount of PLLs on an FPGA however a single PLL block in the FPGA can often be used to generate several different frequencies.

entity pll_test is port (
	CLOCK_50 : in std_logic;
	SW			: in std_logic_vector(9 downto 0);
	LEDG		: OUT std_logic_vector(9 downto 0)

jgibbard

<?xml version="1.0" encoding="UTF-8" ?>
<project>
    <gatt in="gatt.xml" />
    <hardware in="hardware.xml" />    
    <script in="frisbee.bgs" />
    <image out="BLE112.hex" />  
    <device type="ble112" />
	<boot fw="bootuart" />
</project>

jgibbard

/* 
 * File:   LCD_LIB.c
 * Author: James Gibbard
 * Description: Display library for operating 16x2 Hitachi HD44780 type displays
 * Created on 24 April 2013, 15:23
 */

#include <xc.h>
#include "LCD_LIB.h"
#include <stdio.h>