Skip to content

Instantly share code, notes, and snippets.

View jjcarrier's full-sized avatar

Jon Carrier jjcarrier

9 followers · 0 following
  • New Hampshire, USA
View GitHub Profile
@jjcarrier
jjcarrier / PWM.vhd
Last active March 8, 2022 22:34
A parameterized PWM module written in VHDL
-- Written By Jon Carrier
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity PWM is
generic (
prescale: integer := 0; --frequency(PWM_clk)=frequency(i_CLK/(prescale+1))
@jjcarrier
jjcarrier / adc.v
Created May 3, 2012 23:29
MCP3002 ADC Module
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Jon Carrier
//
// Create Date: 13:47:10 12/03/2009
// Design Name: MCP3002 ADC SPI
// Module Name: adc
// Project Name: MCP3002 ADC SPI
// Target Devices: MCP3002, Spartan3E
// Tool versions: ISE 11
@jjcarrier
jjcarrier / adc.v
Created May 3, 2012 23:20
MCP3002 ADC Module (Interlaced)
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Jon Carrier
//
// Create Date: 13:47:10 12/03/2009
// Design Name: MCP3002 ADC SPI
// Module Name: adc
// Project Name: MCP3002 ADC SPI
// Target Devices: MCP3002, Spartan3E
// Tool versions: ISE 11
@jjcarrier
jjcarrier / fft_reconstruct.m
Created February 19, 2012 18:28
A basic example of reconstructing FFT frequency axis
% A simple example of how to reconstruct
% the frequency components from an FFT
%% Clean up the workspace
clear all;
close all;
clc;
%% Create the initial parameters
Window=5; %Set how long in time to sample + and -
Fs=100; %Set the sampling frequency
@jjcarrier
jjcarrier / sweep.cpp
Created February 19, 2012 18:22
sweep routine
void sweep(){
radio.mute();
Metrics RSQ;
Serial.print("SCAN_BEGIN:");
for(word i=6400;i<=10800;i+=10){
Serial.print(i,DEC);
Serial.print(":");
radio.tuneFrequency(i);
radio.getRSQ(&RSQ);
Serial.print(RSQ.SNR,DEC);
@jjcarrier
jjcarrier / zerocrossings.m
Created February 19, 2012 18:18
Zero-Crossings example
clear all;
close all;
clc;
tArray=0:.01:4;
%Add some noise for good measure
noise=.1.*randn(1,length(tArray));
vArray=sin(tArray).*sin(3*pi.*tArray)+noise;
%computes the difference of each neighboring
%element in the boolean expression
test=diff(vArray>=0);
@jjcarrier
jjcarrier / FPGA_2_ShiftReg.v
Last active April 16, 2017 18:35
THIS CODE HAS BEEN ADDED AS A REPO @ https://github.com/jjcarrier/FPGA_2_ShiftReg
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Carrier Frequency, Inc.
// Engineer: Jon Carrier
//
// Create Date: 21:33:11 01/26/2012
// Design Name:
// Module Name: FPGA_2_ShiftReg
// Project Name:
// Target Devices:
@jjcarrier
jjcarrier / FPGA_2_LCD.v
Created December 28, 2011 18:40
A simple character LCD controller core written in Verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Carrier Frequency, Inc.
// Engineer: Jon Carrier
//
// Create Date: 21:33:11 06/17/2011
// Design Name:
// Module Name: FPGA_2_LCD
// Project Name:
// Target Devices: