Osman Karaketir karaketir16

Simple CPU Instruction Set

Overview

12-bit registers: R0--R7 (3-bit register indices).
R0 is hardwired to zero.
All instructions are 16 bits.
Instruction groups by opcode patterns:
- 0000 (0x0): Arithmetic & Shift Instructions (with funct field)
- 0001 (0x1): Logical Instructions (with funct field)

The machine level has the highest privileges and is the only mandatory privilege level for a RISC-V hardware platform. Code run in machine-mode (M-mode) is usually inherently trusted, as it has low-level access to the machine implementation. M-mode can be used to manage secure execution environments on RISC-V. User-mode (U-mode) and supervisor-mode (S-mode) are intended for conventional application and operating system usage respectively.

The lock feature of the optional PMP facility can provide some limited protection even with only M-mode implemented.

The SYSTEM major opcode is used to encode all privileged instructions in the RISC-V ISA. These can be divided into two main classes: those that atomically read-modify-write control and status registers

	import os
	import sys
	import shutil
	import hashlib
	from pathlib import Path

	def get_models_path(custom_path=None):
	if custom_path:
	return custom_path


	from: https://developer.lsst.io/cpp/style.html

	6.3. Comments
	Documenting C++ Code Documentation Standards contains most of the rules about comments. A few detailed rules are listed here.

	6-22. Tricky code SHOULD not be commented but rewritten!
	Sometimes tricky code is unavoidable, but if the choice is between being clever and being clear, choose clarity.

	6-23. All comments MUST be written in English.