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@larkmjc
larkmjc / ticket-lock-riscv.s
Last active June 2, 2021 23:40
Queued ticket lock description in English and some RISC-V assembly for a possible implementation
#pragma once
# Ticket Lock
#
# Ticket locks are fair spinlocks that order acccess on a first-in,
# first-out basis. The lock is composed of a head counter and a tail
# counter. The head counter indicates the ticket number of the current
# lock owner. The tail counter indicates the last issued ticket number.
# To acquire the lock, the acquiring thread atomically increments the
# tail counter to assign itself a ticket number. It then waits until
@larkmjc
larkmjc / atomic_latency.cc
Created December 12, 2020 07:35
atomic memory interlock latency benchmark
/*
* atomic memory interlock latency benchmark (public domain)
* author: Michael Clark <michaeljclark@mac.com>
* c++ -pthread -O2 atomic_latency.cc -o atomic_latency
*/
#include <cstdio>
#include <thread>
#include <atomic>
#include <chrono>
@larkmjc
larkmjc / please-license.c
Created November 21, 2020 08:15
PLEASE LICENSE is a software license somewhere in between the ISC license and public domain.
/*
* PLEASE LICENSE 11/2020, John Smith <john.smith@example.com>
*
* All rights to this work are granted for all purposes, with exception of
* author's implied right of copyright to defend the free use of this work.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
@larkmjc
larkmjc / workmule.cc
Last active November 11, 2020 19:03
C++ threaded worker pool that executes work-items from a queue
// See LICENSE for license details.
#include <vector>
#include <atomic>
#include <thread>
#include <mutex>
#include <memory>
#include <functional>
#include <condition_variable>
@larkmjc
larkmjc / ftkitty.cc
Last active October 30, 2020 04:43
ftkitty rasterizes text using FreeType and HarfBuzz and outputs using kitty image protocol
/*
* ftkitty - program that outputs text using kitty image protocol
*
* meet `ftkitty`, a tiny example emitting graphics to the terminal
* using #FreeType, #HarfBuzz, and the #kitty graphics protocol.
* this is possible with ImageMagick and icat, but ftkitty is smaller
* and mostly it's just an experiment with terminal protocols.
*
* g++ -O2 examples/ftkitty.cc $(pkg-config --libs freetype2 --libs harfbuzz
* --cflags freetype2 --cflags harfbuzz) -o build/ftkitty
@larkmjc
larkmjc / intersection.patch
Created February 26, 2020 21:36
Perform 2D rectangle intersection test and return topology classes
commit ac3c81578e760af11732da8f925b87ba7b1f70be
Author: Michael Clark <michaeljclark@mac.com>
Date: Tue Feb 25 10:45:10 2020 +1300
Perform 2D rectangle intersection test and return topology classes
diff --git a/src/geometry.h b/src/geometry.h
new file mode 100644
index 000000000000..1b5d890c2f58
--- /dev/null
--- linux-4.19-rc8.orig/arch/riscv/kernel/setup.c 2018-10-15 18:20:24.000000000 +1300
+++ linux-4.19-rc8/arch/riscv/kernel/setup.c 2018-10-19 00:25:54.571772704 +1300
@@ -227,7 +227,9 @@
setup_bootmem();
paging_init();
unflatten_device_tree();
+#ifdef CONFIG_SWIOTLB
swiotlb_init(1);
+#endif
@larkmjc
larkmjc / misaligned_atomics.c
Last active October 23, 2024 01:21
Demonstrates torn loads for misaligned atomics
#include <stdio.h>
#include <stdlib.h>
#include <stdatomic.h>
#include <limits.h>
#include <pthread.h>
/*
* Intel® 64 and IA-32 Architectures Software Developer’s Manual
*
* Volume 3A - 8.1.1 Guaranteed Atomic Operations
@larkmjc
larkmjc / riscv-rvc-register-usage-histogram
Last active August 26, 2017 07:47
RISC-V RVC register usage histogram
NOTE: - indicates RVC accesible register
register usage histogram (gcc 7.0.1 20170321 experimental) -Os newlib
~~~~~~~~~~~~~~~~~~~~~~~~
1. a5 15.12% [1711277823] ---------------------------------------
2. a2 13.64% [1543505068] -----------------------------------
3. a7 10.38% [1174405192] ==========================
4. a4 8.95% [1012926250] -----------------------
5. a6 7.77% [878706830] ====================
6. t4 5.30% [599785556] =============
@larkmjc
larkmjc / sample-riscv-decoding-notation
Last active August 19, 2017 07:40
Sample RISC-V instruction decoding notation
u : { [31:12], [11:7] } -> { simm[31:12], rd[4:0] }
uj : { [31:12], [11:7] } -> { simm[20|10:1|11|19:12], rd[4:0] }
i : { [31:20], [19:15], [11:7] } -> { simm[11:0], rs1[4:0], rd[4:0] }
i_sh5 : { [24:20], [19:15], [11:7] } -> { imm[4:0], rs1[4:0], rd[4:0] }
i_sh6 : { [25:20], [19:15], [11:7] } -> { imm[5:0], rs1[4:0], rd[4:0] }
i_sh7 : { [26:20], [19:15], [11:7] } -> { imm[6:0], rs1[4:0], rd[4:0] }
i_csr : { [31:20], [19:15], [11:7] } -> { imm[11:0], rs1[4:0], rd[4:0] }
s : { [24:20], [19:15], [11:7] } -> { simm[11:5], rs2[4:0], rs1[4:0], simm[4:0] }
sb : { [24:20], [19:15], [11:7] } -> { simm[12|10:5], rs2[4:0], rs1[4:0],