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import dateutil.parser
import re
date_re = r'(-?(?:[1-9][0-9]*)?[0-9]{4})-(1[0-2]|0[1-9])-(3[01]|0[1-9]|[12][0-9])T(2[0-3]|[01][0-9]):([0-5][0-9]):([0-5][0-9])(\.[0-9]+)?(Z|[+-](?:2[0-3]|[01][0-9]):[0-5][0-9])?'
full_re = f'({date_re}) (\[(\d*)/\d*\]) (.*)'
match = re.compile(full_re).match
def process_log(lines):
last_date = None
total_time = 0
Baseline Clang: /home/luismarques/llvm-builds/llvm-build-2021-07-21-11-05-39-170dd6eb9c5/bin/clang (commit 170dd6eb9c54938b5ba9589b7d4905cc85f16258 2021-07-21 11:05:39)
Patched Clang: /home/luismarques/llvm-builds/llvm-build-2021-01-01-00-00-00-0f6feeb944e/bin/clang (commit 0f6feeb944ebed790916cb37caec6f7f11f50631)
CoreMark O3:
- Δ score: 0.0379%
- score: 0.9738 → 0.9741
- size: 6104 → 6108 (+4 bytes, 0.0655%)
build/coremark/coremark 100.066% +4 bytes
CoreMark O2:
@luismarques
luismarques / disable-trace-and-logging.diff
Created March 9, 2022 15:03
Ibex simple system: disable tracing and logging
diff --git a/examples/simple_system/ibex_simple_system.core b/examples/simple_system/ibex_simple_system.core
index a74ceee3..74c5f7dd 100644
--- a/examples/simple_system/ibex_simple_system.core
+++ b/examples/simple_system/ibex_simple_system.core
@@ -131,7 +131,6 @@ targets:
verilator:
mode: lint-only
verilator_options:
- - "-Wall"
# RAM primitives wider than 64bit (required for ECC) fail to build in
@luismarques
luismarques / gist:2ab5950051a08be0fadfe78f0bf6489f
Last active October 11, 2022 11:46
OpenTitan shadow call stack size impact
Format: (size differences include .text and read-only data, but not .bss)
% size increase | byte size increase | file
# Sorted by % size increase
0.68% 2112 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_ibex_functest_wycheproof_prog_fpga_cw310.elf
0.86% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_wycheproof_prog_fpga_cw310.elf
0.86% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_wycheproof_prog_sim_dv.elf
0.86% 2684 bin/sw/device/silicon_creator/lib/sigverify/mod_exp_otbn_functest_wycheproof_prog_sim_verilator.elf
0.91% 2860 bin/sw/device/silicon_creator/lib/sigverify/sigverify_dynamic_functest_wycheproof_prog_fpga_cw310.elf
@luismarques
luismarques / gist:af593391badc563c37c394f344c2ac7b
Created October 11, 2022 15:42
OpenTitan jump guards size impact
Format:
% size increase | byte size increase | file
# Sorted by % size increase
7.12% 2192 /home/luismarques/opentitan-build1/output1/execroot/lowrisc_opentitan/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/tests/flash_ctrl_ops_test_prog_fpga_cw310.elf
7.13% 2192 /home/luismarques/opentitan-build1/output1/execroot/lowrisc_opentitan/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/tests/flash_ctrl_ops_test_prog_sim_verilator.elf
7.14% 2196 /home/luismarques/opentitan-build1/output1/execroot/lowrisc_opentitan/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/tests/flash_ctrl_ops_test_prog_sim_dv.elf
7.35% 1760 /home/luismarques/opentitan-build1/output1/execroot/lowrisc_opentitan/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/tests/alert_handler_ping_timeout_test_prog_fpga_cw310.elf
7.38% 1764 /home/luismarques/opentitan-build1/output1/execroot/lowrisc_opentitan/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/tests/alert_handler_ping_timeout_test_prog_sim_dv.elf
@luismarques
luismarques / sival.py
Last active February 15, 2024 18:10
SiVal report
import warnings
warnings.simplefilter(action='ignore', category=FutureWarning)
import pandas as pd
# Load CSV data into a DataFrame
fn = 'SiVal Items - Update - 2024-02-15.csv'
df = pd.read_csv(fn, keep_default_na=False)
# We want only the remaining tests (ones without a bazel target)