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NuttX on Ox64 BL808: ECALL Log. See https://github.com/lupyuen/nuttx-ox64
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| [I][] | |
| [I][] ____ ____ __ __ _ | |
| [I][] / __ \ | _ \ / _|/ _|| | | |
| [I][] | | | |_ __ ) | ___ _ _| |_| |_ __ _| | ___ | |
| [I][] | | | | '_ \ / _ \ '_ \| _ < / _ \| | | | _| _/ _` | |/ _ \ | |
| [I][] | |__| | |_) | __/ | | | |_) | (_) | |_| | | | || (_| | | (_) | | |
| [I][] \____/| .__/ \___|_| |_|____/ \___/ \__,_|_| |_| \__,_|_|\___/ | |
| [I][] | | | |
| [I][] |_| | |
| [I][] | |
| [I][] Powered by BoufaloLab | |
| [I][] Build:11:52:04,Mar 6 2023 | |
| [I][] Copyright (c) 2023 OpenBouffalo team | |
| [I][] Copyright (c) 2022 Bouffalolab tea | |
| [I][] dynamic memory init success,heap s[I][LowLoad] D0 start... | |
| [I][LowLoad] low_load start... | |
| [I][LowLoad] Header at 0x5d5ff000 | |
| [I][LowLoad] Section dtb(1) - Start 0x5d5ff100, Size 14314 | |
| [I][LowLoad] Copying DTB to 0x51ff8000...0x51ffb7ea | |
| [I][LowLoad] Done! | |
| [I][LowLoad] Section OpenSBI(2) - Start 0x5d60f100, Size 109864 | |
| [I][LowLoad] Copying OpenSBI to 0x3ef80000...0x3ef9ad28 | |
| [I][LowLoad] Done! | |
| [I][LowLoad] Section Kernel(3) - Start 0x5d62f100, Size 315597 | |
| [I][LowLoad] Uncompressing Kernel to 0x50000[I][LowLoad] Done! | |
| [I][LowLoad] CRC: 00000000 | |
| [I][LowLoad] load time: 61313 us | |
| [I][LowLoad] etting PMP | |
| [I][LowLoad] Booting OpenSBI at 0x000000003ef80000 w0x51ff8000 | |
| OpenSBI v1.2 | |
| ____ _____ ____ _____ | |
| / __ \ / ____| _ \_ _| | |
| | | | |_ __ ___ _ __ | (___ | |_) || | | |
| | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |
| | |__| | |_) | __/ | | |____) | |_) || |_ | |
| \____/| .__/ \___|_| |_|_____/|____/_____| | |
| | | | |
| |_| | |
| Platform Name : Pine64 Ox64 (D0) | |
| Platform Features : medeleg | |
| Platform HART Count : 1 | |
| Platform IPI Device : aclint-mswi | |
| Platform Timer Device : aclint-mtimer @ 1000000Hz | |
| Platform Console Device : bflb_uart | |
| Platform HSM Device : --- | |
| Platform PMU Device : --- | |
| Platform Reboot Device : --- | |
| Platform Shutdown Device : --- | |
| Firmware Base : 0x3ef80000 | |
| Firmware Size : 200 KB | |
| Runtime SBI Version : 1.0 | |
| Domain0 Name : root | |
| Domain0 Boot HART : 0 | |
| Domain0 HARTs : 0* | |
| Domain0 Region00 : 0x00000000e4008000-0x00000000e400bfff (I) | |
| Domain0 Region01 : 0x00000000e4000000-0x00000000e4007fff (I) | |
| Domain0 Region02 : 0x000000003ef80000-0x000000003efbffff () | |
| Domain Region03 : 0x0000000000000000-0xffffffffffffffff (R,W,X) | |
| Domain0 Next Address : 0x0000000050000000 | |
| Domain0 Next Arg1 : 0x0000000051ff8000 | |
| Domain0 Next Mode : S-mode | |
| Domain0 SysReset : yes | |
| Boot HART ID : 0 | |
| Boot HART Domain : root | |
| Boot HART Priv Version : v1.11 | |
| Boot HART Base ISA : rv64imafdcvx | |
| Boot HART ISA Extensions : time | |
| Boot HART PMP Count : 8 | |
| Boot HART PMP Granularity : 4096 | |
| Boot HART PMP Address Bits: 38 | |
| Boot HART MHPM Count : 8 | |
| Boot HART MIDELEG : 0x0000000000000222 | |
| Boot HART MEDELEG : 0x000000000000b109 | |
| U-Boot 2023.04-rc2 (Mar 06 2023 - 11:48:40 +0000) | |
| DRAM: 64 MiB | |
| Core: 36 devices, 17 uclasses, devicetree: board | |
| MMC: mmc@20060000: 0 | |
| Loading Environment from FAT... Unable to read "uboot.env" from mmc0:2... | |
| Loading Environment from nowhere... OK | |
| In: serial@30002000 | |
| Out: serial@30002000 | |
| Err: serial@30002000 | |
| Net: | |
| Warning: emac@20070000 (eth0) using random MAC address - b2:37:99:2c:b9:e7 | |
| eth0: emac@20070000 | |
| Hit any key to stop autoboot: 0 | |
| switch to partitions #0, OK | |
| mmc0 is current device | |
| Scanning mmc 0:2... | |
| Found /extlinux/extlinux.conf | |
| Retrieving file: /extlinux/extlinux.conf | |
| Select the boot mode | |
| 1:.Pine64 0X64 Kernel | |
| 2:.Sipeed M1SDock Kernel | |
| Enter choice: 1:.Pine64 0X64 Kernel | |
| Retrieving file: /extlinux/../Image | |
| append: root=PARTLABEL=rootfs rootwait rw rootfstype=ext4 console=ttyS0,2000000 loglevel=8 earlycon=sbi | |
| Retrieving file: /extlinux/../bl808-pine64-ox64.dtb | |
| ## Flattened Device Tree blob at 51ff8000 | |
| Booting using the fdt blob at 0x51ff8000 | |
| Working FDT set to 51ff8000 | |
| Loading Device Tree to 0000000053f22000, end 0000000053f25fab ... OK | |
| Working FDT set to 53f22000 | |
| Starting kernel ... | |
| 123jh7110_copy_ramdisk: _edata=0x50400258, _sbss=0x50400290, _ebss=0x50408000, JH7110_IDLESTACK_TOP=0x50408c00 | |
| jh7110_copy_ramdisk: ramdisk_addr=0x50410288 | |
| jh7110_copy_ramdisk: size=8192000 | |
| ABCjh7110_kernel_mappings: map I/O regions | |
| mmu_ln_map_region: ptlevel=1, lnvaddr=0x50407000, paddr=0, vaddr=0, size=0x40000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=1, lnvaddr=0x50407000, paddr=0, vaddr=0, mmuflags=0x26 | |
| jh7110_kernel_mappings: map PLIC as Interrupt L2 | |
| mmu_ln_map_region: ptlevel=2, lnvaddr=0x50403000, paddr=0xe0000000, vaddr=0xe0000000, size=0x10000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe0000000, vaddr=0xe0000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe0200000, vaddr=0xe0200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe0400000, vaddr=0xe0400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe0600000, vaddr=0xe0600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe0800000, vaddr=0xe0800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe0a00000, vaddr=0xe0a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe0c00000, vaddr=0xe0c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe0e00000, vaddr=0xe0e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe1000000, vaddr=0xe1000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe1200000, vaddr=0xe1200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe1400000, vaddr=0xe1400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe1600000, vaddr=0xe1600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe1800000, vaddr=0xe1800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe1a00000, vaddr=0xe1a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe1c00000, vaddr=0xe1c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe1e00000, vaddr=0xe1e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe2000000, vaddr=0xe2000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe2200000, vaddr=0xe2200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe2400000, vaddr=0xe2400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe2600000, vaddr=0xe2600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe2800000, vaddr=0xe2800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe2a00000, vaddr=0xe2a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe2c00000, vaddr=0xe2c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe2e00000, vaddr=0xe2e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe3000000, vaddr=0xe3000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe3200000, vaddr=0xe3200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe3400000, vaddr=0xe3400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe3600000, vaddr=0xe3600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe3800000, vaddr=0xe3800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe3a00000, vaddr=0xe3a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe3c00000, vaddr=0xe3c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe3e00000, vaddr=0xe3e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe4000000, vaddr=0xe4000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe4200000, vaddr=0xe4200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe4400000, vaddr=0xe4400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe4600000, vaddr=0xe4600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe4800000, vaddr=0xe480000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe4a00000, vaddr=0xe4a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe4c00000, vaddr=0xe4c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe4e00000, vaddr=0xe4e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe5000000, vaddr=0xe5000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe5200000, vaddr=0xe5200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe5400000, vaddr=0xe5400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe5600000, vaddr=0xe5600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe5800000, vaddr=0xe5800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe5a00000, vaddr=0xe5a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe5c00000, vaddr=0xe5c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe5e00000, vaddr=0xe5e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe6000000, vaddr=0xe6000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe6200000, vaddr=0xe6200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe6400000, vaddr=0xe6400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe6600000, vaddr=0xe6600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe6800000, vaddr=0xe6800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe6a00000, vaddr=0xe6a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe6c00000, vaddr=0xe6c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe6e00000, vaddr=0xe6e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe7000000, vaddr=0xe7000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe7200000, vaddr=0xe7200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe7400000, vaddr=0xe7400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe7600000, vaddr=0xe7600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe7800000, vaddr=0xe7800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe7a00000, vaddr=0xe7a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe7c00000, vaddr=0xe7c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe7e00000, vaddr=0xe7e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe8000000, vaddr=0xe8000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe8200000, vaddr=0xe8200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe8400000, vaddr=0xe8400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe8600000, vaddr=0xe8600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe8800000, vaddr=0xe8800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe8a00000, vaddr=0xe8a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe8c00000, vaddr=0xe8c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe8e00000, vaddr=0xe8e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe9000000, vaddr=0xe9000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe9200000, vaddr=0xe9200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe9400000, vaddr=0xe9400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe9600000, vaddr=0xe9600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe9800000, vaddr=0xe9800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0x9a00000, vaddr=0xe9a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe9c00000, vaddr=0xe9c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xe9e00000, vaddr=0xe9e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xea000000, vaddr=0xea000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xea200000, vaddr=0xea200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xea400000, vaddr=0xea400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xea600000, vaddr=0xea600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xea800000, vaddr=0xea800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeaa00000, vaddr=0xeaa00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeac00000, vaddr=0xeac00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeae00000, vaddr=0xeae00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeb000000, vaddr=0xeb000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeb200000, vaddr=0xeb200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeb400000, vaddr=0xeb400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeb600000, vaddr=0xeb600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeb800000, vaddr=0xeb800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeba00000, vaddr=0xeba00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xebc00000, vaddr=0xebc00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xebe00000, vaddr=0xebe00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xec000000, vaddr=0xec000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xec200000, vaddr=0xec200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xec400000, vaddr=0xec400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xec600000, vaddr=0xec600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xec800000, vaddr=0xec800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeca00000, vaddr=0xeca00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xecc00000, vaddr=0xecc00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xece00000, vaddr=0xece00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xed000000, vaddr=0xed000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xed200000, vaddr=0xed200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xed400000, vaddr=0xed400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xed600000, vaddr=0xed600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xed800000, vaddr=0xed800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeda00000, vaddr=0xeda00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xedc00000, vaddr=0xedc00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xede00000, vaddr=0xede00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xee000000, vaddr=0xee000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xee200000, vaddr=0xee200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xee400000, vaddr=0xee400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xee600000, vaddr=0xee600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xee800000, vaddr=0xee800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeea00000, vaddr=0xeea00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeec00000, vaddr=0xeec00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xeee00000, vaddr=0xeee00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xef000000, vaddr=0xef000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xef200000, vaddr=0xef200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xef400000, vaddr=0xef400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xef600000, vaddr=0xef600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xef800000, vaddr=0xef800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xefa00000, vaddr=0xefa00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xefc00000, vaddr=0xefc00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50403000, paddr=0xefe00000, vaddr=0xefe00000, mmuflags=0x26 | |
| jh7110_kernel_mappings: connect the L1 and Interrupt L2 page tables for PLIC | |
| mmu_ln_setentry: ptlevel=1, lnvaddr=0x50407000, paddr=0x50403000, vaddr=0xe0000000, mmuflags=0x20 | |
| jh7110_kernel_mappings: map kernel text | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x50404000, vaddr=0x50200000, mmuflags=0x0 | |
| jh7110_kernel_mappings: map kernel data | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x50405000, vaddr=0x50400000, mmuflags=0x0 | |
| jh7110_kernel_mappings: connect the L1 and L2 page tables | |
| mmu_ln_setentry: ptlevel=1, lnvaddr=0x50407000, paddr=0x50406000, vaddr=0x50200000, mmuflags=0x20 | |
| jh7110_kernel_mappings: map the page pool | |
| mmu_ln_map_region: ptlevel=2, lnvaddr=0x50406000, paddr=0x50600000, vaddr=0x50600000, size=0x1400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x50600000, vaddr=0x50600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x50800000, vaddr=0x50800000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x50a00000, vaddr=0x50a00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x50c00000, vaddr=0x50c00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x50e00000, vaddr=0x50e00000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x51000000, vaddr=0x51000000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x51200000, vaddr=0x51200000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x51400000, vaddr=0x51400000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x51600000, vaddr=0x51600000, mmuflags=0x26 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50406000, paddr=0x51800000, vaddr=0x51800000, mmuflags=0x26 | |
| mmu_satp_reg: pgbase=0x50407000, asid=0x0, reg=0x8000000000050407 | |
| mmu_write_satp: reg=0x8000000000050407 | |
| nx_start: Entry | |
| up_irqinitialize: | |
| irq_attach: irq=0, isr=0x502083a4 | |
| irq_attach: irq=1, isr=0x502083a4 | |
| irq_attach: irq=2, isr=0x502083a4 | |
| irq_attach: irq=3, isr=0x502083a4 | |
| irq_attach: irq=5, isr=0x502083a4 | |
| irq_attach: irq=7, isr=0x502083a4 | |
| irq_attach: irq=4, isr=0x502083a4 | |
| irq_attach: irq=6, isr=0x502083a4 | |
| irq_attach: irq=8, isr=0x50208ef6 | |
| irq_attach: irq=9, isr=0x502083a4 | |
| irq_attach: irq=10, isr=0x502083a4 | |
| irq_attach: irq=11, isr=0x502083a4 | |
| irq_attach: irq=12, isr=0x502083a4 | |
| irq_attach: irq=13, isr=0x502083a4 | |
| irq_attach: irq=14, isr=0x502083a4 | |
| irq_attach: irq=15, isr=0x502083a4 | |
| irq_attach: irq=19, isr=0x502083a4 | |
| up_irq_enable: | |
| irq_attach: irq=17, isr=0x502081c0 | |
| up_enable_irq: irq=17 | |
| uart_register: Registering /dev/console | |
| work_start_lowpri: Starting low-priority kernel worker thread(s) | |
| riscv_swint: Entry: regs: 0x50408940 cmd: 2 | |
| up_dump_register: EPC: 000000005020186e | |
| up_dump_register: A0: 0000000000000002 A1: 0000000050400d08 A2: 000000005040a900 A3: 000000005040a900 | |
| up_dump_register: A4: 000000005040a2d0 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000003 | |
| up_dump_register: T0: 000000000000002e T1: 0000000000000000 T2: 00000000000001ff T3: 000000005040e030 | |
| up_dump_register: T4: 000000005040e028 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 0000000050400d08 S1: 8000000200046002 S2: 0000000050400e90 S3: 0000000050400cf8 | |
| up_dump_register: S4: fffffffffffffff3 S5: 0000000053fe2f98 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000053f7a15c S9: 0000000053fcf2e0 S10: 0000000000000001 S11: 0000000000000003 | |
| up_dump_register: SP: 0000000050408b50 FP: 0000000050400d08 TP: 0000000000000000 RA: 000000005020186e | |
| riscv_swint: SWInt Return: Context switch! | |
| up_dump_register: EPC: 0000000050201f22 | |
| up_dump_register: A0: 0000000000000000 A1: 0000000000000000 A2: 0000000000000000 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000000000 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000000000000 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040e800 FP: 0000000000000000 TP: 0000000000000000 RA: 0000000000000000 | |
| nx_start_application: Starting init task: /system/bin/init | |
| up_addrenv_create: textsize=0x15b80, datasize=0x584, heapsize=0x80000, addrenv=0x5040d560 | |
| mmu_ln_setentry: ptlevel=1, lnvaddr=0x50600000, paddr=0x50601000, vaddr=0x80100000, mmuflags=0x0 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50601000, paddr=0x50602000, vaddr=0x80100000, mmuflags=0x0 | |
| mmu_ln_setentry: ptlevel=2, lnvaddr=0x50601000, paddr=0x5061b000, vaddr=0x80200000, mmuflags=0x0 | |
| mmu_satp_reg: pgbase=0x50600000, asid=0x0, reg=0x8000000000050600 | |
| up_addrenv_select: addrenv=0x5040d560, satp=0x8000000000050600 | |
| mmu_write_satp: reg=0x8000000000050600 | |
| elf_symname: Symbol has no name | |
| elf_symvalue: SHN_UNDEF: Failed to get symbol name: -3 | |
| elf_relocateadd: Section 2 reloc 2: Undefined symbol[0] has no name: -3 | |
| up_exit: TCB=0x5040a900 exiting | |
| riscv_swint: Entry: regs: 0x5040e5a0 cmd: 1 | |
| up_dump_register: EPC: 000000005020838c | |
| up_dump_register: A0: 0000000000000001 A1: 000000005040a2d0 A2: 0000000000000010 A3: 0000000000000002 | |
| up_dump_register: A4: 000000005040e000 A5: 0000000000000000 A6: 0000000000000009 A7: fffffffffffffff8 | |
| up_dump_register: T0: 000000000000002e T1: 000000000000006a T2: 00000000000001ff T3: 000000000000006c | |
| up_dump_register: T4: 0000000000000068 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 0000000050400e90 S1: 000000005040a900 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040e7b0 FP: 0000000050400e90 TP: 0000000000000000 RA: 000000005020838c | |
| riscv_swint: SWInt Return: Context switch! | |
| up_dump_register: EPC: 0000000050201f22 | |
| up_dump_register: A0: 0000000000000000 A1: 0000000000000000 A2: 0000000000000000 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000000000 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000000000000 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040c800 FP: 0000000000000000 TP: 0000000000000000 RA: 0000000000000000 | |
| riscv_swint: Entry: regs: 0x5040c540 cmd: 2 | |
| up_dump_register: EPC: 000000005020342c | |
| up_dump_register: A0: 0000000000000002 A1: 000000005040a2d0 A2: 000000005040d5e0 A3: 0000000050400e90 | |
| up_dump_register: A4: 0000000000000064 A5: 0000000000000000 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 000000005040a2d0 S1: 0000000050401cf0 S2: 0000000200042020 S3: 0000000000000001 | |
| up_dump_register: S4: 0000000050400e90 S5: 0000000000000002 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040c750 FP: 000000005040a2d0 TP: 0000000000000000 RA: 000000005020342c | |
| riscv_swint: SWInt Return: Context switch! | |
| up_dump_register: EPC: 0000000050201f22 | |
| up_dump_register: A0: 0000000000000000 A1: 0000000000000000 A2: 0000000000000000 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000000000 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000000000000 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bec0 FP: 0000000000000000 TP: 0000000000000000 RA: 0000000000000000 | |
| riscv_swint: Entry: regs: 0x5040bc90 cmd: 4 | |
| up_dump_register: EPC: 0000000050208762 | |
| up_dump_register: A0: 0000000000000004 A1: 000000008000004a A2: 0000000000000001 A3: 0000000080202010 | |
| up_dump_register: A4: 0000000000000000 A5: 000000008000004a A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000000000000 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bea0 FP: 0000000000000000 TP: 0000000000000000 RA: 0000000050208762 | |
| riscv_swint: SWInt Return: 1 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 13 | |
| up_dump_register: EPC: 0000000080001934 | |
| up_dump_register: A0: 000000000000000d A1: 0000000000000000 A2: 0000000080202bc8 A3: 0000000080202010 | |
| up_dump_register: A4: 0000000080000030 A5: 0000000000000000 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000000000000 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000001 S1: 0000000080202010 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202bc0 FP: 0000000000000001 TP: 0000000000000000 RA: 0000000080000086 | |
| riscv_swint: SWInt Return: 5 | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 0000000080000086 | |
| up_dump_register: A0: 0000000000000003 A1: 0000000080202bc8 A2: 0000000000000000 A3: 0000000080202010 | |
| up_dump_register: A4: 0000000080000030 A5: 0000000000000064 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000050212942 T1: 0000000000000000 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000001 S1: 0000000080202010 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 0000000000000001 TP: 0000000000000000 RA: 0000000080000086 | |
| riscv_swint: SWInt Return: 0 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 70 | |
| up_dump_register: EPC: 000000008000a2e8 | |
| up_dump_register: A0: 0000000000000046 A1: 000000000000ff01 A2: 0000000000000000 A3: 0000000080202010 | |
| up_dump_register: A4: 0000000000000064 A5: 000000000000ff01 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000050212942 T1: 000000008000aa08 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000001 S1: 0000000080202010 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202bc0 FP: 0000000000000001 TP: 0000000000000000 RA: 00000000800000a6 | |
| riscv_swint: SWInt Return: 3e | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 00000000800000a6 | |
| up_dump_register: A0: 0000000000000003 A1: 0000000000000000 A2: 0000000000000000 A3: 000000000000ff08 | |
| up_dump_register: A4: 000000000000ff01 A5: 000000000000ff01 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 000000005021227a T1: 000000008000aa08 T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000001 S1: 0000000080202010 S2: 0000000000000000 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000000 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 0000000000000001 TP: 0000000000000000 RA: 00000000800000a6 | |
| riscv_swint: SWInt Return: 0 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 11 | |
| up_dump_register: EPC: 0000000080001914 | |
| up_dump_register: A0: 000000000000000b A1: 0000000000000348 A2: 0000000000000348 A3: 000000000000ff08 | |
| up_dump_register: A4: 7ffffffffffffffe A5: 0000000000000018 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 000000005021227a T1: 0000000080007ebe T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000080200000 S1: 0000000000000350 S2: 0000000080200000 S3: 0000000080100000 | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202ad0 FP: 0000000080200000 TP: 0000000000000000 RA: 000000008000892e | |
| riscv_swint: SWInt Return: 3 | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 000000008000892e | |
| up_dump_register: A0: 0000000000000003 A1: 0000000000000348 A2: 0000000000000003 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000003 A5: 000000005040d5e0 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502124ac T1: 0000000080007ebe T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000080200000 S1: 0000000000000350 S2: 0000000080200000 S3: 0000000080100000 | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 0000000080200000 TP: 0000000000000000 RA: 000000008000892e | |
| riscv_swint: SWInt Return: 3 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 11 | |
| up_dump_register: EPC: 0000000080001914 | |
| up_dump_register: A0: 000000000000000b A1: 0000000000000348 A2: 0000000000000003 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000003 A5: 000000005040d5e0 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502124ac T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: ffffffffffffffff S1: 0000000080200000 2: 0000000080200000 S3: 0000000080100000 | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202aa0 FP: ffffffffffffffff TP: 0000000000000000 RA: 0000000080001308 | |
| riscv_swint: SWInt Return: 3 | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 0000000080001308 | |
| up_dump_register: A0: 0000000000000003 A1: 0000000000000348 A2: 0000000000000003 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000003 A5: 000000005040d5e0 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502124ac T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: ffffffffffffffff S1: 0000000080200000 S2: 0000000080200000 S3: 0000000080100000 | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: ffffffffffffffff TP: 0000000000000000 RA: 0000000080001308 | |
| riscv_swint: SWInt Return: 3 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 26 | |
| up_dump_register: EPC: 0000000080001922 | |
| up_dump_register: A0: 000000000000001a A1: 0000000080200000 A2: 0000000000000003 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000003 A5: 000000005040d5e0 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502124ac T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000348 S1: 0000000080200000 S2: ffffffffffffff83 S3: fffffffffffffffc | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202ab0 FP: 0000000000000348 TP: 0000000000000000 RA: 0000000080001362 | |
| riscv_swint: SWInt Return: 12 | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 0000000080001362 | |
| up_dump_register: A0: 0000000000000003 A1: 0000000080200000 A2: 0000000000000000 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000006 A5: 0000000000000000 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502126e6 T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000348 S1: 0000000080200000 S2: ffffffffffffff83 S3: fffffffffffffffc | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 0000000000000348 TP: 0000000000000000 RA: 0000000080001362 | |
| riscv_swint: SWInt Return: 0 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 11 | |
| up_dump_register: EPC: 0000000080001914 | |
| up_dump_register: A0: 000000000000000b A1: 0000000080200000 A2: 0000000000000000 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000006 A5: 0000000000000000 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502126e6 T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000080200000 S2: ffffffffffffff83 S3: fffffffffffffffc | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202ab0 FP: 0000000000000000 TP: 0000000000000000 RA: 0000000080001370 | |
| riscv_swint: SWInt Return: 3 | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 0000000080001370 | |
| up_dump_register: A0: 0000000000000003 A1: 0000000080200000 A2: 0000000000000003 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000003 A5: 000000005040d5e0 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502124ac T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000000 S1: 0000000080200000 S2: ffffffffffffff83 S3: fffffffffffffffc | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 0000000000000000 TP: 0000000000000000 RA: 0000000080001370 | |
| riscv_swint: SWInt Return: 3 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 11 | |
| up_dump_register: EPC: 0000000080001914 | |
| up_dump_register: A0: 000000000000000b A1: 00000000802005c0 A2: 000000000000001f A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000000003 A5: fffffffffffffffe A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502124ac T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000003 S1: 0000000000000350 S2: 0000000080200000 S3: 0000000080100000 | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202ab0 FP: 0000000000000003 TP: 0000000000000000 RA: 0000000080001308 | |
| riscv_swint: SWInt Return: 3 | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 0000000080001308 | |
| up_dump_register: A0: 0000000000000003 A1: 00000000802005c0 A2: 0000000000000003 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000003 A5: 000000005040d5e0 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502124ac T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000000000003 S1: 0000000000000350 S2: 0000000080200000 S3: 0000000080100000 | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 0000000000000003 TP: 0000000000000000 RA: 0000000080001308 | |
| riscv_swint: SWInt Return: 3 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 28 | |
| up_dump_register: EPC: 0000000080001978 | |
| up_dump_register: A0: 000000000000001c A1: 0000000080200000 A2: 0000000000000003 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000003 A5: ffffffffffffffff A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 00000000502124ac T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000080200000 S1: 0000000000000350 S2: 0000000080200000 S3: 0000000080100000 | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6:0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202ac0 FP: 0000000080200000 TP: 0000000000000000 RA: 00000000800014d6 | |
| riscv_swint: SWInt Return: 14 | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 00000000800014d6 | |
| up_dump_register: A0: 0000000000000003 A1: 0000000080200000 A2: 0000000000000000 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000007fff A5: 0000000000000001 A6: 0000000000000101 A7: 0000000000000000 | |
| up_dump_register: T0: 0000000050212a20 T1: 000000008000193a T2: 0000000000000000 T3: 0000000000000000 | |
| up_dump_register: T4: 0000000000000000 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 0000000080200000 S1: 0000000000000350 S2: 0000000080200000 S3: 0000000080100000 | |
| up_dump_register: S4: ffffffffffffffff S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 0000000080200000 TP: 0000000000000000 RA: 00000000800014d6 | |
| riscv_swint: SWInt Return: 0 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 63 | |
| up_dump_register: EPC: 00000000800019b2 | |
| up_dump_register: A0: 000000000000003f A1: 0000000000000001 A2: 000000008000ad00 A3: 000000000000001e | |
| up_dump_register: A4: 0000000000000001 A5: 000000008000ad00 A6: 0000000000000000 A7: fffffffffffffff8 | |
| up_dump_register: T0: 0000000050212a20 T1: 0000000000000007 T2: 0000000000000000 T3: 0000000080200908 | |
| up_dump_register: T4: 0000000080200900 T5: 0000000000000000 T6: 0000000000000000 | |
| up_dump_register: S0: 00000000802005c0 S1: 0000000080202010 S2: 0000000080202010 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000001 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202b70 FP: 00000000802005c0 TP: 0000000000000000 RA: 0000000080001a6a | |
| riscv_swint: SWInt Return: 37 | |
| STUB_write: nbr=440, parm1=1, parm2=8000ad00, parm3=1e | |
| NuttShell (NSH) NuttX-12.0.3 | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 0000000080001a6a | |
| up_dump_register: A0: 0000000000000003 A1: 000000005040bbec A2: 000000000000001e A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000007fff A5: 0000000000000001 A6: 0000000000000009 A7: fffffffffffffff8 | |
| up_dump_register: T0: 000000000000002e T1: 000000000000006a T2: 00000000000001ff T3: 000000000000006c | |
| up_dump_register: T4: 0000000000000068 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 00000000802005c0 S1: 0000000080202010 S2: 0000000080202010 S3: 0000000000000000 | |
| up_dump_register: S4: 0000000000000001 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 00000000802005c0 TP: 0000000000000000 RA: 0000000080001a6a | |
| riscv_swint: SWInt Return: 1e | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 63 | |
| up_dump_register: EPC: 00000000800019b2 | |
| up_dump_register: A0: 000000000000003f A1: 0000000000000001 A2: 0000000080015b00 A3: 0000000000000005 | |
| up_dump_register: A4: 0000000000000001 A5: 0000000080015b00 A6: 0000000000000009 A7: fffffffffffffff8 | |
| up_dump_register: T0: 000000000000002e T1: 000000000000006a T2: 00000000000001ff T3: 000000000000006c | |
| up_dump_register: T4: 0000000000000068 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 00000000802005c0 S1: 00000000802008b8 S2: 0000000080015b00 S3: ffffffffffffffff | |
| up_dump_register: S4: 0000000000000001 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202b70 FP: 00000000802005c0 TP: 0000000000000000 RA: 0000000080001a98 | |
| riscv_swint: SWInt Return: 37 | |
| STUB_write: nbr=440, parm1=1, parm2=80015b00, parm3=5 | |
| nsh> riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 0000000080001a98 | |
| up_dump_register: A0: 0000000000000003 A1: 000000005040bbec A2: 0000000000000005 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000007fff A5: 0000000000000001 A6: 0000000000000009 A7: fffffffffffffff8 | |
| up_dump_register: T0: 000000000000002e T1: 000000000000006a T2: 00000000000001ff T3: 000000000000006c | |
| up_dump_register: T4: 0000000000000068 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 00000000802005c0 S1: 00000000802008b8 S2: 0000000080015b00 S3: ffffffffffffffff | |
| up_dump_register: S4: 0000000000000001 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 00000000802005c0 TP: 0000000000000000 RA: 0000000080001a98 | |
| riscv_swint: SWInt Return: 5 | |
| riscv_dispatch_irq: irq=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 63 | |
| up_dump_register: EPC: 00000000800019b2 | |
| up_dump_register: A0: 000000000000003f A1: 0000000000000001 A2: 0000000080015b30 A3: 0000000000000003 | |
| up_dump_register: A4: 0000000000000001 A5: 0000000080015b30 A6: 0000000000000009 A7: fffffffffffffff8 | |
| up_dump_register: T0: 000000000000002e T1: 0000000080001c48 T2: 00000000000001ff T3: 000000000000006c | |
| up_dump_register: T4: 0000000000000068 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 0000000000000000 S1: 00000000802008b8 S2: 0000000080015b00 S3: 0000000080202b40 | |
| up_dump_register: S4: 0000000000000050 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202ac0 FP: 0000000000000000 TP: 0000000000000000 RA: 00000000800032b0 | |
| riscv_swint: SWInt Return: 37 | |
| STUB_write: nbr=440, parm1=1, parm2=80015b30, parm3=3 | |
| riscv_swint: Entry: regs: 0x5040baa0 cmd: 3 | |
| up_dump_register: EPC: 00000000800032b0 | |
| up_dump_register: A0: 0000000000000003 A1: 000000005040bbec A2: 0000000000000003 A3: 0000000000000000 | |
| up_dump_register: A4: 0000000000007fff A5: 0000000000000001 A6: 0000000000000009 A7: fffffffffffffff8 | |
| up_dump_register: T0: 000000000000002e T1: 000000000000006a T2: 00000000000001ff T3: 000000000000006c | |
| up_dump_register: T4: 0000000000000068 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 0000000000000000 S1: 00000000802008b8 S2: 0000000080015b00 S3: 0000000080202b40 | |
| up_dump_register: S4: 0000000000000050 S5: 0000000000000000 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000000000000 S9: 0000000000000000 S10: 0000000000000000 S11: 0000000000000000 | |
| up_dump_register: SP: 000000005040bcb0 FP: 0000000000000000 TP: 0000000000000000 RA: 00000000800032b0 | |
| riscv_swint: SWInt Return: 3 | |
| riscv_dispatch_irq: ir=8 | |
| riscv_swint: Entry: regs: 0x5040bcb0 cmd: 62 | |
| up_dump_register: EPC: 000000008000a4d2 | |
| up_dump_register: A0: 000000000000003e A1: 0000000000000000 A2: 0000000080202a9f A3: 0000000000000001 | |
| up_dump_register: A4: 0000000000000000 A5: 0000000080202a9f A6: 0000000000000009 A7: fffffffffffffff8 | |
| up_dump_register: T0: 000000000000002e T1: 000000000000006a T2: 00000000000001ff T3: 000000000000006c | |
| up_dump_register: T4: 0000000000000068 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 0000000080202b40 S1: 0000000000000004 S2: 0000000000000000 S3: 0000000080202b40 | |
| up_dump_register: S4: 0000000000000050 S5: 0000000080015b30 S6: 0000000080101038 S7: 0000000000000008 | |
| up_dump_register: S8: 000000000000007f S9: 000000000000001b S10: 000000000000000a S11: 0000000000000000 | |
| up_dump_register: SP: 0000000080202a90 FP: 0000000080202b40 TP: 0000000000000000 RA: 0000000080001c70 | |
| riscv_swint: SWInt Return: 36 | |
| riscv_swint: Entry: regs: 0x5040b990 cmd: 2 | |
| up_dump_register: EPC: 000000005020342c | |
| up_dump_register: A0: 0000000000000002 A1: 000000005040d5e0 A2: 0000000050400d08 A3: 0000000050400e90 | |
| up_dump_register: A4: 0000000000000064 A5: 0000000000000000 A6: 0000000000000009 A7: fffffffffffffff8 | |
| up_dump_register: T0: 0000000050212914 T1: 000000000000006a T2: 00000000000001ff T3: 000000000000006c | |
| up_dump_register: T4: 0000000000000068 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 000000005040d5e0 S1: 0000000050400028 S2: 0000000200042020 S3: 0000000000000001 | |
| up_dump_register: S4: 0000000050400e90 S5: 00000000504000b0 S6: 0000000000000000 S7: 0000000000000002 | |
| up_dump_register: S8: 0000000050400000 S9: 000000000000001b S10: 000000000000001b S11: 000000000000005b | |
| up_dump_register: SP: 000000005040bba0 FP: 000000005040d5e0 TP: 0000000000000000 RA: 000000005020342c | |
| riscv_swit: SWInt Return: Context switch! | |
| up_dump_register: EPC: 000000005020186e | |
| up_dump_register: A0: 0000000000000002 A1: 0000000050400d08 A2: 000000005040a900 A3: 000000005040a900 | |
| up_dump_register: A4: 000000005040a2d0 A5: 0000000000000000 A6: 0000000000000000 A7: 0000000000000003 | |
| up_dump_register: T0: 000000000000002e T1: 0000000000000000 T2: 00000000000001ff T3: 000000005040e030 | |
| up_dump_register: T4: 000000005040e028 T5: 0000000000000009 T6: 000000000000002a | |
| up_dump_register: S0: 0000000050400d08 S1: 8000000200046002 S2: 0000000050400e90 S3: 0000000050400cf8 | |
| up_dump_register: S4: fffffffffffffff3 S5: 0000000053fe2f98 S6: 0000000000000000 S7: 0000000000000000 | |
| up_dump_register: S8: 0000000053f7a15c S9: 0000000053fcf2e0 S10: 0000000000000001 S11: 0000000000000003 | |
| up_dump_register: SP: 0000000050408b50 FP: 0000000050400d08 TP: 0000000000000000 RA: 000000005020186e | |
| nx_start: CPU0: Beginning Idle Loop |
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