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max-dark/ov7670_registers.h

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OmniVision OV7670 RegisterSet
Raw
ov7670_registers.h
#ifndef OV7670_REGISTERS_H
#define OV7670_REGISTERS_H
#pragma once
/**
* @brief OmniVision OV7670 RegisterSet
*
* Provides a list and description of the Device Control registers contained in the OV7670/OV7171.
* For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0.
* The device slave addresses are 42 for write and 43 for read.
*
* @see OV7670 Datasheet (V1.4)
*/
enum OV_REGISTERS
{
/**
* AGC - Gain control
*
* bit[7:0] - AGC[7:0]
* range - [00..ff]
* default - 0x00
* @see VREF[7:6] - AGC[9:8]
*/
OV_REG_GAIN = 0x00,
/**
* Blue channel gain setting
*
* range - [00..ff]
* default - 0x80
*/
OV_REG_BLUE = 0x01,
/**
* Red channel gain setting
*
* range - [00..ff]
* default - 0x80
*/
OV_REG_RED = 0x02,
/**
* Vertical frame control
*
* bit[7:6] - AGC[9:8] (see GAIN[7:0])
* bit[5:4] - reserved
* bit[3:2] - VREF end low bits (see VSTOP)
* bit[1:0] - VREF start low bits (see VSTRT)
*
* default - 0x00
*/
OV_REG_VREF = 0x03,
/**
* Common control 1
*
* bit[7] - reserved
* bit[6] - CCIR656 format enable/disable
* bit[5:2] - reserved
* bit[1:0] - AEC low bits (see AECHH/AECH)
*
* default = 0x00
*/
OV_REG_COM1 = 0x04,
/**
* U/B Average level
*
* default = 0x00
*/
OV_REG_BAVE = 0x05,
/**
* Y/Gb Average level
*
* default = 0x00
*/
OV_REG_GbAVE = 0x06,
/**
* Exposure value - AEC MSB 5 bits
*
* bit[7:6] - reserved
* bit[5:0] - AEC[15:10] (see AECH/COM1)
*
* default - 0x00
*/
OV_REG_AECHH = 0x07,
/**
* V/R Average level
*
* default = 0x00
*/
OV_REG_RAVE = 0x08,
/**
* Common control 2
*
* bit[7:5] - reserved
* bit[4] - soft sleep mode
* bit[3:2] - reserved
* bit[1:0] - output drive capability
* 00 - 1x
* 01 - 2x
* 10 - 3x
* 11 - 4x
*
* default - 0x01
*/
OV_REG_COM2 = 0x09,
/// Product ID MSB == '0x76', RO
OV_REG_PID = 0x0A,
/// Product ID LSB == '0x70', RO
OV_REG_VER = 0x0B,
/**
* Common control 3
*
* bit[7] - reserved
* bit[6] - output data MSB/LSB swap
* bit[5] - Tri-state option for clock at power-down period
* 0 - tri-state
* 1 - no tri-state
* bit[4] Tri-state option for output data at power-down period
* 0 - tri-state
* 1 - no tri-state
* bit[3] - scale enable
* 0 - disable
* 1 - enable. if set set to predefined format(see COM7[5:2]) then COM14[3] must be set to '1'
* bit[2] - DCW enable
* 0 - disable
* 1 - enable. if set set to predefined format(see COM7[5:2]) then COM14[3] must be set to '1'
* bit[1:0] - reserved
*
* default - 0x00
*/
OV_REG_COM3 = 0x0C,
/**
* Common control 4
*
* bit[7:6] - reserved
* bit[5:4] - Average option(must be same as COM17[7:6])
* 00 - full window
* 01 - 1/2 window
* 10 - 1/4 window
* 11 - 1/4(?) window
* bit[3:0] - reserved
*
* default - 0x00
*/
OV_REG_COM4 = 0x0D,
/**
* Common control 5
*
* bit[7-0] - reserved
*
* default - 0x01
*/
OV_REG_COM5 = 0x0E,
/**
* Common control 6
*
* bit[7] - output of optical black line
* 0 - disable HREF at optical black
* 1 - enable HREF at optical black
* bit[6:2] - reserved
* bit[1] - reset all timing when format changes
* 0 - no reset
* 1 - resets timing
* bit[0] - reserved
*
* default - 0x43 (0'10000'1'1)
*/
OV_REG_COM6 = 0x0F,
/**
* Exposure value
*
* bit[7:0] - AEC[9:2](see AECHH and COM1)
*
* default - 0x40
*/
OV_REG_AECH = 0x10,
/**
* Internal clock
*
* bit[7] - reserved
* bit[6] - use external clock directly(no pre-scale available)
* bit[5:0] - internal clock pre-scale - F(internal) = F(input) / (bit[5:0] + 1)
*
* default - 0x80 (1'0'00000)
*/
OV_REG_CLKRC = 0x11,
/**
* Common control 7
*
* bit[7] - SCCB register reset
* 0 - no change
* 1 - reset all registers to default values
* bit[6] - reserved
* bit[5] - output format - CIF
* bit[4] - output format - QVGA
* bit[3] - output format - QCIF
* bit[2] - output format - RGB (see below)
* bit[1] - color bar
* 0 - disable
* 1 - enable
* bit[0] - output format - Raw RGB (see below)
*
* COM7[2] COM7[0]
* YUV 0 0
* RGB 1 0
* Bayer RAW 0 1
* Processed Bayer RAW 1 1
*
* default - 0x00
*/
OV_REG_COM7 = 0x12,
/**
* Common control 8
*
* bit[7] - enable fast AGC/AEC algorithm
* bit[6] - AEC - step size limit
* 0 - step size limited to vertical blank
* 1 - unlimited step size
* bit[5] - banding filter ON/OF. in order to turn ON BD50ST or BD60ST must be set to nonzero
* 0 - OFF
* 1 - ON
* bit[4:3] - reserved
* bit[2] - AGC Enable
* bit[1] - AWB Enable
* bit[0] - AEC Enable
*
* default - 0x8f (1'0'0'01'1'1'1)
*/
OV_REG_COM8 = 0x13,
/**
* Common control 9
*
* bit[7] - reserved
* bit[6:4] - Automatic Gain Ceiling - maximum AGC value
* 000 - 2x
* 001 - 4x
* 010 - 8x
* 011 - 16x
* 100 - 32x
* 101 - 64x
* 110 - 128x
* 111 - not allowed
* bit[3:1] - reserved
* bit[0] - Freeze AGC/AEC
*
* default 0x4A (0'100'101'0)
*/
OV_REG_COM9 = 0x14,
/**
* Common control 10 / Sync options
*
* bit[7] - reserved
* bit[6] - HREF changes to HSYNC
* bit[5] - PCLK output option
* 0 - free running PCLK
* 1 - PCLK does not toggle during horizontal blank
* bit[4] - PCLK reverse
* bit[3] - HREF reverse
* bit[2] - VSYNC option
* 0 - VSYNC changes on falling edge of PCLK
* 1 - VSYNC changes on rising edge of PCLK
* bit[1] - VSYNC negative
* bit[0] - HSYNC negative
*
* default - 0x00
*/
OV_REG_COM10 = 0x15,
OV_REG_RSVD_0X16 = 0x16, ///< Reserved
/**
* Output format - Horizontal frame(HREF column) start / high 8-bit(low is HREF[2:0])
*
* default = 0x11
*/
OV_REG_HSTART = 0x17,
/**
* Output format - Horizontal frame(HREF column) stop / high 8-bit(low is HREF[5:3])
*
* default = 0x61
*/
OV_REG_HSTOP = 0x18,
/**
* Output format - Vertical frame(row) start / high 8-bit(low is VREF[1:0])
*
* default = 0x03
*/
OV_REG_VSTRT = 0x19,
/**
* Output format - Vertical frame(row) stop / high 8-bit(low is VREF[3:2])
*
* default = 0x7b
*/
OV_REG_VSTOP = 0x1A,
/**
* Output format - Pixel delay select
*
* delays timings of the D[7:0] data relative to HREF in pixel units
* range:
* 0x00 - no delay
* 0xff - 256 pixel delay which accounts for whole array
*
* default - 0x00
*/
OV_REG_PSHIFT = 0x1B,
OV_REG_MIDH = 0x1C, ///< Manufacturer ID / High == 0x7F, RO
OV_REG_MIDL = 0x1D, ///< Manufacturer ID / Low == 0xA2, RO
/**
* Mirror/VFlip Enable
*
* bit[7:6] - reserved
* bit[5] - Mirror enable
* 0 - Normal image
* 1 - Mirror image
* bit[4] - VFlip enable
* 0 - Normal image
* 1 - Vertical flip image
* bit[3] - reserved
* bit[2] - black sun enable
* bit[1:0] - Reserved
*
* default 0x01 (00'0'0'0'0'01)
*/
OV_REG_MVFP = 0x1E,
OV_REG_LAEC = 0x1F, ///< Reserved
/**
* ADC Control
* bit[7:4] - reserved
* bit[3] - ADC range adjustment
* 0 - 1x range
* 1 - 1.5x range
* bit[2:0] ADC reference adjustment
* 000 - 0.8x
* 100 - 1.0x
* 111 - 1.2x
*
* default - 0x04 (0000'0'100)
*/
OV_REG_ADCCTR0 = 0x20,
OV_REG_ADCCTR1 = 0x21, ///< Reserved / 0x02
OV_REG_ADCCTR2 = 0x22, ///< Reserved / 0x01
OV_REG_ADCCTR3 = 0x23, ///< Reserved / 0x00
/**
* AGC/AEC - Stable Operating Region (Upper Limit)
*
* default - 0x75
*/
OV_REG_AEW = 0x24,
/**
* AGC/AEC - Stable Operating Region (Lower Limit)
*
* default - 0x63
*/
OV_REG_AEB = 0x25,
/**
* AGC/AEC Fast Mode operating region
*
* bit[7:4] - High nibble of upper limit of fast mode control zone
* bit[3:0] - High nibble of lower limit of fast mode control zone
*
* default = 0xD4
*/
OV_REG_VPT = 0x26,
/**
* B channel signal output bias (effective only when COM6[3] == 1)
*
* bit[7] - bias adjustment sign
* 0 - add bias
* 1 - subtract bias
* bit[6:0] - bias value of 10-bit range
*
* default - 0x80
*/
OV_REG_BBIAS = 0x27,
/**
* Gb channel signal output bias (effective only when COM6[3] == 1)
*
* bit[7] - bias adjustment sign
* 0 - add bias
* 1 - subtract bias
* bit[6:0] - bias value of 10-bit range
*
* default - 0x80
*/
OV_REG_GbBIAS = 0x28,
OV_REG_RSVD_0X29 = 0x29, ///< Reserved
/**
* Dummy pixel insert MSB
*
* bit[7:4] - 4 MSB for dummy pixel insert in horizontal direction
* bit[3:2] - HSYNC falling edge delay 2 MSB
* bit[1:0] - HSYNC rising edge delay 2 MSB
*
* default = 0x00
*/
OV_REG_EXHCH = 0x2A,
/**
* Dummy pixel insert LSB
*
* 8 LSB for dummy pixel insert in horizontal direction
*
* default = 0x00
*/
OV_REG_EXHCL = 0x2B,
/**
* R channel signal output bias (effective only when COM6[3] == 1)
*
* bit[7] - bias adjustment sign
* 0 - add bias
* 1 - subtract bias
* bit[6:0] - bias value of 10-bit range
*
* default - 0x80
*/
OV_REG_RBIAS = 0x2C,
/**
* LSB of Insert dummy lines in vertical direction(1 bit equals 1 line)
*
* default - 0x00
*/
OV_REG_ADVFL = 0x2D,
/**
* MSB of Insert dummy lines in vertical direction(1 bit equals 1 line)
*
* default - 0x00
*/
OV_REG_ADVFH = 0x2E,
/**
* Y/G Channel average value
*/
OV_REG_YAVE = 0x2F,
/**
* HSYNC rising edge delay(low 8 bits)
*
* default = 0x08
*/
OV_REG_HSYST = 0x30,
/**
* HSYNC falling edge delay(low 8 bits)
*
* default = 0x30
*/
OV_REG_HSYEN = 0x31,
/**
* HREF control
*
* bit[7:6] - HREF edge offset to data output
* bit[5:3] - HREF end 3 LSB (high 8 MSB at register HSTOP)
* bit[2:0] - HREF start 3 LSB (high 8 MSB at register HSTART)
*
* default - 0x80 (10'000'000)
*/
OV_REG_HREF = 0x32,
/**
* ADC Current Control
*
* bit[7:0] - reserved
*
* default - 0x08
*/
OV_REG_CHLF = 0x33,
/**
* ADC Reference Control
*
* bit[7:0] - reserved
*
* default - 0x11
*/
OV_REG_ARBLM = 0x34,
OV_REG_RSVD_0X35 = 0x35, ///< Reserved
OV_REG_RSVD_0X36 = 0x36, ///< Reserved
/**
* ADC Control
*
* bit[7:0] - reserved
*
* default - 0x3F
*/
OV_REG_ADC = 0x37,
/**
* ADC and Analog common mode Control
*
* bit[7:0] - reserved
*
* default - 0x01
*/
OV_REG_ACOM = 0x38,
/**
* ADC Offset Control
*
* bit[7:0] - reserved
*
* default - 0x00
*/
OV_REG_OFON = 0x39,
/**
* Line buffer test option
*
* bit[7:6] - reserved
* bit[5] - negative image enable
* 0 - normal image
* 1 - negative image
* bit[4] - UV output value
* 0 - use normal UV output
* 1 - use fixed UV value(set in registers MANU/MANV) as UV output instead of chip output
* bit[3] - output sequence(use with COM13[0])
* TSLB[3], COM13[0]:
* 00: Y U Y V
* 01: Y V Y U
* 10: U Y V Y
* 11: V Y U Y
* bit[2:1] - reserved
* bit[0] - Auto output window
* 0 - Sensor DOES NOT automatically set window after
* resolution change. The companion backend
* processor can adjust the output window immediately
* after changing the resolution
* 1 - Sensor automatically sets output window when
* resolution changes. After resolution changes, the
* companion backend processor must adjust the
* output window after the next VSYNC pulse.
*
* default - 0x0D (00'0'0'1'10'1)
*/
OV_REG_TSLB = 0x3A,
/**
* Common control 11
*
* bit[7] - night mode
* 0 - night mode disable
* 1 - night mode enable - The frame rate is reduced
* automatically while the minimum frame rate is limited
* by COM11[6:5]. Also, ADVFH and ADVFL will be
* automatically updated.
* bit[6:5] - Minimum frame rate of night mode
* 00: Same as normal mode frame rate
* 01: 1/2 of normal mode frame rate
* 10: 1/4 of normal mode frame rate
* 11: 1/8 of normal mode frame rate
* bit[4] - D56_Auto
* 0: Disable 50/60 Hz auto detection
* 1: Enable 50/60 Hz auto detection
* bit[3] - Banding filter value select (effective only when COM11[4] = 0)
* 0: Select BD60ST[7:0] (0x9E) as Banding Filter Value
* 1: Select BD50ST[7:0] (0x9D) as Banding Filter Value
* bit[2] - reserved
* bit[1] - Exposure timing can be less than limit of banding filter
* when light is too strong
* bit[0] - reserved
*
* default = 0x00
*/
OV_REG_COM11 = 0x3B,
/**
* Common control 12
*
* bit[7] - HREF option
* 0 - No HREF when VSYNC is low
* 1 - Always has HREF
* bit[6:0] - reserved
*
* default - 0x68
*/
OV_REG_COM12 = 0x3C,
/**
* Common control 13
*
* bit[7] - Gamma enable
* bit[6] - UV saturation level - UV auto adjustment.
* Result is saved in SATCTR[3:0](0xC9)
* bit[5:1] - reserved
* bit[0] - UV swap(use with register TSLB[3](0x3A))
* TSLB[3], COM13[0]:
* 00: Y U Y V
* 01: Y V Y U
* 10: U Y V Y
* 11: V Y U Y
*
* default = 0x88 (10001000)
*/
OV_REG_COM13 = 0x3D,
/**
* Common control 14
*
* bit[7:5] - reserved
* bit[4] - DCW and scaling PCLK enable
* 0 - normal PCLK
* 1 - DCW and scaling PCLK, controlled by register
* COM14[2:0] and SCALING_PCLK_DIV[3:0] (0x73)
* bit[3] - Manual scaling enable for pre-defined resolution modes
* such as CIF, QCIF and QVGA
* 0 - scaling parameter cannot be adjusted manually
* 1 - scaling parameter can be adjusted manually
* bit[2:0] - PCLK divider (only when COM14[4] = 1)
* 000: Divided by 1
* 001: Divided by 2
* 010: Divided by 4
* 011: Divided by 8
* 100: Divided by 16
* 101~111: Not allowed
*
* default = 0x00
*/
OV_REG_COM14 = 0x3E,
/**
* Edge Enhancement Adjustment
*
* bit[7:5] - reserved
* bit[4:0] - edge enhancement factor
*
* default = 0x00
*/
OV_REG_EDGE = 0x3F,
/**
* Common control 15
*
* bit[7:6] - Data format - output full range enable
* 0x: Output range: [10] to [F0]
* 10: Output range: [01] to [FE]
* 11: Output range: [00] to [FF]
* bit[5:4] - RGB 555/565 option (must set COM7[2] = 1 and COM7[0] = 0)
* x0: Normal RGB output
* 01: RGB 565, effective only when RGB444[1] is low
* 11: RGB 555, effective only when RGB444[1] is low
* bit[3:0] - reserved
*
* default = 0xC0 (11'00'0000)
*/
OV_REG_COM15 = 0x40,
/**
* Common control 16
*
* bit[7:6] - reserved
* bit[5] - Enable edge enhancement threshold auto-adjustment for
* YUV output (result is saved in register EDGE[4:0] (0x3F)
* and range is controlled by registers REG75[4:0] (0x75)
* and REG76[4:0] (0x76))
* 0: Disable
* 1: Enable
* bit[4] - De-noise threshold auto-adjustment (result is saved in
* register DNSTH (0x4C) and range is controlled by register
* REG77[7:0] (0x77))
* 0: Disable
* 1: Enable
* bit[3] - AWB gain enable
* bit[2] - reserved
* bit[1] - Color matrix coefficient double option
* 0: Original matrix
* 1: Double of original matrix
* bit[0] - reserved
*
* default - 0x08 (00'0'0'1'0'0'0)
*/
OV_REG_COM16 = 0x41,
/**
* Common control 17
*
* bit[7:6] - AEC window must be the same value as COM4[5:4]
* 00: Normal
* 01: 1/2
* 10: 1/4
* 11: 1/4
* bit[5:6] - reserved
* bit[3] - DSP color bar enable
* 0: Disable
* 1: Enable
* bit[2:0] - reserved
*
* default - 0x00
*/
OV_REG_COM17 = 0x42,
OV_REG_AWBC1 = 0x43, ///< Reserved / 0x14
OV_REG_AWBC2 = 0x44, ///< Reserved / 0xF0
OV_REG_AWBC3 = 0x45, ///< Reserved / 0x45
OV_REG_AWBC4 = 0x46, ///< Reserved / 0x61
OV_REG_AWBC5 = 0x47, ///< Reserved / 0x51
OV_REG_AWBC6 = 0x48, ///< Reserved / 0x79
OV_REG_RSVD_0X49 = 0x49, ///< Reserved
OV_REG_RSVD_0X4A = 0x4A, ///< Reserved
/**
* Register 4B
*
* bit[7:1] - reserved
* bit[0] - UV average enable
*
* default = 0x00
*/
OV_REG_REG4B = 0x4B,
/**
* De-noise strength
*
* default = 0x00
*/
OV_REG_DNSTH = 0x4C,
OV_REG_RSVD_0X4D = 0x4D, ///< Reserved
OV_REG_RSVD_0X4E = 0x4E, ///< Reserved
OV_REG_MTX1 = 0x4F, ///< matrix coefficient 1 / 0x40
OV_REG_MTX2 = 0x50, ///< matrix coefficient 2 / 0x34
OV_REG_MTX3 = 0x51, ///< matrix coefficient 3 / 0x0C
OV_REG_MTX4 = 0x52, ///< matrix coefficient 4 / 0x17
OV_REG_MTX5 = 0x53, ///< matrix coefficient 5 / 0x29
OV_REG_MTX6 = 0x54, ///< matrix coefficient 6 / 0x40
OV_REG_BRIGHT = 0x55, ///< Brightness control / 0x00
OV_REG_CONTRAS = 0x56, ///< Contrast Control / 0x40
OV_REG_CONTRAS_CENTER = 0x57, ///< Contrast Center / 0x80
/**
* Matrix Coefficient Sign for Coefficient 5 to 0
*
* bit[7] - Auto contrast center enable
* 0: Disable, center is set by register CONTRAS-CENTER (0x57)
* 1: Enable, register CONTRAS-CENTER is updated automatically
* bit[6] - reserved
* bit[5:0] - Matrix coefficient sign
* 0: Plus
* 1: Minus
*
* default = 0x1E (0'0'011110)
*/
OV_REG_MTXS = 0x58,
OV_REG_RSVD_0X59 = 0x59, ///< Reserved
OV_REG_RSVD_0X61 = 0x61, ///< Reserved
/**
* Lens Correction Option 1 - X Coordinate of Lens Correction Center
* Relative to Array Center
*
* default = 0x00
*/
OV_REG_LCC1 = 0x62,
/**
* Lens Correction Option 2 - Y Coordinate of Lens Correction Center
* Relative to Array Center
*
* default = 0x00
*/
OV_REG_LCC2 = 0x63,
/**
* Lens Correction Option 3
* G Channel Compensation Coefficient when LCC5[2] (0x66) is 1
* R, G, and B Channel Compensation Coefficient when LCC5[2] (0x66) is 0
*
* default = 0x50
*/
OV_REG_LCC3 = 0x64,
/**
* Lens Correction Option 4 - Radius of the circular section where no
* compensation applies
*
* default = 0x30
*/
OV_REG_LCC4 = 0x65,
/**
* Lens Correction Control 5
*
* bit[7:3] - reserved
* bit[2] - Lens correction control select
* 0: R, G, and B channel compensation coefficient is set
* by register LCC3 (0x64)
* 1: R, G, and B channel compensation coefficient is set
* by registers LCC6, LCC3, and LCC7, respectively
* bit[1] - reserved
* bit[0] - Lens correction enable
* 0: Disable
* 1: Enable
*
* default = 0x00
*/
OV_REG_LCC5 = 0x66,
/**
* Manual U Value (effective only when register TSLB[4] is high)
*
* default = 0x80
*/
OV_REG_MANU = 0x67,
/**
* Manual V Value (effective only when register TSLB[4] is high)
*
* default = 0x80
*/
OV_REG_MANV = 0x68,
/**
* Fix Gain Control
*
* bit[7:6] - Fix gain for Gr channel
* 00: 1x
* 01: 1.25x
* 10: 1.5x
* 11: 1.75x
* bit[5:4] - Fix gain for Gb channel
* 00: 1x
* 01: 1.25x
* 10: 1.5x
* 11: 1.75x
* bit[3:2] - Fix gain for R channel
* 00: 1x
* 01: 1.25x
* 10: 1.5x
* 11: 1.75x
* bit[1:0] - Fix gain for B channel
* 00: 1x
* 01: 1.25x
* 10: 1.5x
* 11: 1.75x
*
* default = 0x00
*/
OV_REG_GFIX = 0x69,
/**
* G Channel AWB Gain
*
* default = 0x00
*/
OV_REG_GGAIN = 0x6A,
/**
* bit[7:6] PLL control
* 00: Bypass PLL
* 01: Input clock x4
* 10: Input clock x6
* 11: Input clock x8
* bit[5] - reserved
* bit[4] - Regulator control
* 0: Enable internal regulator
* 1: Bypass internal regulator
* bit[3:0] - reserved
*
* default = 0x0A(00'0'0'1010)
*/
OV_REG_DBLV = 0x6B,
OV_REG_AWBCTR3 = 0x6C, ///< AWB Control 3 / 0x02
OV_REG_AWBCTR2 = 0x6D, ///< AWB Control 2 / 0x55
OV_REG_AWBCTR1 = 0x6E, ///< AWB Control 1 / 0xC0
OV_REG_AWBCTR0 = 0x6F, ///< AWB Control 0 / 0x9A
/**
* bit[7] - Test_pattern[0] - works with test_pattern[1] test_pattern
* (SCALING_XSC[7], SCALING_YSC[7]):
* 00: No test output
* 01: Shifting "1"
* 10: 8-bar color bar
* 11: Fade to gray color bar
* bit[6:0] - Horizontal scale factor
*/
OV_REG_SCALING_XSC = 0x70,
/**
* bit[7] - Test_pattern[1] - works with test_pattern[0] test_pattern
* (SCALING_XSC[7], SCALING_YSC[7]):
* 00: No test output
* 01: Shifting "1"
* 10: 8-bar color bar
* 11: Fade to gray color bar
* bit[6:0] - Vertical scale factor
*/
OV_REG_SCALING_YSC = 0x71,
/**
* DCW control
* bit[7] - Vertical average calculation option
* 0: Vertical truncation
* 1: Vertical rounding
* bit[6] - Vertical down sampling option
* 0: Vertical truncation
* 1: Vertical rounding
* bit[5:4] - Vertical down sampling rate
* 00: No vertical down sampling
* 01: Vertical down sample by 2
* 10: Vertical down sample by 4
* 11: Vertical down sample by 8
* bit[3] - Horizontal average calculation option
* 0: Horizontal truncation
* 1: Horizontal rounding
* bit[2] - Horizontal down sampling option
* 0: Horizontal truncation
* 1: Horizontal rounding
* bit[1:0] - Horizontal down sampling rate
* 00: No horizontal down sampling
* 01: Horizontal down sample by 2
* 10: Horizontal down sample by 4
* 11: Horizontal down sample by 8
*
* default = 0x11 (0'0'01'0'0'01)
*/
OV_REG_SCALING_DCWCTR = 0x72,
/**
* bit[7:4] - Reserved
* bit[3] - Bypass clock divider for DSP scale control
* 0: Enable clock divider
* 1: Bypass clock divider
* bit[2:0] - Clock divider control for DSP scale control (valid only
* when COM14[3] = 1). Should change with COM14[2:0].
* 000: Divided by 1
* 001: Divided by 2
* 010: Divided by 4
* 011: Divided by 8
* 100: Divided by 16
* 101~111: Not allowed
*
* default = 0x00
*/
OV_REG_SCALING_PCLK_DIV = 0x73,
/**
* Register 0x74
* bit[7:5] - Reserved
* bit[4] - DG_Manu
* 0: Digital gain control by VREF[7:6]
* 1: Digital gain control by REG74[1:0]
* bit[3:2] - Reserved
* bit[1:0] - Digital gain manual control
* 00: Bypass
* 01: 1x
* 10: 2x
* 11: 4x
*
* default = 0x00
*/
OV_REG_REG74 = 0x74,
/**
* Register 0x75
*
* bit[7:5] - Reserved
* bit[4:0] - Edge enhancement lower limit
*
* default = 0x0F
*/
OV_REG_REG75 = 0x75,
/**
* Register 0x76
*
* bit[7] - Black pixel correction enable
* 0: Disable
* 1: Enable
* bit[6] - White pixel correction enable
* 0: Disable
* 1: Enable
* bit[5] - Reserved
* bit[4:0] - Edge enhancement higher limit
*
* default = 0x01
*/
OV_REG_REG76 = 0x76,
/**
* register 0x77
* bit[7:0] De-noise offset
* default = 0x10
*/
OV_REG_REG77 = 0x77,
OV_REG_RSVD_0X78 = 0x78, ///< Reserved
OV_REG_RSVD_0X79 = 0X79, ///< Reserved
/**
* Gamma Curve Highest Segment Slope - calculated as follows:
* SLOP[7:0] = (0x100 - GAM15[7:0]) x 4/3
*
* default = 0x24
*/
OV_REG_SLOP = 0x7A,
OV_REG_GAM1 = 0x7B, ///< Gamma curve
OV_REG_GAM2 = 0x7C, ///< Gamma curve
OV_REG_GAM3 = 0x7D, ///< Gamma curve
OV_REG_GAM4 = 0x7E, ///< Gamma curve
OV_REG_GAM5 = 0x7F, ///< Gamma curve
OV_REG_GAM6 = 0x80, ///< Gamma curve
OV_REG_GAM7 = 0x81, ///< Gamma curve
OV_REG_GAM8 = 0x82, ///< Gamma curve
OV_REG_GAM9 = 0x83, ///< Gamma curve
OV_REG_GAM10 = 0x84, ///< Gamma curve
OV_REG_GAM11 = 0x85, ///< Gamma curve
OV_REG_GAM12 = 0x86, ///< Gamma curve
OV_REG_GAM13 = 0x87, ///< Gamma curve
OV_REG_GAM14 = 0x88, ///< Gamma curve
OV_REG_GAM15 = 0x89, ///< Gamma curve
OV_REG_RSVD_0X8A = 0x8A, ///< Reserved
OV_REG_RSVD_0X8B = 0x8B, ///< Reserved
/**
* bit[7:2] - Reserved
* bit[1] - RGB444 enable, effective only when COM15[4] is high
* 0: Disable
* 1: Enable
* bit[0] - RGB444 word format
* 0: xR GB
* 1: RG Bx
*
* default 0x00
*/
OV_REG_RGB444 = 0x8C,
OV_REG_RSVD_0X8D = 0x8D, ///< Reserved
// OV_REG_RSVD_0X8E = 0x8E, ///< Reserved
// OV_REG_RSVD_0X8f = 0x8F, ///< Reserved
// OV_REG_RSVD_0X90 = 0x90, ///< Reserved
OV_REG_RSVD_0X91 = 0x91, ///< Reserved
/**
* Dummy line low 8 bits
*
* default = 0x00
*/
OV_REG_DM_LNL = 0x92,
/**
* Dummy line high 8 bits
*
* default = 0x00
*/
OV_REG_DM_LNH = 0x93,
/**
* Lens Correction Option 6 (effective only when LCC5[2] is high)
*
* default = 0x50
*/
OV_REG_LCC6 = 0x94,
/**
* Lens Correction Option 7 (effective only when LCC5[2] is high)
*
* default = 0x50
*/
OV_REG_LCC7 = 0x95,
OV_REG_RSVD_0X96 = 0x96, ///< Reserved
OV_REG_RSVD_0X9C = 0x9C, ///< Reserved
/**
* 50 Hz Banding Filter Value (effective only when COM8[5] is high and COM11[3] is high)
*
* default = 0x99
*/
OV_REG_BD50ST = 0x9D,
/**
* 60 Hz Banding Filter Value (effective only when COM8[5] is high and COM11[3] is low)
*
* default = 0x7F
*/
OV_REG_BD60ST = 0x9E,
/**
* Histogram-based AEC/AGC Control 1
*
* default = 0xC0
*/
OV_REG_HAECC1 = 0x9F,
/**
* Histogram-based AEC/AGC Control 2
*
* default = 0x90
*/
OV_REG_HAECC2 = 0xA,
OV_REG_RSVD_0XA1 = 0xA1, ///< Reserved
/**
* Pixel Clock Delay
* bit[7] - reserved
* bit[6:0] - Scaling output delay
*
* default = 0x02
*/
OV_REG_SCALING_PCLK_DELAY = 0xA2,
OV_REG_RSVD_0XA3 = 0xA3, ///< Reserved
/**
* NT_CTRL
*
* bit[7:4] - reserved
* bit[3] - auto frame adjustment control
* 0 - double exposure time
* 1 - reduce frame rate by half
* bit[2] - reserved
* bit[1:0] - auto frame rate adjustment switch point
* 00 - insert dummy row at 2x gain
* 01 - insert dummy row at 4x gain
* 10 - insert dummy row at 8x gain
*
* default = 0x00
*/
OV_REG_NT_CTRL = 0xA4,
/**
* 50Hz Banding Step Limit
*
* default = 0x0F
*/
OV_REG_BD50MAX = 0xA5,
/**
* Histogram-based AEC/AGC Control 3
*
* default = 0xF0
*/
OV_REG_HAECC3 = 0xA6,
/**
* Histogram-based AEC/AGC Control 4
*
* default = 0xC1
*/
OV_REG_HAECC4 = 0xA7,
/**
* Histogram-based AEC/AGC Control 5
*
* default = 0xF0
*/
OV_REG_HAECC5 = 0xA8,
/**
* Histogram-based AEC/AGC Control 6
*
* default = 0xC1
*/
OV_REG_HAECC6 = 0xA9,
/**
* Histogram-based AEC/AGC Control 7
*
* bit[7] - AEC algorithm selection
* 0 - Average-based AEC algorithm
* 0 - Histogram-based AEC algorithm
* bit[6:0] - reserved
*
* default = 0x14
*/
OV_REG_HAECC7 = 0xAA,
/**
* 60Hz Banding Step Limit
*
* default = 0x0F
*/
OV_REG_BD60MAX = 0xAB,
/**
* Register AC
*
* bit[7] - Strobe enable
* bit[6] - R / G / B gain controlled by STR_R (0xAD) / STR_G(0xAE) / STR_B (0xAF) for LED output frame
* bit[5:4] - Xenon mode option
* 00: 1 row
* 01: 2 rows
* 10: 3 rows
* 11: 4 rows
* bit[3:2] - reserved
* bit[1:0] - Mode select
* 00: Xenon
* 01: LED 1
* 1x: LED 2
*
* default = 0x00
*/
OV_REG_STR_OPT = 0xAC,
/**
* R Gain for LED Output Frame
*
* default = 0x80
*/
OV_REG_STR_R = 0xAD,
/**
* G Gain for LED Output Frame
*
* default = 0x80
*/
OV_REG_STR_G = 0xAE,
/**
* B Gain for LED Output Frame
*
* default = 0x80
*/
OV_REG_STR_B = 0xAF,
OV_REG_RSVD_0XB0 = 0xB0, ///< Reserved
/**
* bit[7:3] - reserved
* bit[2] - ABLC enable
* 0: Disable ABLC function
* 1: Enable ABLC function
* bit[1:0] - reserved
*
* default = 0x00
*/
OV_REG_ABLC1 = 0xB1,
OV_REG_RSVD_0XB2 = 0xB2, ///< Reserved
/**
* ABLC Target
*
* default = 0x80
*/
OV_REG_THL_ST = 0xB3,
OV_REG_RSVD_0XB4 = 0xB4, ///< Reserved
/**
* ABLC Stable Range
*
* default = 0x04
*/
OV_REG_THL_DTL = 0xB5,
OV_REG_RSVD_0XB6 = 0xB6, ///< Reserved
OV_REG_RSVD_0XBD = 0xBD, ///< Reserved
/**
* Blue Channel Black Level Compensation
* bit[7] - reserved
* bit[6] - sign bit
* bit[5:0] - Blue Channel Black Level Compensation
*
* default = 0x00
*/
OV_REG_AD_CHB = 0xBE,
/**
* Red Channel Black Level Compensation
* bit[7] - reserved
* bit[6] - sign bit
* bit[5:0] - Red Channel Black Level Compensation
*
* default = 0x00
*/
OV_REG_AD_CHR = 0xBF,
/**
* Gb Channel Black Level Compensation
* bit[7] - reserved
* bit[6] - sign bit
* bit[5:0] - Gb Channel Black Level Compensation
*
* default = 0x00
*/
OV_REG_AD_CHGb = 0xC0,
/**
* Gr Channel Black Level Compensation
* bit[7] - reserved
* bit[6] - sign bit
* bit[5:0] - Gr Channel Black Level Compensation
*
* default = 0x00
*/
OV_REG_AD_CHGr = 0xC1,
OV_REG_RSVD_0XC2 = 0xC2, ///< Reserved
OV_REG_RSVD_0XC8 = 0xC8, ///< Reserved
/**
* Saturation control
*
* bit[7:4] - UV saturation control min
* bit[3:0] - UV saturation control result
*
* default = 0xC0
*/
OV_REG_SARCTR = 0xC9,
// NOTE: All other registers are factory-reserved.
// Please contact OmniVision Technologies for reference register settings.
};
typedef enum OV_REGISTERS OV_REGISTERS;
#endif // OV7670_REGISTERS_H
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