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mcandre / lazerbrite-battery-replacement.md
Last active January 26, 2023 20:59
LazerBrite Battery Replacement

LazerBrite Battery Replacement

The included instructions fail to explain how to remove any existing batteries during replacement. So we document the full process here.

  1. Select either of the individual light ends of the LazerBrite system for battery replacement.
  2. Unscrew any plastic diffusal attachments from the individual light, to reveal the bare LED.
  3. On the other side of the individual light, unscrew any plastic attachments.
  4. Untie any helix loops from the black battery cover.
  5. Use a medium flathead driver (screwdriver, coin, back of a utensil, etc) to unscrew the battery cover.
  6. Firmly smack the open battery holder against a clean, hard surface until the two CR2032 batteries fall out.
@mcandre
mcandre / elecraft-kx3-cheatsheet.md
Last active January 23, 2025 00:55
Elecraft KX3 Cheatsheet

Elecraft KX3 Cheatsheet

The KX3 transceiver is designed for HF amateur band operation. The KX3 natively supports 160m - 6m.

An optional 2m accessory can extend the band support to 2m, though the installation of that accessory is a more intensive, electronics hobbyist task.

WARNINGS

As with all radios, do not transmit when the antenna is disconnected. Avoid touching the antenna or feed line when transmitting. Power down the radio and disconnect the feed line when making antenna adjustments.

@mcandre
mcandre / yaesu-ft-70dr-cheatsheet.md
Last active March 6, 2022 22:43
Yaesu FT-70DR Cheatsheet

Yaesu FT-70DR Cheatsheet

Belt Clip

Yaesu sells handheld transceivers with an optional belt clip, detached by default. To attach the clip, remove any battery. Then firmly insert the two belt clip screws with an appropriate screwdriver. My radio came with two small Phillips head screws.

Charging

The battery charges via a barrel plug located on the right side of the radio.

@mcandre
mcandre / baofeng-uv-5x3-cheatsheet.md
Last active September 10, 2023 18:29
Baofeng UV-5x3 Cheatsheet

Baofeng UV-5x3 Cheatsheet

SUMMARY

A growing list of notes, bugs, issues, problems, design flaws, oddities, quirks, bad UX, nonintuitivity, challenges, frequently asked questions, gotchas, glitches, and errors with the Baofeng UV-5x3 amateur radio transceiver.

WARNING

DO NOT TRANSMIT ON THE RADIO WHILE THE ANTENNA IS DISCONNECTED, UNFOLDED, OR DAMAGED; DOING SO MAY RESULT IN PAINFUL BURNS FROM SPURIOUS RADIO FREQUENCY EMISSIONS.

@mcandre
mcandre / How to install Homebrew Casks
Created December 2, 2021 22:30
how-to-install-homebrew-casks.md
Homebrew keeps changing the syntax to install casks.
As of this writing, the syntax is `brew install homebrew/cask/<formula>`.
@mcandre
mcandre / shrink-wsl.md
Created November 18, 2021 17:19
Shrink WSL
  1. Backup any critical data.
  2. Launch an administrative PowerShell session.
  3. Change directory like cd "C:\Users\andrew\AppData\Local\Packages\CanonicalGroupLimited.UbuntuonWindows_79rhkp1fndgsc\LocalState"
  4. Run optimize-vhd -Path ext4.vhdx -Mode full
  5. Wait a few minutes for the process to complete.
  6. Relaunch WSL.
@mcandre
mcandre / fulladder_chain.sv
Created October 11, 2021 15:39
full adder chain
`include "fulladder.sv"
module fulladder_chain #(parameter WIDTH)(input carry_in, [WIDTH-1:0] a, [WIDTH-1:0] b, output carry_out, [WIDTH-1:0] sum);
const int sizes[] = {WIDTH-2, 0};
const int CARRY_WIDTH = sizes.max;
wire [CARRY_WIDTH:0] carries;
@mcandre
mcandre / verilator-build-error.log
Last active October 9, 2021 20:06
verilator build error
$ make
------------------------------------------------------------
making verilator in src
make -C src
make[1]: Entering directory '/home/ubuntu/go/src/github.com/verilator/verilator/src'
mkdir -p obj_dbg
make -C obj_dbg -j 1 TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj serial
make[2]: Entering directory '/home/ubuntu/go/src/github.com/verilator/verilator/src/obj_dbg'
@mcandre
mcandre / half_adder.v
Created September 28, 2021 02:14
bad adder
module half_adder(
input clk,
a,
b,
output reg [0:0] sum,
carry
);
always @(posedge clk)
begin
sum <= a ^ b;
@mcandre
mcandre / half_adder.sv
Created September 28, 2021 01:43
half_adder SystemVerilog
module half_adder(
input clk,
a,
b,
output reg sum,
carry
);
always @(posedge clk)
begin
sum <= a ^ b;