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"""Investigating and implementing MCTS without the complications of the MTG simulator.""" | |
from collections import Counter | |
from copy import deepcopy | |
import math | |
import random | |
import cProfile | |
compose = lambda f: lambda g: lambda *args, **kwds: f(g(*args, **kwds)) |
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; %n - fp register n | |
; @n - int register n | |
; $n - lit int n | |
initial f32 top, left, bottom, right, 16.0f; | |
final f32 result[256]; | |
ld %0,$0 ; %0 = top | |
ld %1,$1 ; %1 = left | |
ld %2,$2 ; %2 = bottom |
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data _⊔_is_ : ℕ → ℕ → ℕ → Set where | |
m≥⊔nism : {m n : ℕ} | |
→ n ≤ m | |
--------- | |
→ m ⊔ n is m | |
m≤⊔nisn : {m n : ℕ} | |
→ m ≤ n | |
--------- | |
→ m ⊔ n is n |
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data ℕ : Set where | |
zero : ℕ | |
suc : ℕ → ℕ | |
{-# BUILTIN NATURAL ℕ #-} | |
data _≤_ : ℕ → ℕ → Set where | |
z≤n : {n : ℕ} | |
------- | |
→ zero ≤ n |
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DEBUG = True | |
macro ASSERT(e): | |
return \(if DEBUG: | |
if not $e: | |
raise AssertionError($(stringify(e)))) | |
def assert_equal(x, z): | |
# x and z are compared so they must have the same type |
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# normal macro | |
# \ is ` and $ is , | |
macro assert(e): | |
\(if DEBUG: | |
if not $e: | |
raise AssertionError($(stringify(e))) | |
# control structure macro |
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# normal macro | |
# \ is ` and $ is , | |
macro assert(e): | |
\(if DEBUG: | |
if not $e: | |
raise AssertionError($(stringify(e))) | |
# control structure macro |
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data X = X { _y :: Y } | |
data Y = Y1 { _y1 :: Int } | |
| Y2 { _y2 :: String } | |
x1 = X (Y1 0) | |
x2 = X (Y2 "Hello") | |
i1 = x1^.y.y1 -- error ?? | |
i2 = x2^.y.y1 -- error ?? | |
s1 = x1^.y.y2 |
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def tclass(*argnames, then_do=None): | |
if len(argnames) == 1 and isinstance(argnames[0], dict): | |
argnames = argnames[0] | |
def decorator(cls): | |
def inner_init(self, *args, **kwargs): | |
for argname, arg in zip(argnames, args): | |
self.__setattr__(argname, arg) | |
for argname in list(argnames)[len(args):]: | |
self.__setattr__(argname, argnames[argname]) |
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DCPU-16N Specification | |
Copyrights 1985 Mojang, Meisaka Yukara | |
Version 0.14 influenced by DCPU-16 (1.7) | |
=================================== SUMMARY ==================================== | |
* 16 bit CISC CPU design | |
* DCPU-16 compatibility functions | |
* 8/16 bit switchable memory word size (1 octet per address or 2 octets per address) |