Morgan Prior morganp

Authoring Ebooks: http://www.authoringebooks.com/
Create Your Own Programming Language: http://createyourproglang.com/
Exceptional Ruby: http://exceptionalruby.com/
JavaScript Performance Rocks: http://javascriptrocks.com/performance/
Redmine Tips: http://www.redminetips.com/
The SPDY Book: http://spdybook.com/
Rails 3 Upgrade Handbook: http://www.railsupgradehandbook.com/
Refactoring Redmine: http://www.refactoringredmine.com/book/
Bootstrapping Design: http://bootstrappingdesign.com/
Recipes With Backbone:

Update: Meetup had revived the group and are welcoming us back again. At the end, no data was lost, even though interim communications suggested it was.
We are happy that things had finally taken a positive turn and are happy to stay at meetup and grow our community to our next event and next next event. We are a little bit sorry that things went soar for awhile but what's important is that at the end both us and meetup had learned how to make things better for the next time.

Original post below....

Meetup, you've been bad, bad hosts!

TL;DR: Meetup had deleted my group, for what I beleive to be their mistake, yet they did not admit the mistake nor can they restore the data. I am deeply dissapointed from meetup and I've lost my trust in them.

To run a verilog simulation using irun and create a shm waveform file,

initial begin
  $shm_open("waves.shm"); $shm_probe("AS");
end

run with irun -access +r testcase.sv

Or create this tcl file:

	//To change the way (below) is displayed
	$display("%t", $realtime);

	//$timeformat(unit#, prec#, "unit", minwidth);
	$timeformat(-3, 2, " ms", 10); // -3 and " ms" give useful display msg

	unit is the base that time is to be displayed in, from 0 to -15
	precision is the number of decimal points to display.
	"unit" is a string appended to the time, such as " ns".
	minwidth is the minimum number of characters that will be displayed.

	--langdef=systemverilog
	--langmap=systemverilog:.sv.svh.svi.v
	--regex-systemverilog=/^\s(\b(static\|local\|virtual\|protected)\b)\s\bclass\b\s(\b\w+\b)/\3/c,class/
	--regex-systemverilog=/^\s(\b(static\|local\|virtual\|protected)\b)\s\btask\b\s(\b(static\|automatic)\b)?\s(\w+::)?\s(\b\w+\b)/\6/t,task/
	--regex-systemverilog=/^\s(\b(static\|local\|virtual\|protected)\b)\s\bfunction\b\s(\b(static\|automatic)\b)?\s\b\w+\b(\s\[.+\])\s(\w+::)?\s*(\b\w+\b)/\7/f,function/

	--regex-systemverilog=/^\s\bmodule\b\s(\b\w+\b)/\1/m,module/
	--regex-systemverilog=/^\s\bprogram\b\s(\b\w+\b)/\1/p,program/
	--regex-systemverilog=/^\s\binterface\b\s(\b\w+\b)/\1/i,interface/
	--regex-systemverilog=/^\s\btypedef\b\s+.\s+(\b\w+\b)\s*;/\1/e,typedef/