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phire / gist:96988e872a3e38ca37aaeeb15ad6ef1b

Last active February 15, 2021 13:33

re3 vc6 shaders

	MESA_SHADER_FRAGMENT prog 25/1 QPU:
	0x3e90f186bb800000 nop ; nop ; ldvary.r3; wrtmuc (tex[0].p0 \| 0x3)
	0x56403106bbcc0000 nop ; fmul r4, r3, rf0 ; wrtmuc (tex[0].p1 \| 0x0)
	0x3dd0054805fec000 fadd rf8, r4, r5 ; mov rf21, 0 ; ldvary.r0
	0x54003046bbc00000 nop ; fmul r1, r0, rf0
	0x3d10a18705829000 fadd rf7, r1, r5 ; nop ; ldvary.r2
	0x540030c6bbc80000 nop ; fmul r3, r2, rf0
	0x3d1121850582b000 fadd rf5, r3, r5 ; nop ; ldvary.r4
	0x54003006bbd00000 nop ; fmul r0, r4, rf0
	0x3d10618605828000 fadd rf6, r0, r5 ; nop ; ldvary.r1

phire / pthread-test.c

Created February 12, 2021 22:12

Trying to reproduce a bug in an emulator.

	// clang pthread-test.c -O3 -o pthread-test -lpthread

	#include <stdio.h>
	#include <stdint.h>
	#include <stdatomic.h>
	#include <pthread.h>
	#include <unistd.h>
	#include <stdlib.h>

	#define NUM_THREADS 64

phire / gist:54345f7826599d474d7eda4edb11ef6b

Created January 18, 2021 13:00

Geekbench5

	fex -n 500 --- https://browser.geekbench.com/v5/cpu/5960094
	fex -n 500 -m --- https://browser.geekbench.com/v5/cpu/5960557

phire / Matrix.py

Created December 11, 2020 08:06

	class MatrixRow(Elaboratable):
	def __init__(self, num_values, num_sets, num_sets_per_row, row_id):
	self.num_values = num_values
	self.num_sets = num_sets
	self.id = row_id
	addr_width = (num_values-1).bit_length()

	self.addr = Array(Array(Signal(addr_width, name=f"row_addr_{i}_{j}") for j in range(num_sets_per_row)) for i in range(num_sets))
	self.row_set = Array(Signal(name=f"row_set_{i}") for i in range(num_sets))

phire / gist:bd8f7a218aefe9bcd3ac6281170637ab

Created August 22, 2020 04:01

FTL inner PNG decoding loop IL

	IR 0x6f0190:
	(%ssa1) IRHeader #0x6f0190, %ssa2, #0
	(%ssa2) CodeBlock %ssa4, %ssa181, %ssa3
	(%ssa4 i0) Dummy
	%ssa5(GPR0) i64 = LoadContext #0x10, GPR
	%ssa6(GPR1) i64 = LoadContext #0x20, GPR
	%ssa7(GPR2) i64 = Add %ssa5(GPR0) i64, %ssa6(GPR1) i64
	%ssa8(GPR2) i8 = LoadMemTSO %ssa7(GPR2) i64, #0x1, #0x1, GPR
	(%ssa9 i64) StoreContext %ssa8(GPR2) i8, #0x48, GPR
	%ssa10(GPR3) i64 = Constant #0x1

phire / gist:ee67455a50ccf80aa26f2bddfc4d89ee

Created April 22, 2020 04:29

rpi4 dolphin perf

	- 98.53% 0.00% FIFO-GPU thread libpthread-2.30.so [.] start_thread ▒
	- start_thread ▒
	29.09% memcpy ▒
	- 20.30% VertexManagerBase::Flush ▒
	- 19.53% _mesa_Draw

phire / instruction_workings.txt

Created April 3, 2020 05:13

Attempt to understand T cycles of gameboy's SM83 cpu core

phire / LiteralFn

Created September 25, 2019 09:43

	#include <type_traits>
	#include <utility>

	template<class ReturnType, class...Xs>
	struct CallableBase {
	virtual ReturnType operator()(Xs...) const = 0;
	virtual ReturnType operator()(Xs...) = 0;
	virtual void copy(void*) const = 0;
	};

phire / goal.cpp

Created September 23, 2019 02:36

Goal for instruction table generation (doesn't compile)

	struct Instruction {
	const char* name;
	void (*execute)(m65816 &cpu); // Function that executes full instruciton
	void (*step)(m65816 &cpu); // Fuction that only executes a single cycle
	int cycle_count;

	Instruction(char *name, LiteralFn<bool(m65816, int)> fn)
	: name(name),
	execute(Execute<fn>),
	step(Step<fn>),

phire / round_to_zero_overflow_test.cpp

Created June 30, 2019 06:29

Minimal testcase for what I think might be an intel cpu bug

	// g++ round_to_zero_overflow_test.cpp && ./a.out
	// don't compile with optimisation, it might pre-caculate the result with the default rounding mode.
	#include <stdio.h>
	#include <limits>
	#include <cfenv>

	int main() {
	// the result of max_float + max_float is obviously infinity
	float test = std::numeric_limits<float>::max() + std::numeric_limits<float>::max();
	printf("%g\n", test); // prints "inf"

Scott Mansell phire