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extern crate llvm_sys;
use std::ffi::CStr;
use llvm_sys::core::*;
use llvm_sys::bit_reader::*;
fn main() {
unsafe {
let mut llvm_module = std::mem::uninitialized();
let mut buffer = std::mem::uninitialized();
def cone2(v1, v2):
return Cone(direction=normalize(v1+v2), angle_by_point=v1)
def cone3(v1, v2, v3):
return Cone(direction=normalize(cross(v2-v1, v3-v1)), angle_by_point=v1)
def cone4(v1, v2, v3, v4):
c = cone2(v1, v2)
if v3 not in c:
c = cone2(v1, v3)
@rrika
rrika / expected_output.v
Created March 27, 2018 01:59
Using CAQE to synthesize Verilog code
/* Generated by Yosys 0.7+528 (git sha1 3f007024, gcc 7.3.0 -fPIC -Os) */
(* top = 1 *)
module \7controller.aig (bit_control_0, bit_mode_0, bit_control_16, bit_control_15, bit_control_14, bit_control_13, bit_control_12, bit_control_11, bit_control_10, bit_control_9, bit_control_8, bit_control_7, bit_control_6, bit_control_5, bit_control_4, bit_control_3, bit_control_2, bit_control_1);
output bit_control_0;
output bit_control_1;
output bit_control_10;
output bit_control_11;
output bit_control_12;
output bit_control_13;
while ! ./_/build.sh 2> _/build.log; do
if [[ $(grep "No such file or directory" _/build.log) =~ .*error..(.*)..No.such.* ]]; then
missing=${BASH_REMATCH[1]}
echo "Adding file" $missing
mkdir -p $(dirname _missing/$missing)
touch _missing/$missing
elif [[ $(grep "was not declared in this scope" _/build.log) =~ .*error..‘([A-Z0-9_]*)’.was.not.* ]]; then
missing=${BASH_REMATCH[1]}
echo "Adding constant" $missing