kprotty

1. Every atomic object has a timeline (TL) of writes:

   • A write is either a store or a read-modify-write (RMW): it read latest write & pushed new one.
   • A write is either tagged Relaxed, Release, or SeqCst.
   • A read observes some write on the timeline:
     • On the same thread, future reads can't go backwards on the timeline.
     • A read is either tagged Relaxed, Acquire, or SeqCst.
     • RMWs can also be tagged Acquire (or AcqRel). If so, the Acquire refers to the "read" portion of "RMW".

2. Each thread has its own view of the world:

• Shared write timelines but each thread could be reading at different points.

attractivechaos

What is an "arena" in memory allocation?

I first leanred about "arena" when I was trying to understand the internal of [glibc malloc][glibc-alloc] around 2010, but I [later realized][trend] the concept is narrowly defined [in][arena1] [other][arena2] [context][arena3]. This blog post explains the difference in definition and the limitations in the so-called "arena allocators" we use today.

Background: why is malloc needed?

Raimo33

C Speed Optimization Checklist

This is a list of general-purpose optimizations for C programs, from the most impactful to the tiniest low-level micro-optimizations to squeeze out every last bit of performance. It is meant to be read top-down as a checklist, with each item being a potential optimization to consider. Everything is in order of speed gain.

Algorithm && Data Structures

Choose the best algorithm and data structure for the problem at hand by evaluating:

1. time complexity

viega

// defer.h
// [email protected]
// © 2025 Crash Override, Inc.
// Licensed under the BSD 3-Clause license

#pragma once
#include <stdint.h>

typedef struct n00b_defer_ll_t n00b_defer_ll_t;