sbourdeauducq

from cffi import FFI

ffi = FFI()
ffi.cdef("""
typedef int LLVMBool;

void LLVMDisposeMessage(char *Message);

typedef struct LLVMOpaqueModule *LLVMModuleRef;
LLVMModuleRef LLVMModuleCreateWithName(const char *ModuleID);

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/*
 *  byt_rt5670_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
 *                     Cherrytrail and Braswell, with RT5672 codec.
 *
 *  Copyright (C) 2014 Intel Corp
 *  Author: Subhransu S. Prusty <[email protected]>
 *          Mengdong Lin <[email protected]>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by

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from collections import OrderedDict
from itertools import product

from artiq import *


class ScanMe(HasEnvironment):
    def build(self):
        self.attr_argument("foo1", Scannable(LinearScan(1000, 2000, 100)))
        self.attr_argument("foo2", Scannable(LinearScan(1000, 2000, 100)))

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# Based on: https://github.com/Bekbolatov/SortingNetworks/blob/master/src/main/js/gr.js
def boms_get_partner(n, l, p):
    if p == 1:
        return n ^ (1 << (l - 1))
    scale = 1 << (l - p)
    box = 1 << p
    sn = n//scale - n//scale//box*box;
    if sn == 0 or sn == (box - 1):
        return n
    if (sn % 2) == 0:

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diff --git a/misoc/targets/sayma_amc.py b/misoc/targets/sayma_amc.py
index e15ba3a5..d34aeb6a 100755
--- a/misoc/targets/sayma_amc.py
+++ b/misoc/targets/sayma_amc.py
@@ -88,21 +88,20 @@ class BaseSoC(SoCSDRAM):
                             sdram_module.geom_settings, sdram_module.timing_settings)
         self.csr_devices.append("ddrphy")
 
-        if not self.integrated_rom_size:
-            spiflash_pads = platform.request("spiflash")

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# openocd -f sayma_new.cfg -c "pld load 0 rtm.bit; exit"
# openocd -f sayma_new.cfg -c "pld load 1 amc.bit; exit"

interface ftdi
ftdi_device_desc "Quad RS232-HS"
ftdi_vid_pid 0x0403 0x6011
# if there are multiple Sayma:
#ftdi_location 5:2
ftdi_channel 0
# EN_USB_JTAG on ADBUS7: out, high

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open_checkpoint top_route.dcp
set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
set_property CLKOUT3_PHASE 0.0 [get_cells crg_main_mmcm]
write_bitstream top_0000.bit
set_property CLKOUT3_PHASE 22.5 [get_cells crg_main_mmcm]
write_bitstream top_0225.bit
set_property CLKOUT3_PHASE 45.0 [get_cells crg_main_mmcm]
write_bitstream top_0450.bit
set_property CLKOUT3_PHASE 67.5 [get_cells crg_main_mmcm]
write_bitstream top_0675.bit

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import sys
import select
import time
from collections import OrderedDict

from artiq.experiment import *


def chunker(seq, size):
    res = []

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@@ -318,12 +318,14 @@ pub mod hmc7043 {
          *  Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
          *  16*25ps = 400ps: limit analog delay to 16 steps instead of 32.
          */
+        let analog_delay = (phase % 17) as u8;
+        let digital_delay = (phase / 17) as u8;
         if dacno == 0 {
-            write(0x00d5, (phase & 0xf) as u8);
-            write(0x00d6, ((phase >> 4) & 0x1f) as u8);
+            write(0x00d5, analog_delay);

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diff --git a/artiq/firmware/runtime/Cargo.toml b/artiq/firmware/runtime/Cargo.toml
index f7eb87ac..6c36c0fa 100644
--- a/artiq/firmware/runtime/Cargo.toml
+++ b/artiq/firmware/runtime/Cargo.toml
@@ -19,6 +19,7 @@ failure_derive = { version = "0.1", default-features = false }
 byteorder = { version = "1.0", default-features = false }
 cslice = { version = "0.3" }
 log = { version = "0.4", default-features = false }
+crc = { version = "1.7", default-features = false }
 managed = { version = "0.6", default-features = false, features = ["alloc", "map"] }