ssvb

https://gist.github.com/ssvb/56da061451216a37080f

# This program runs a set of tests, which are repeatedly doing
# memcpy over N bytes sized memory buffer. Each individual
# test is calibrated to run a sufficient number of iterations
# to make its duration close to 300 ms.
# For each line in the report below, tests are run 20
# times normally and 20 times slightly slower than normal
# (the difference is shown in the first column). The timings
# of these runs are also measured using gettimeofday(...)

ssvb

https://gist.github.com/ssvb/56da061451216a37080f

# This program runs a set of tests, which are repeatedly doing
# memcpy over N bytes sized memory buffer. Each individual
# test is calibrated to run a sufficient number of iterations
# to make its duration close to 300 ms.
# For each line in the report below, tests are run 20
# times normally and 20 times slightly slower than normal
# (the difference is shown in the first column). The timings
# of these runs are also measured using gettimeofday(...)

ssvb

https://gist.github.com/ssvb/56da061451216a37080f

# This program runs a set of tests, which are repeatedly doing
# memcpy over N bytes sized memory buffer. Each individual
# test is calibrated to run a sufficient number of iterations
# to make its duration close to 300 ms.
# For each line in the report below, tests are run 20
# times normally and 20 times slightly slower than normal
# (the difference is shown in the first column). The timings
# of these runs are also measured using gettimeofday(...)

ssvb

# str sp, [pc]
fel fill 0x10000 1 0x00
fel fill 0x10001 1 0xd0
fel fill 0x10002 1 0x8f
fel fill 0x10003 1 0xe5

# bx lr
fel fill 0x10004 1 0x1e
fel fill 0x10005 1 0xff
fel fill 0x10006 1 0x2f

ssvb

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index f01846e..cd06c72 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -106,6 +106,10 @@ void s_init(void)
 	 * access gets messed up (seems cache related) */
 	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 #endif
+#if defined CONFIG_MACH_SUN6I
+	/* Allow access to RTC clock from non-secure mode */

ssvb

diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index ee219f8..f826a51 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -13,3 +13,7 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_USB0_ID_DET="PH4"

ssvb

#!/bin/sh
# Convert a raw binary image into an ELF file suitable for loading into a disassembler
#
# Usage: bin2elf input_binary_file output_elf_file base_address

cat > raw$$.ld <<EOF
SECTIONS
{
EOF

ssvb

== 528 MHz ==

DRAM:
0: 
1: 
2: 
3: 
4: 
5: 
6: 

ssvb

From bd714466d306c1affb94da77b3343797c5e6450d Mon Sep 17 00:00:00 2001
From: Siarhei Siamashka <[email protected]>
Date: Sat, 12 Dec 2015 04:30:55 +0200
Subject: [PATCH] OpenRISC (or1k) support for GCC 4.9.2

This is the difference between 80794b79e069d2dc28e15d2843ef55a7066ed9a1
from https://github.com/openrisc/or1k-gcc.git and vanilla GCC 4.9.2
---
 ChangeLog.or1k                                     |    8 +
 config.guess                                       |    5 +-

ssvb

From 29f1fc1eda7db3907a1f0f0ca7f2bdd0b541c62b Mon Sep 17 00:00:00 2001
From: Siarhei Siamashka <[email protected]>
Date: Mon, 14 Dec 2015 08:47:38 +0200
Subject: [PATCH] OpenRISC support for GCC 5.2.0

This is the difference between 1672972457156a6b701152f0f1c7c8696220a4dc
from https://github.com/openrisc/or1k-gcc.git and vanilla GCC 5.2.0

---
 ChangeLog.or1k                                     |    8 +