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From 30633a810bb0047295965e7b32f1a0cd12d8d93e Mon Sep 17 00:00:00 2001
From: Krylon360 <[email protected]>
Date: Thu, 9 Aug 2012 10:16:20 -0600
Subject: [PATCH 1/2] SurfaceFlinger: Removal of NO_RGBX_8888 flag for OMAP3
Removing this will allow color format of surface to be set for RGBX8888
that can improve performance for 32 bit framebuffer.
Tested on Nook Color with CM10
TI's commit can be found here:
From b93d7551841d235ac1fa50ae2d315afb39879005 Mon Sep 17 00:00:00 2001
From: Steven Luo <[email protected]>
Date: Fri, 29 Mar 2013 00:32:46 -0700
Subject: [PATCH] init.encore.rc: remove obsolete ro.debuggable=1 trigger
Whatever purpose this trigger once served is now handled by the
init.encore.usb.rc triggers introduced in ICS, and keeping it appears to
tickle an init bug concerning /dev/socket sockets handling and
restarting of already-started services.
@steven676
steven676 / gist:4192300
Created December 3, 2012 02:50
tweak SmartReflex OPP5 disable patch
diff --git a/arch/arm/mach-omap2/smartreflex-class1p5.c b/arch/arm/mach-omap2/smartreflex-class1p5.c
index 372715c..17463d2 100644
--- a/arch/arm/mach-omap2/smartreflex-class1p5.c
+++ b/arch/arm/mach-omap2/smartreflex-class1p5.c
@@ -184,7 +184,8 @@ static void sr_class1p5_calib_work(struct work_struct *work)
__func__, volt_data->volt_nominal,
voltdm->name);
volt_data->volt_calibrated = volt_data->volt_nominal;
- goto work_disable;
+ u_volt_current = omap_vp_get_curr_volt(voltdm);
@steven676
steven676 / 0001-encore-disable-SmartReflex-calibration-for-OPP5-when.patch
Created December 1, 2012 04:48
[PATCH] encore: disable SmartReflex calibration for OPP5 when overclocking
From dd0e7090d23697f61fd894766a9cc0105d861a61 Mon Sep 17 00:00:00 2001
From: Steven Luo <[email protected]>
Date: Sat, 1 Dec 2012 00:29:35 -0800
Subject: [PATCH] encore: disable SmartReflex calibration for OPP5 when overclocking
It appears the SR class 1.5 calibration process itself is causing
problems for some users at the non-standard 1100/1200 MHz overclocks.
Disable the calibration process for OPP5, effectively locking the
voltage for that OPP to 1.375 V.
---
@steven676
steven676 / gist:4092657
Created November 17, 2012 02:11
Boxer panel: add Kconfig option to disable 24-bit display
From 1765ccb5b8d7a6809fb5ca49a2717af4f1208f9e Mon Sep 17 00:00:00 2001
From: Steven Luo <[email protected]>
Date: Fri, 16 Nov 2012 18:10:00 -0800
Subject: [PATCH] Boxer panel: add Kconfig option to disable 24-bit display
24-bit color display hurts performance by quite a bit on Encore, so
disable it by default and create a new option to enable it.
XXX: This should probably be runtime configurable as well.
---
@steven676
steven676 / gist:4084493
Created November 16, 2012 05:42
DO NOT APPLY THIS DIFF!!!!!!!!!! BACK IT OUT BEFORE applying the new overvolt patch
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index 63241a3..554ae51 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -91,6 +91,7 @@ struct omap_vdd_dep_info omap34xx_vddmpu_dep_info[] = {
/* Amount in uV to add to SmartReflex-calculated voltages as a safety margin */
#define OMAP3630_SR_MPU_DEFAULT_MARGIN 37500
#define OMAP3630_SR_MPU_DEFAULT_MARGIN_1G 62500
+#define OMAP3630_SR_MPU_DISABLE_SR_MARGIN 125000
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 40a4c63..477ab8a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -274,6 +274,29 @@ config MACH_ENCORE
select REGULATOR_FIXED_VOLTAGE
select WLAN_POWER_EVT1
+choice
+ bool "MPU clock speed for Encore"
diff --git a/arch/arm/mach-omap2/smartreflex-class1p5.c b/arch/arm/mach-omap2/smartreflex-class1p5.c
index 4d3e5fc..e14c094 100644
--- a/arch/arm/mach-omap2/smartreflex-class1p5.c
+++ b/arch/arm/mach-omap2/smartreflex-class1p5.c
@@ -303,6 +303,7 @@ done_calib:
__func__, voltdm->name, u_volt_margin,
volt_data->volt_margin, volt_data->volt_nominal,
u_volt_current);
+ u_volt_safe = volt_data->volt_nominal;
}
@steven676
steven676 / 0001-OMAP-PM-Optimize-cpufreq-transition-latency.patch
Created November 13, 2012 08:36
[PATCH] OMAP PM: Optimize cpufreq transition latency
From 2f8ab1b7d5d1aa60a52c9f8a94f497eb4ae1fbb1 Mon Sep 17 00:00:00 2001
From: Vishwanath BS <[email protected]>
Date: Thu, 25 Nov 2010 13:38:11 +0000
Subject: [PATCH] OMAP PM: Optimize cpufreq transition latency
Currently cpufreq transition latency value does not really reflect the actual
OMAP OPP transition delay. This patch has the actual latency value.
I did profile the DVFS latency on OMAP3430, OMAP3630 and OMAP4 for worstcase(MPU and Core together) and found that in none of these platforms, transiton value
goes beyong 10ms. Added a buffer of 20ms to avoid too frequent ondemand timer
expiry.
@steven676
steven676 / 0001-OMAP3-abort-suspend-if-omap2_gpio_prepare_for_idle-r.patch
Created November 5, 2012 01:35
[PATCH] OMAP3: abort suspend if omap2_gpio_prepare_for_idle() reports failure
From 6c162e038ab60c5035145bd85a7beb95781edb99 Mon Sep 17 00:00:00 2001
From: Steven Luo <[email protected]>
Date: Sun, 4 Nov 2012 17:26:59 -0800
Subject: [PATCH] OMAP3: abort suspend if omap2_gpio_prepare_for_idle() reports failure
Otherwise, since d40caba... ("ARM: omap4: gpio: abort suspend if a level
wake interrupt is pending") and 05647ea... ("OMAP3: PM: Fix compile
after gpio wakeup API change"), we end up going into suspend with GPIOs
in an inconsistent state.
---