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#pragma once | |
#include <list> | |
template<class T> | |
class BST { | |
public: | |
struct Node { | |
T value; | |
Node *lhs, *rhs, *parent; |
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#pragma once | |
template<class T> T gcd(T a, T b) { | |
T c; | |
while ( a != 0 ) { c = a; a = b%a; b = c; } | |
return b; | |
} | |
template<class T> T lcm(T a, T b) { | |
return a / gcd(a,b) * b; |
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#pragma once | |
#include <string> | |
#include <functional> | |
#include <vector> | |
#include <map> | |
class options { | |
public: |
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#pragma once | |
#include <iostream> | |
#ifdef DEBUG | |
#define debug std::cout | |
#else | |
#define debug true ? : std::cout | |
#endif |
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#include <vector> | |
#include <algorithm> | |
#include <limits> | |
template<class T> | |
class segtree { | |
public: | |
explicit segtree(size_t N=1, T init=std::numeric_limits<T>::max()) | |
: _init(init), _N(N), _tree(4*N,init) {} |
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#pragma once | |
#include <vector> | |
template<class T> | |
class BIT { | |
public: | |
explicit BIT(size_t N=1) : _bit(N) {} | |
void add(size_t i, T val) { | |
while (i < _bit.size()){ |
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#pragma once | |
#include <list> | |
template<class T> | |
class union_find { | |
public: | |
struct node { | |
node *parent = nullptr; | |
T data; |
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#pragma once | |
#include <vector> | |
template<class T, size_t N = 1> | |
class vec : public std::vector<vec<T,N-1>> { | |
public: | |
explicit vec() : std::vector<vec<T,N-1>>() {} | |
template<class Size, class... Sizes> | |
explicit vec(Size n, Sizes... ns) : std::vector<vec<T,N-1>>(n,vec<T,N-1>(ns...)) {} |
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#pragma once | |
#include <algorithm> | |
template<class Iterator> | |
bool next_combination(Iterator first1, Iterator last1, Iterator first2, Iterator last2) { | |
if((first1 == last1) || (first2 == last2)) return false; | |
Iterator m1 = last1, m2 = last2; --m2; | |
while(--m1 != first1 && !(*m1 < *m2)) {} | |
const bool result = !((m1 == first1) && !(*first1 < *m2)); |
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# Makefile for iVerilog testing | |
SRC_DIR := src | |
TEST_DIR := test | |
SIM_DIR := sim | |
TESTS := $(sort $(patsubst $(TEST_DIR)/%.v,$(SIM_DIR)/%.vcd,$(wildcard $(TEST_DIR)/test_*.v))) | |
VERILOGS := $(sort $(wildcard $(SRC_DIR)/*.v)) | |
.PHONY: $(SIM_DIR)/test_%.sim | |
$(SIM_DIR)/test_%.sim: $(TEST_DIR)/test_%.v |