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Ravi Teja Gudapati tejainece

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tejainece / PppRouterC.nc
Created January 10, 2014 00:58
TinyOS basic PPPRouter example. This does nothing useful. However, you can use it to check if you can ping your mote.
#include <iprouting.h>
#include "ppp.h"
configuration PppRouterC {
} implementation {
components PppRouterP;
components MainC;
PppRouterP.Boot -> MainC;
@tejainece
tejainece / Sample output running threadstack.c
Last active January 3, 2016 17:49
Do threads have their own stack and heap?
Main thread info
Stack variable address : 0x7fff70649a4c
main function address : 0x4006dd
printInfo function address : 0x4007b5
Global variable address : 0x601058
Static variable address : 0x601060
Thread 2 thread info
Stack variable address : 0x7f730be3be6c
main function address : 0x4006dd
@tejainece
tejainece / fixed_point.py
Last active January 3, 2016 22:09
Fixed point arithmetic library fro Python. I developed this to aid me in studying Circuit perspective of Computer Arithmetic.
def bin_complement(a):
tmpBin = list(a)
for i, c in enumerate(tmpBin):
if c == "1":
tmpBin[i] = "0"
else:
tmpBin[i] = "1"
return ''.join(tmpBin)
def bin_increment(a):
@tejainece
tejainece / binary_multiple.py
Created January 21, 2014 16:32
Binary multiplication
from math import ceil, log
def shift_and_sign_extend(num_list, shift=1):
length = 0
#find the length
for index, element in enumerate(numlist):
tEl = element + '0' * (index * shift)
tLen = len(tEl)
numlist[index] = tEl
if length < tLen:
@tejainece
tejainece / unsigned_binary_mul.py
Created January 21, 2014 17:57
Unsigned multiplication
from math import ceil, log
def shift_and_sign_extend(num_list, shift=1):
length = 0
#find the length
for index, element in enumerate(numlist):
tEl = element + '0' * (index * shift)
tLen = len(tEl)
numlist[index] = tEl
if length < tLen:
@tejainece
tejainece / BoothPartialProductGenerater.vhdl
Last active January 4, 2016 04:19
Partial product generator for 16 bit radix 4 Booth multiplier
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:00:36 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
@tejainece
tejainece / read_output_correct.vhd
Created January 29, 2014 14:12
Read output ports in Verilog and VHDL. This was written for my blog post.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ReadOutputCorrect is
PORT (
in1 : IN STD_LOGIC;
in2 : IN STD_LOGIC;
in3 : IN STD_LOGIC;
o1 : OUT STD_LOGIC;
o2 : OUT STD_LOGIC
@tejainece
tejainece / ThisRegWontProduceReg.v
Created January 29, 2014 17:59
Not all variables declared as reg gets synthesized to registers in verilog.
module ThisRegWontProduceReg(
output reg o1,
input i1, i2, i3
);
always @(i1, i2, i3) begin
if (i1 == 1'b1) begin
o1 <= i2;
end else begin
o1 <= i3;
@tejainece
tejainece / RegAssignmentWrong.v
Created January 29, 2014 18:22
Where not to assign wire and reg in Verilog. This was written for demonstration purposes in my blog post.
module RegAssignmentWrong(
output reg o,
input in1,
input in2
);
assign o = in1 & in2;
endmodule
@tejainece
tejainece / Makefile
Last active August 29, 2015 13:56
Motion search using CUDA
all: motion_search_cuda motion_search_cpu
motion_search_cuda: motion_search_cuda.cu
nvcc -o $@ $^
motion_search_cpu: motion_search_cpu.c
gcc -o $@ $^ -std=c99
clean:
rm motion_search_cuda motion_search_cpu output_cuda.yuv output_cpu.yuv