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Todd Stellanova tstellanova

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tstellanova / Dockerfile-libfaketime
Last active January 17, 2019 04:25 — forked from miguelmota/Dockerfile
Docker faketime lib example
FROM node:8
WORKDIR /
RUN git clone https://github.com/wolfcw/libfaketime.git
WORKDIR /libfaketime/src
RUN make install
WORKDIR /usr/src/app
COPY package.json ./
@tstellanova
tstellanova / broadcastify_listen.py
Created June 25, 2019 13:45 — forked from wiseman/broadcastify_listen.py
Python 3 code for taking an mp3 stream, such as a police scanner feed from broadcastify, and running it through speech recognition.
"""Does utterance segmentation and speech recognition on an mp3 stream
(like from broadcastify...)
Requires that ffmpeg be installed, and a Microsoft cognitive speech
services API key
(see https://azure.microsoft.com/en-us/try/cognitive-services/?api=speech-services).
"""
import audioop
import collections
@tstellanova
tstellanova / STM32H7_SWO_Output_Solution.py
Created February 7, 2020 00:27 — forked from mofosyne/STM32H7_SWO_Output_Solution.py
This generates codes that enables SWO output for STM32H7 and was tested on NUCLEO-H743ZI2. This is required because stm32h7 changed the registers that OpenOCD expects for SWO output.
#!/usr/bin/env python3
"""
# STM32H7 SWO Output Solution
Author: Brian Khuu 2020
Main Copy: https://gist.github.com/mofosyne/178ad947fdff0f357eb0e03a42bcef5c
This generates codes that enables SWO output for STM32H7 and was tested on NUCLEO-H743ZI2.
This is required because stm32h7 changed the registers that OpenOCD expects for SWO output.
Best to use 400Mhz, tried lower... but had issue with getting stable uart output
@tstellanova
tstellanova / itm_en.rs
Created March 13, 2020 21:30 — forked from richardeoin/itm_en.rs
Enable ITM output over the SWO pin for STM32H7 parts. The output is manchester coded and can be received by a debugger - eg. blackmagic probe
/// Enables ITM
///
/// If swo_enable is true, then the SWO output pin will be enabled
fn low_level_itm(dbgmcu: &stm32::DBGMCU, swo_enable: bool) {
// ARMv7-M DEMCR: Set TRCENA. Enables DWT and ITM units
unsafe { *(0xE000_EDFC as *mut u32) |= 1 << 24 };
// Ensure debug blocks are clocked before interacting with them
dbgmcu.cr.modify(|_, w| {
w.d1dbgcken()