upa

#!/usr/bin/env python3


import os
import sys
import time
import subprocess


from optparse import OptionParser

upa

-- This test does the following:
--	2. Send UDP packets from NIC 1 to NIC 2
--

local mg     = require "moongen"
local memory = require "memory"
local device = require "device"
local ts     = require "timestamping"
local filter = require "filter"
local hist   = require "histogram"

upa

local mg     = require "moongen"
local memory = require "memory"
local device = require "device"
local stats	 = require "stats"
local log    = require "log"
local timer  = require "timer"


local pktctrs = {}

upa

#!/bin/bash

ip=/bin/ip
ifc=/sbin/ifconfig

intf=$1
configdir=ns-configs

if [ "$intf" == "" ]; then
	echo $0 [raw interface]

upa

keybase.md

Keybase proof

I hereby claim:

• I am upa on github.
• I am upa (https://keybase.io/upa) on keybase.
• I have a public key ASDYBl8z7taGpmVyem5c7-O07Y0gU9k7V2fmHuFGuhbiSwo

upa

*.png
*.json

upa

// fthash.v
// embedded sum of src ip and first half of dst ip to src MAC 8 bit

module one_port #(
	// Master AXI Stream Data width
	parameter C_M_AXIS_DATA_WIDTH=256,
	parameter C_M_AXIS_TUSER_WIDTH=128,
	parameter C_S_AXIS_DATA_WIDTH=256,
	parameter C_S_AXIS_TUSER_WIDTH=128,
	parameter SRC_PORT_POS=16,

upa

// fthash.v
// embedded sum of src ip and first half of dst ip to src MAC 8 bit

module one_port #(
		  // Master AXI Stream Data width
		  parameter C_M_AXIS_DATA_WIDTH=256,
		  parameter C_M_AXIS_TUSER_WIDTH=128,
		  parameter C_S_AXIS_DATA_WIDTH=256,
		  parameter C_S_AXIS_TUSER_WIDTH=128,
		  parameter SRC_PORT_POS=16,

upa

// fthash.v
// embedded sum of src ip and first half of dst ip to src MAC 8 bit

module one_port #(
	// Master AXI Stream Data width
	parameter C_M_AXIS_DATA_WIDTH=256,
	parameter C_M_AXIS_TUSER_WIDTH=128,
	parameter C_S_AXIS_DATA_WIDTH=256,
	parameter C_S_AXIS_TUSER_WIDTH=128,
	parameter SRC_PORT_POS=16,

upa

// sdhash.v
// embedded sum of src ip and first half of dst ip to src MAC 8 bit

// working at 2016/5/26 4:14
module one_port #(
	// Master AXI Stream Data width
	parameter C_M_AXIS_DATA_WIDTH=256,
	parameter C_M_AXIS_TUSER_WIDTH=128,
	parameter C_S_AXIS_DATA_WIDTH=256,
	parameter C_S_AXIS_TUSER_WIDTH=128,