Resistor Model in Verilog-A, used in Cadence Virtuoso

Resistor_Verilog-AMS.v

`include "discipline.h"
 
module polyres_hdl (n2, n1, ctrl2, ctrl1); 
//(wr, lr, rtemp, jc1a, jc1b, jc2a, jc2b, tc1, tc2, etch, tnom, rsh0, rmaxvcoef, rminvcoef)
electrical n2, n1, ctrl2, ctrl1;
 
parameter real lr=0.0;parameter real wr=0.0;
parameter real rtemp=($temperature - 273.15);
parameter real jc1a = 0;parameter real jc1b = 0;
parameter real jc2a = 0;parameter real jc2b= 0;
parameter real tc1 = 0;parameter real tc2 = 0;
parameter real etch = 0;parameter real tnom = 25.0;
parameter real rsh0 = 1;parameter real rmaxvcoef = 3;
parameter real rminvcoef = 0.33;
 
real dt, absv, vc1, vc2, tcoef, vcoef, r0, weff;
 
analog begin
    dt = (rtemp - tnom);
    vc1 = jc1a + jc1b / lr; vc2 = (jc2a + jc2b / lr) / lr;
    absv = abs(V(ctrl2, ctrl1));
    tcoef = 1.0 + dt * (tc1 + dt * tc2);
    vcoef = 1.0 + absv * (vc1 + absv * vc2);
    vcoef = min(vcoef, rmaxvcoef);
    vcoef = max(vcoef, rminvcoef);
    weff = (wr - 2.0 * etch);
    r0 = rsh0 * lr / weff * tcoef * vcoef;
    V(n2, n1) <+ I(n2, n1) * r0;
end
endmodule