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testing uefi on core3566 https://github.com/jaredmcneill/quartz64_uefi/pull/56
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DDR Version V1.11 20211103 | |
ln | |
ddrconfig:7 | |
LP4 MR14:0x4d | |
LPDDR4, 324MHz | |
BW=32 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=4096MB | |
change to: 324MHz | |
PHY drv:clk:38,ca:38,DQ:30,odt:0 | |
vrefinner:41%, vrefout:41% | |
dram drv:40,odt:0 | |
clk skew:0x58 | |
change to: 528MHz | |
PHY drv:clk:38,ca:38,DQ:30,odt:0 | |
vrefinner:41%, vrefout:41% | |
dram drv:40,odt:0 | |
clk skew:0x70 | |
change to: 780MHz | |
PHY drv:clk:38,ca:38,DQ:30,odt:0 | |
vrefinner:41%, vrefout:41% | |
dram drv:40,odt:0 | |
clk skew:0x58 | |
change to: 1560MHz(final freq) | |
PHY drv:clk:38,ca:38,DQ:30,odt:60 | |
vrefinner:16%, vrefout:29% | |
dram drv:40,odt:80 | |
clk skew:0x15 | |
out | |
U-Boot SPL board init | |
U-Boot SPL 2017.09-gaaca6ffec1-211203 #zzz (Dec 03 2021 - 18:42:16) | |
unknown raw ID phN | |
unrecognized JEDEC id bytes: 00, 00, 00 | |
Trying to boot from MMC2 | |
No misc partition | |
Trying fit image at 0x4000 sector | |
Not fit magic | |
Trying fit image at 0x5000 sector | |
## Verified-boot: 0 | |
## Checking atf-1 0x00040000 ... sha256(fe4f274c06...) + OK | |
## Checking uboot 0x00a00000 ... OK | |
## Checking fdt 0x00b00000 ... sha256(18bb173df9...) + OK | |
## Checking atf-2 0x00068000 ... sha256(8d44036095...) + OK | |
## Checking atf-3 0xfdcd0000 ... sha256(e410275b51...) + OK | |
## Checking atf-4 0xfdcc9000 ... sha256(990c53fc01...) + OK | |
## Checking atf-5 0x00066000 ... sha256(315a4195a9...) + OK | |
## Checking optee 0x08400000 ... sha256(08e1fd41e1...) + OK | |
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000) | |
Total: 351.194 ms | |
INFO: Preloader serial: 2 | |
NOTICE: BL31: v2.3():v2.3-181-gc9a647cae:cl | |
NOTICE: BL31: Built : 10:55:41, Oct 18 2021 | |
INFO: GICv3 without legacy support detected. | |
INFO: ARM GICv3 driver initialized in EL3 | |
INFO: pmu v1 is valid | |
INFO: dfs DDR fsp_param[0].freq_mhz= 1560MHz | |
INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz | |
INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz | |
INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz | |
INFO: Using opteed sec cpu_context! | |
INFO: boot cpu mask: 0 | |
INFO: BL31: Initializing runtime services | |
INFO: BL31: Initializing BL32 | |
I/TC: | |
I/TC: OP-TEE version: 3.13.0-595-gf5add58be #hisping.lin (gcc version 10.2.1 20201103 (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16))) #26 Tue Dec 21 15:50:44 CST 2021 aarch64 | |
I/TC: Primary CPU initializing | |
I/TC: Primary CPU switching to normal world boot | |
INFO: BL31: Preparing for EL3 exit to normal world | |
INFO: Entry point address = 0xa00000 | |
INFO: SPSR = 0x3c9 | |
UEFI firmware (version v1.1-core3566 built at 15:58:03 on Nov 12 2023) | |
Synchronous Exception at 0x00000000ECAB6070 |
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