Strange VHDL Behavior

test.vhd

library ieee;
use ieee.std_logic_1164.all;

entity counter is
end entity;
-----------------------------------------
architecture dual_counter of counter is
 signal sig1,sig2: natural;
 signal clk : std_logic := '0';
 signal var1_o : natural := 0;
 signal var2_o : natural := 0;
 signal sig1_o : natural := 0;
 signal sig2_o : natural := 0;
begin
    clk <= not clk after 1 ns;
-----------------------------------------

with_signal1: process(clk) begin 
if (clk'event and clk='1') then
-- Changed here
    if (sig1=25) then
        sig1 <= 1;
    end if;
    -- This line used to be above
    sig1 <= sig1 + 1;
-- End Changes
end if;
sig1_o <= sig1;
end process with_signal1;
-- continued on the next page

-----------------------------------------
with_variable1: process(clk)
 variable var1: natural;
begin
 if (clk'event and clk='1') then
 var1 := var1 + 1;
 if (var1=25) then
 var1 := 1;
 end if;
 end if;
 var1_o <= var1;
end process with_variable1;
-----------------------------------------
with_variable2: process(clk)
 variable var2: natural;
begin
 if (clk'event and clk='1') then
 if (var2=25) then
 var2 := 1;
 else
 var2:=var2+1;
 end if;
 end if;
 var2_o <= var2;
end process with_variable2;
-----------------------------------------
with_signal2: process(clk)
begin
 if (clk'event and clk='1') then
 if (sig2=25) then
 sig2 <= 1;
 else
 sig2<=sig2+1;
 end if;
 end if;
 sig2_o <= sig2;
end process with_signal2;

end architecture;