cuterunner-vga.v

module top(r0, r1, g0, g1, b0, b1, hsync, vsync,
    clk_,
    but0, but1, but2, but3,
    led4);

(* LOC = "FB1_2" *)
output r0;
(* LOC = "FB1_6" *)
output r1;
(* LOC = "FB1_3" *)
output g0;
(* LOC = "FB1_7" *)
output g1;
(* LOC = "FB1_4" *)
output b0;
(* LOC = "FB1_8" *)
output b1;
(* LOC = "FB1_1" *)
output reg hsync;
(* LOC = "FB1_5" *)
output reg vsync;

(* LOC = "FB1_14" *)
input but0;
(* LOC = "FB1_15" *)
input but1;
(* LOC = "FB1_16" *)
input but2;
(* LOC = "FB3_1" *)     // dedicated input
input but3;

(* LOC = "FB1_9" *)
output led4;

(* LOC = "FB2_5" *)
input clk_;

assign led4 = 0;

// NOTE: Must manually instantiate BUFG
wire clk;
BUFG bufg0 (
    .I(clk_),
    .O(clk),
);

reg [10:0] dotcnt;
reg [9:0] rowcnt;

reg hporch;
reg vporch;
wire porch;

assign porch = hporch | vporch;

// assign {b1, b0, g1, g0, r1, r0} = (dotcnt[6:1]) & {6{!porch}};

always @(*)
    if (porch) begin
        r1 <= 0;
        r0 <= 0;
        g1 <= 0;
        g0 <= 0;
        b1 <= 0;
        b0 <= 0;
    end else begin
        if (rowcnt >= 160 && rowcnt < 320) begin
            if (dotcnt >= 128 && dotcnt < 256) begin
                if (but0) begin
                    r1 <= 0;
                    r0 <= 1;
                end else begin
                    r1 <= 1;
                    r0 <= 1;
                end
            end else if (dotcnt >= 896 && dotcnt < 1024) begin
                if (but3) begin
                    r1 <= 0;
                    r0 <= 1;
                end else begin
                    r1 <= 1;
                    r0 <= 1;
                end
            end else begin
                r1 <= 0;
                r0 <= 0;
            end

            if (dotcnt >= 384 && dotcnt < 512) begin
                if (but1) begin
                    g1 <= 0;
                    g0 <= 1;
                end else begin
                    g1 <= 1;
                    g0 <= 1;
                end
            end else if (dotcnt >= 896 && dotcnt < 1024) begin
                if (but3) begin
                    g1 <= 0;
                    g0 <= 1;
                end else begin
                    g1 <= 1;
                    g0 <= 1;
                end
            end else begin
                g1 <= 0;
                g0 <= 0;
            end

            if (dotcnt >= 640 && dotcnt < 768) begin
                if (but2) begin
                    b1 <= 0;
                    b0 <= 1;
                end else begin
                    b1 <= 1;
                    b0 <= 1;
                end
            end else if (dotcnt >= 896 && dotcnt < 1024) begin
                if (but3) begin
                    b1 <= 0;
                    b0 <= 1;
                end else begin
                    b1 <= 1;
                    b0 <= 1;
                end
            end else begin
                b1 <= 0;
                b0 <= 0;
            end
        end else begin
            r1 <= 0;
            r0 <= 0;
            g1 <= 0;
            g0 <= 0;
            b1 <= 0;
            b0 <= 0;
        end
    end

always @(posedge clk)
    if (dotcnt == 1587)
        dotcnt <= 0;
    else
        dotcnt <= dotcnt + 1;

always @(posedge clk)
    if (dotcnt == 1587)
        if (rowcnt == 524)
            rowcnt <= 0;
        else
            rowcnt <= rowcnt + 1;

// 1588 x 525 total time at 50 MHz
// 59.97 Hz, trying to mimic timing for 640x480

// visible area is set up to start when counters are at 0
// so we have   visible | fp | sync | bp
//                 1270 | 32 | 191  | 95

always @(*)
    if (dotcnt >= 1270)
        hporch <= 1;
    else
        hporch <= 0;

always @(*)
    if ((dotcnt >= 1270 + 32) && (dotcnt < 1270 + 32 + 191))
        hsync <= 0;
    else
        hsync <= 1;

always @(*)
    if (rowcnt >= 480)
        vporch <= 1;
    else
        vporch <= 0;

always @(*)
    if ((rowcnt >= 480 + 10) && (rowcnt < 480 + 10 + 2))
        vsync <= 0;
    else
        vsync <= 1;

endmodule