problemcontext.tex

In modern embedded systems, energy efficiency is one of the most important
design aspects. As there is only limited energy available per battery-life
cycle, the amount of computation that can be performed is heavily constrained.
General purpose processors provide high programmability at a high level of
abstraction, but this comes at a cost of lower performance, lower energy
efficiency or both.

In contrast, Application Specific Integrated Circuits (\textsc{ASIC}s) can offer
high performance at a high energy efficiency, but the operations performed by an
ASIC are fixed in hardware so flexibility is lacking. Since time-to-market is
increasingly important, programmability becomes more and more important. Field
Programmable Gate Arrays (\textsc{FPGA}s) offer more design-time options and a
shorter development cycle by providing reconfigurability at logic gate level,
allowing developers to map out an application spatially. This low level of
abstraction leads to a high configuration cost, in both processor area and
development effort. For most signal-processing applications such as audio
processing or image manipulation, the operations that need to be performed fall
into a limited number of categories, and the configurability of an FPGA is
excessive.

\subsection{Coarse-Grained Reconfigurable Architectures}
A Coarse-Grained Reconfigurable Architecture (\textsc{CGRA}) features functional
blocks at a higher level of abstraction than a FPGA, while still allowing enough
flexibility to spatially layout an application in hardware. The coarser grained
units require fewer configuration bits, resulting in a lower energy consumption.
From a programmer's perspective, the CGRA can be viewed as an extension to Very
Long Instruction Word (\textsc{VLIW}) processors such as Quallcomm's Hexagon
architecture \cite{hexagon} and Single Instruction, Multiple Data
(\textsc{SIMD}) processing. Combining lower configuration overhead, higher
development abstraction, programmer familiarity with these kinds of processors
and the energy benefits of spatially mapping makes the CGRA a good target for accelerating

\subsection{Optimal instruction scheduling and register allocation}
\subsection{Optimal instruction scheduling and register allocation for CGRAs}