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BoyBaykiller/JitDumpGet.txt

Created July 14, 2025 21:47
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Tier0 and Tier1 jitdump of Get in https://github.com/dotnet/runtime/issues/117577
Raw
JitDumpGet.txt
****** START compiling Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float (MethodHash=2b4c0cab)
Generating code for Windows x64
OPTIONS: Tier-0 compilation (set DOTNET_TieredCompilation=0 to disable)
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000 03 ldarg.1
IL_0001 17 ldc.i4.1
IL_0002 30 04 bgt.s 4 (IL_0008)
IL_0004 03 ldarg.1
IL_0005 16 ldc.i4.0
IL_0006 2f 0b bge.s 11 (IL_0013)
IL_0008 72 01 00 00 70 ldstr 0x70000001
IL_000d 03 ldarg.1
IL_000e 28 01 00 00 2b call 0x2B000001
IL_0013 0f 00 ldarga.s 0x0
IL_0015 7c f8 01 00 04 ldflda 0x40001F8
IL_001a e0 conv.u
IL_001b 03 ldarg.1
IL_001c d3 conv.i
IL_001d 1a ldc.i4.4
IL_001e 5a mul
IL_001f 58 add
IL_0020 4e ldind.r4
IL_0021 2a ret
1 return registers for return type float
[00..04) reg mm0
Parameter V00 ABI info: [00..08) reg rcx (implicit by-ref)
Parameter V01 ABI info: [00..04) reg rdx
lvaGrabTemp returning 2 (V02 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
Local V02 should not be enregistered because: it is address exposed
; Initial local variable assignments
;
; V00 arg0 struct <Program.EntryPoint+Vector2, 12> <Program.EntryPoint+Vector2>
; V01 arg1 int
; V02 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
*************** In compInitDebuggingInfo() for Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 2
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 022h
1: 01h 01h V01 arg1 000h 022h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
Jump targets:
IL_0008
IL_0013
New Basic Block BB01 [0000] created.
BB01 [0000] [000..004)
New Basic Block BB02 [0001] created.
BB02 [0001] [004..008)
New Basic Block BB03 [0002] created.
BB03 [0002] [008..013)
New Basic Block BB04 [0003] created.
BB04 [0003] [013..022)
setting likelihood of BB01 -> BB03 to 0.5
setting likelihood of BB01 -> BB02 to 0.5
setting likelihood of BB02 -> BB04 to 0.5
setting likelihood of BB02 -> BB03 to 0.5
setting likelihood of BB03 -> BB04 to 1
CLFLG_MINOPT set for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
IL Code Size,Instr 34, 19, Basic Block count 4, Local Variable Num,Ref count 3, 5 for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
IL Code Size,Instr 34, 19, Basic Block count 4, Local Variable Num,Ref count 3, 5 for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
OPTIONS: opts.MinOpts() == true
Basic block list for 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond )
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond )
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always)
BB04 [0003] 2 BB02,BB03 1 [013..022) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
Trees after Pre-import
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond )
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond )
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always)
BB04 [0003] 2 BB02,BB03 1 [013..022) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Profile incorporation
not optimizing, so not incorporating any profile data
*************** Finishing PHASE Profile incorporation [no changes]
*************** Starting PHASE Canonicalize entry
*************** Finishing PHASE Canonicalize entry [no changes]
*************** Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 0 (0x000) ldarg.1
[ 1] 1 (0x001) ldc.i4.1 1
[ 2] 2 (0x002) bgt.s
STMT00000 ( 0x000[E-] ... ??? )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB03 (PC=008) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 8 (0x008) ldstr 70000001
[ 1] 13 (0x00d) ldarg.1
[ 2] 14 (0x00e) call 2B000001
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
STMT00001 ( 0x008[E-] ... ??? )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
impImportBlockPending for BB04
Importing BB04 (PC=019) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 19 (0x013) ldarga.s 0
[ 1] 21 (0x015) ldflda 040001F8
[ 1] 26 (0x01a) conv.u
[ 1] 27 (0x01b) ldarg.1
[ 2] 28 (0x01c) conv.i
[ 2] 29 (0x01d) ldc.i4.4 4
[ 3] 30 (0x01e) mul
[ 2] 31 (0x01f) add
[ 1] 32 (0x020) ldind.r4
[ 1] 33 (0x021) ret
STMT00002 ( 0x013[E-] ... ??? )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
Importing BB02 (PC=004) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 4 (0x004) ldarg.1
[ 1] 5 (0x005) ldc.i4.0 0
[ 2] 6 (0x006) bge.s
STMT00003 ( 0x004[E-] ... ??? )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
impImportBlockPending for BB03
impImportBlockPending for BB04
*************** Finishing PHASE Importation
Trees after Importation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import [no changes]
*************** Starting PHASE Save contexts around async calls
No async calls where execution context capture/restore is necessary
*************** Finishing PHASE Save contexts around async calls [no changes]
*************** Starting PHASE Morph - Init
*************** Finishing PHASE Morph - Init [no changes]
*************** Starting PHASE Morph - Inlining
*************** Finishing PHASE Morph - Inlining [no changes]
*************** Starting PHASE Allocate Objects
no newobjs or newarr in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks [no changes]
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty try/catch/fault
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try/catch/fault [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Morph - Promote Structs
promotion opt flag not enabled
*************** Finishing PHASE Morph - Promote Structs [no changes]
*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
LocalAddressVisitor visiting statement:
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
Local V00 should not be enregistered because: it is address exposed
LocalAddressVisitor modified statement:
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
*************** Finishing PHASE Morph - Structs/AddrExp
Trees after Morph - Structs/AddrExp
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Optimize mask conversions
Skipping. Optimizations Disabled
*************** Finishing PHASE Optimize mask conversions [no changes]
*************** Starting PHASE Early liveness
*************** Finishing PHASE Early liveness [no changes]
*************** Starting PHASE Forward Substitution
*************** Finishing PHASE Forward Substitution [no changes]
*************** Starting PHASE Physical promotion
*************** Finishing PHASE Physical promotion [no changes]
*************** Starting PHASE Identify candidates for implicit byref copy omission
*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]
*************** Starting PHASE Morph - ByRefs
Changing the lvType for struct parameter V00 to TYP_BYREF.
*************** Finishing PHASE Morph - ByRefs
Trees after Morph - ByRefs
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Morph - Global
compEnregLocals() is false, setting doNotEnreg flag for all locals.
Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V01 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V02 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Morphing BB01
fgMorphTree BB01, STMT00000 (before)
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
Morphing BB02
fgMorphTree BB02, STMT00003 (before)
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
Morphing BB03
fgMorphTree BB03, STMT00001 (before)
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
Adding final args and determining ABI info for [000006]:
Argument 0 ABI info: [00..08) reg rcx
Argument 1 ABI info: [00..04) reg rdx
Args for call [000006] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000004].CNS_STR ref (By value), 1 segments: <[00..08) reg rcx>]
CallArg[[000005].LCL_VAR int (By value), 1 segments: <[00..04) reg rdx>]
Morphing args for 6.CALL:
Sorting the arguments:
Deferred argument:
[000005] -----+----- * LCL_VAR int V01 arg1
Moved to late list
Deferred argument:
[000022] H----+----- * CNS_INT(h) ref 'You tried to access this vector at index: {0}'
Moved to late list
Register placement order: rdx rcx
Args for [000006].CALL after fgMorphArgs:
CallArg[[000022].CNS_INT ref (By value), 1 segments: <[00..08) reg rcx>, processed]
CallArg[[000005].LCL_VAR int (By value), 1 segments: <[00..04) reg rdx>, processed]
OutgoingArgsStackSize is 32
fgMorphTree BB03, STMT00001 (after)
[000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
[000022] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
Morphing BB04
fgMorphTree BB04, STMT00002 (before)
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
lvaGrabTemp returning 3 (V03 tmp1) called for Cast away GC.
Rewriting an implicit by-ref parameter reference:
[000008] ----------- * LCL_ADDR byref V00 arg0 [+0]
Transformed into:
[000008] ----------- * LCL_VAR byref V00 arg0
Folding long operator with constant nodes into a constant:
[000013] ----------- * CAST long <- int
[000012] -----+----- \--* CNS_INT int 4
Bashed to long constant:
[000013] ----------- * CNS_INT long 4
fgMorphTree BB04, STMT00002 (after)
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000026] -A---+----- +--* COMMA long
[000023] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000024] -----+----- | \--* LCL_VAR long V03 tmp1
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
[000022] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000026] -A---+----- +--* COMMA long
[000023] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000024] -----+----- | \--* LCL_VAR long V03 tmp1
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Post-Morph
*************** In fgMarkDemotedImplicitByRefArgs()
Clearing annotation for V00
*************** Finishing PHASE Post-Morph
Trees after Post-Morph
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
[000022] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000026] -A---+----- +--* COMMA long
[000023] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000024] -----+----- | \--* LCL_VAR long V03 tmp1
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie [no changes]
*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function
*************** Finishing PHASE Morph array ops [no changes]
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*************** Finishing PHASE Mark local vars [no changes]
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
Trees after Find oper order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
[000022] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000026] -A---+----- +--* COMMA long
[000023] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000024] -----+----- | \--* LCL_VAR long V03 tmp1
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 11 tree nodes
*************** Finishing PHASE Set block order
Trees after Set block order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
N004 (???,???) [000003] -----+----- * JTRUE void
N003 (???,???) [000002] J----+-N--- \--* GT int
N001 (???,???) [000000] -----+----- +--* LCL_VAR int V01 arg1
N002 (???,???) [000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
N004 (???,???) [000021] -----+----- * JTRUE void
N003 (???,???) [000020] J----+-N--- \--* GE int
N001 (???,???) [000018] -----+----- +--* LCL_VAR int V01 arg1
N002 (???,???) [000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
N001 (???,???) [000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
N002 (???,???) [000022] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
N011 (???,???) [000017] -A-XG+----- * RETURN float
N010 (???,???) [000016] -A-XG+----- \--* IND float
N009 (???,???) [000015] -A---+----- \--* ADD long
N004 (???,???) [000026] -A---+----- +--* COMMA long
N002 (???,???) [000023] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
N001 (???,???) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0
N003 (???,???) [000024] -----+----- | \--* LCL_VAR long V03 tmp1
N008 (???,???) [000014] -----+----- \--* LSH long
N006 (???,???) [000011] -----+----- +--* CAST long <- int
N005 (???,???) [000010] -----+----- | \--* LCL_VAR int V01 arg1
N007 (???,???) [000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Stress gtSplitTree
*************** Finishing PHASE Stress gtSplitTree [no changes]
*************** Starting PHASE Remove empty finally 3
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 3 [no changes]
*************** Starting PHASE Remove empty try 3
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 3 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 3
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 3 [no changes]
*************** Starting PHASE Create EH funclets
*************** Finishing PHASE Create EH funclets [no changes]
*************** Starting PHASE Expand casts
*************** Finishing PHASE Expand casts [no changes]
*************** Starting PHASE Expand runtime lookups
*************** Finishing PHASE Expand runtime lookups [no changes]
*************** Starting PHASE Expand static init
Nothing to expand.
*************** Finishing PHASE Expand static init [no changes]
*************** Starting PHASE Expand TLS access
Nothing to expand.
*************** Finishing PHASE Expand TLS access [no changes]
*************** Starting PHASE Expand stack array allocation
*************** Finishing PHASE Expand stack array allocation [no changes]
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Create throw helper blocks
*************** Finishing PHASE Create throw helper blocks [no changes]
*************** Starting PHASE Rationalize IR
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i LIR
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
[000027] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 (???,???) [000000] -----+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -----+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] J----+-N--- t2 = * GT int
/--* t2 int
N004 (???,???) [000003] -----+----- * JTRUE void
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
[000028] ----------- IL_OFFSET void INLRT @ 0x004[E-]
N001 (???,???) [000018] -----+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -----+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] J----+-N--- t20 = * GE int
/--* t20 int
N004 (???,???) [000021] -----+----- * JTRUE void
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
[000029] ----------- IL_OFFSET void INLRT @ 0x008[E-]
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
N002 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t5 int arg1 rdx
+--* t22 ref arg0 rcx
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
[000030] ----------- IL_OFFSET void INLRT @ 0x013[E-]
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000023] DA---+----- * STORE_LCL_VAR long V03 tmp1
N003 (???,???) [000024] -----+----- t24 = LCL_VAR long V03 tmp1
N005 (???,???) [000010] -----+----- t10 = LCL_VAR int V01 arg1
/--* t10 int
N006 (???,???) [000011] -----+----- t11 = * CAST long <- int
N007 (???,???) [000013] -----+----- t13 = CNS_INT long 2
/--* t11 long
+--* t13 long
N008 (???,???) [000014] -----+----- t14 = * LSH long
/--* t24 long
+--* t14 long
N009 (???,???) [000015] -A---+----- t15 = * ADD long
/--* t15 long
N010 (???,???) [000016] -A-XG+----- t16 = * IND float
/--* t16 float
N011 (???,???) [000017] -A-XG+----- * RETURN float
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Lowering nodeinfo
compEnregLocals() is false, setting doNotEnreg flag for all locals.
Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V01 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V02 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V03 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Lowering JTRUE:
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] J----+-N--- t2 = * GT int
/--* t2 int
N004 (???,???) [000003] -----+----- * JTRUE void
Lowering condition:
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] J----+-N--- t2 = * GT int
Lowering JTRUE Result:
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] -----+-N--- * CMP void
N004 (???,???) [000003] -----+----- JCC void cond=SGT
Lowering JTRUE:
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] J----+-N--- t20 = * GE int
/--* t20 int
N004 (???,???) [000021] -----+----- * JTRUE void
Lowering condition:
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] J----+-N--- t20 = * GE int
Lowering JTRUE Result:
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] -----+-N--- * CMP void
N004 (???,???) [000021] -----+----- JCC void cond=SGE
lowering call (before):
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
N002 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t5 int arg1 rdx
+--* t22 ref arg0 rcx
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
Args:
======
Late args:
======
Lowering arg:
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
Passed in [00..04) reg rdx
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
/--* t5 int
[000031] ----------- t31 = * PUTARG_REG int REG rdx
Lowering arg:
N002 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
Passed in [00..08) reg rcx
N002 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t22 ref
[000032] ----------- t32 = * PUTARG_REG ref REG rcx
results of lowering call:
N001 (???,???) [000033] H---------- t33 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t33 long
N002 (???,???) [000034] n---G------ t34 = * IND long
Bumping outgoing arg space size from 0 to 32 for [000006]
lowering call (after):
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
/--* t5 int
[000031] ----------- t31 = * PUTARG_REG int REG rdx
N002 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t22 ref
[000032] ----------- t32 = * PUTARG_REG ref REG rcx
N001 (???,???) [000033] Hc--------- t33 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t33 long
N002 (???,???) [000034] nc--G------ t34 = * IND long REG NA
/--* t31 int arg1 rdx
+--* t32 ref arg0 rcx
+--* t34 long control expr
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
lowering store lcl var/field (before):
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000023] DA---+----- * STORE_LCL_VAR long V03 tmp1
lowering store lcl var/field (after):
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000023] DA---+----- * STORE_LCL_VAR long V03 tmp1
Addressing mode:
Base
N003 (???,???) [000024] -c---+----- * LCL_VAR long V03 tmp1
+ Index * 4 + 0
N006 (???,???) [000011] -----+----- * CAST long <- int
Removing unused node:
N008 (???,???) [000014] -----+----- * LSH long
Removing unused node:
N007 (???,???) [000013] -c---+----- * CNS_INT long 2
New addressing mode node:
N009 (???,???) [000015] -----+----- * LEA(b+(i*4)+0) long
lowering return node
N011 (???,???) [000017] -A-XG+----- * RETURN float
============
Lower has completed modifying nodes.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i LIR
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
[000027] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] -----+-N--- * CMP void
N004 (???,???) [000003] -----+----- JCC void cond=SGT
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
[000028] ----------- IL_OFFSET void INLRT @ 0x004[E-]
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] -----+-N--- * CMP void
N004 (???,???) [000021] -----+----- JCC void cond=SGE
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
[000029] ----------- IL_OFFSET void INLRT @ 0x008[E-]
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
/--* t5 int
[000031] ----------- t31 = * PUTARG_REG int REG rdx
N002 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t22 ref
[000032] ----------- t32 = * PUTARG_REG ref REG rcx
N001 (???,???) [000033] Hc--------- t33 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t33 long
N002 (???,???) [000034] nc--G------ t34 = * IND long REG NA
/--* t31 int arg1 rdx
+--* t32 ref arg0 rcx
+--* t34 long control expr
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
[000030] ----------- IL_OFFSET void INLRT @ 0x013[E-]
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000023] DA---+----- * STORE_LCL_VAR long V03 tmp1
N003 (???,???) [000024] -----+----- t24 = LCL_VAR long V03 tmp1
N005 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1
/--* t10 int
N006 (???,???) [000011] -----+----- t11 = * CAST long <- int
/--* t24 long
+--* t11 long
N009 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long
/--* t15 long
N010 (???,???) [000016] -A-XG+----- t16 = * IND float
/--* t16 float
N011 (???,???) [000017] -A-XG+----- * RETURN float
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i LIR
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
[000027] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] -----+-N--- * CMP void
N004 (???,???) [000003] -----+----- JCC void cond=SGT
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
[000028] ----------- IL_OFFSET void INLRT @ 0x004[E-]
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] -----+-N--- * CMP void
N004 (???,???) [000021] -----+----- JCC void cond=SGE
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
[000029] ----------- IL_OFFSET void INLRT @ 0x008[E-]
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
/--* t5 int
[000031] ----------- t31 = * PUTARG_REG int REG rdx
N002 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t22 ref
[000032] ----------- t32 = * PUTARG_REG ref REG rcx
N001 (???,???) [000033] Hc--------- t33 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t33 long
N002 (???,???) [000034] nc--G------ t34 = * IND long REG NA
/--* t31 int arg1 rdx
+--* t32 ref arg0 rcx
+--* t34 long control expr
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
[000030] ----------- IL_OFFSET void INLRT @ 0x013[E-]
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000023] DA---+----- * STORE_LCL_VAR long V03 tmp1
N003 (???,???) [000024] -----+----- t24 = LCL_VAR long V03 tmp1
N005 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1
/--* t10 int
N006 (???,???) [000011] -----+----- t11 = * CAST long <- int
/--* t24 long
+--* t11 long
N009 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long
/--* t15 long
N010 (???,???) [000016] -A-XG+----- t16 = * IND float
/--* t16 float
N011 (???,???) [000017] -A-XG+----- * RETURN float
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01
use: {}
def: {}
in: {}
out: {}
BB02
use: {}
def: {}
in: {}
out: {}
BB03
use: {}
def: {}
in: {}
out: {}
BB04
use: {}
def: {}
in: {}
out: {}
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence:
Current block: BB01
Current block: BB02
Current block: BB03
Current block: BB04
Final LSRA Block Sequence:
BB01 ( 1 ) critical-out
BB02 ( 1 ) critical-out
BB03 ( 1 ) critical-in
BB04 ( 1 ) critical-in
BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. V01 MEM
N002. CNS_INT 1
N003. CMP
N004. JCC cond=SGT
BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
=====
N000. IL_OFFSET INLRT @ 0x004[E-]
N001. V01 MEM
N002. CNS_INT 0
N003. CMP
N004. JCC cond=SGE
BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
=====
N000. IL_OFFSET INLRT @ 0x008[E-]
N001. t5 = V01 MEM
N000. t31 = PUTARG_REG; t5
N002. t22 = CNS_INT(h) 'You tried to access this vector at index: {0}'
N000. t32 = PUTARG_REG; t22
N001. CNS_INT(h) 0x7ff7f13342a0 ftn
N002. IND
N003. CALL ; t31,t32
BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
=====
N000. IL_OFFSET INLRT @ 0x013[E-]
N001. t8 = V00 MEM
N002. V03 MEM; t8
N003. t24 = V03 MEM
N005. V01 MEM
N006. t11 = CAST
N009. t15 = LEA(b+(i*4)+0); t24,t11
N010. t16 = IND ; t15
N011. RETURN ; t16
buildIntervals second part ========
Arg V00 is live in reg rcx
Arg V01 is live in reg rdx
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N002 (???,???) [000027] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N004 (???,???) [000000] -c---+----- * LCL_VAR int V01 arg1 NA REG NA
Contained
DefList: { }
N006 (???,???) [000001] -c---+----- * CNS_INT int 1 REG NA
Contained
DefList: { }
N008 (???,???) [000002] -----+-N--- * CMP void REG NA
DefList: { }
N010 (???,???) [000003] -----+----- * JCC void cond=SGT REG NA
NEW BLOCK BB02
<RefPosition #1 @12 RefTypeBB BB02 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N014 (???,???) [000028] ----------- * IL_OFFSET void INLRT @ 0x004[E-] REG NA
DefList: { }
N016 (???,???) [000018] -c---+----- * LCL_VAR int V01 arg1 NA REG NA
Contained
DefList: { }
N018 (???,???) [000019] -c---+----- * CNS_INT int 0 REG NA
Contained
DefList: { }
N020 (???,???) [000020] -----+-N--- * CMP void REG NA
DefList: { }
N022 (???,???) [000021] -----+----- * JCC void cond=SGE REG NA
NEW BLOCK BB03
<RefPosition #2 @24 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N026 (???,???) [000029] ----------- * IL_OFFSET void INLRT @ 0x008[E-] REG NA
DefList: { }
N028 (???,???) [000005] -----+----- * LCL_VAR int V01 arg1 NA REG NA
Interval 0: int RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #3 @29 RefTypeDef <Ivl:0> LCL_VAR BB03 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N028.t5. LCL_VAR }
N030 (???,???) [000031] ----------- * PUTARG_REG int REG rdx
<RefPosition #4 @30 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #5 @30 RefTypeUse <Ivl:0> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
Interval 1: int RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #6 @31 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #7 @31 RefTypeDef <Ivl:1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00>
DefList: { N030.t31. PUTARG_REG }
N032 (???,???) [000022] H----+----- * CNS_INT(h) ref 'You tried to access this vector at index: {0}' REG NA
Interval 2: ref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #8 @33 RefTypeDef <Ivl:2> CNS_INT BB03 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N030.t31. PUTARG_REG; N032.t22. CNS_INT }
N034 (???,???) [000032] ----------- * PUTARG_REG ref REG rcx
<RefPosition #9 @34 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #10 @34 RefTypeUse <Ivl:2> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
Interval 3: ref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #11 @35 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #12 @35 RefTypeDef <Ivl:3> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00>
DefList: { N030.t31. PUTARG_REG; N034.t32. PUTARG_REG }
N036 (???,???) [000033] Hc--------- * CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
Contained
DefList: { N030.t31. PUTARG_REG; N034.t32. PUTARG_REG }
N038 (???,???) [000034] nc--G------ * IND long REG NA
Contained
DefList: { N030.t31. PUTARG_REG; N034.t32. PUTARG_REG }
N040 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA
<RefPosition #13 @40 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #14 @40 RefTypeUse <Ivl:1> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #15 @40 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #16 @40 RefTypeUse <Ivl:3> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #17 @41 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11] minReg=1>
NEW BLOCK BB04
<RefPosition #18 @42 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N044 (???,???) [000030] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA
DefList: { }
N046 (???,???) [000008] -----+----- * LCL_VAR byref V00 arg0 NA REG NA
Interval 4: byref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #19 @47 RefTypeDef <Ivl:4> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N046.t8. LCL_VAR }
N048 (???,???) [000023] DA---+----- * STORE_LCL_VAR long V03 tmp1 NA REG NA
<RefPosition #20 @48 RefTypeUse <Ivl:4> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
DefList: { }
N050 (???,???) [000024] -----+----- * LCL_VAR long V03 tmp1 NA REG NA
Interval 5: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #21 @51 RefTypeDef <Ivl:5> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N050.t24. LCL_VAR }
N052 (???,???) [000010] -c---+----- * LCL_VAR int V01 arg1 NA REG NA
Contained
DefList: { N050.t24. LCL_VAR }
N054 (???,???) [000011] -----+----- * CAST long <- int REG NA
Interval 6: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #22 @55 RefTypeDef <Ivl:6> CAST BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N050.t24. LCL_VAR; N054.t11. CAST }
N056 (???,???) [000015] -c---+----- * LEA(b+(i*4)+0) long REG NA
Contained
DefList: { N050.t24. LCL_VAR; N054.t11. CAST }
N058 (???,???) [000016] -A-XG+----- * IND float REG NA
<RefPosition #23 @58 RefTypeUse <Ivl:5> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #24 @58 RefTypeUse <Ivl:6> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
Interval 7: float RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[allMask]
<RefPosition #25 @59 RefTypeDef <Ivl:7> IND BB04 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N058.t16. IND }
N060 (???,???) [000017] -A-XG+----- * RETURN float REG NA
<RefPosition #26 @60 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #27 @60 RefTypeUse <Ivl:7> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: int RefPositions {#3@29 #5@30} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 1: int RefPositions {#7@31 #14@40} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 2: ref (constant) RefPositions {#8@33 #10@34} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 3: ref RefPositions {#12@35 #16@40} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 4: byref RefPositions {#19@47 #20@48} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 5: long RefPositions {#21@51 #23@58} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 6: long RefPositions {#22@55 #24@58} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 7: float RefPositions {#25@59 #27@60} physReg:NA Preferences=[mm0] Aversions=[allMask]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #1 @12 RefTypeBB BB02 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #2 @24 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #3 @29 RefTypeDef <Ivl:0> LCL_VAR BB03 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #4 @30 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #5 @30 RefTypeUse <Ivl:0> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #6 @31 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #7 @31 RefTypeDef <Ivl:1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00>
<RefPosition #8 @33 RefTypeDef <Ivl:2> CNS_INT BB03 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #9 @34 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #10 @34 RefTypeUse <Ivl:2> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #11 @35 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #12 @35 RefTypeDef <Ivl:3> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00>
<RefPosition #13 @40 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #14 @40 RefTypeUse <Ivl:1> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #15 @40 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #16 @40 RefTypeUse <Ivl:3> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #17 @41 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #18 @42 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #19 @47 RefTypeDef <Ivl:4> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #20 @48 RefTypeUse <Ivl:4> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #21 @51 RefTypeDef <Ivl:5> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #22 @55 RefTypeDef <Ivl:6> CAST BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #23 @58 RefTypeUse <Ivl:5> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #24 @58 RefTypeUse <Ivl:6> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #25 @59 RefTypeDef <Ivl:7> IND BB04 regmask=[mm0] minReg=1 wt=400.00>
<RefPosition #26 @60 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #27 @60 RefTypeUse <Ivl:7> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
=====
N002. IL_OFFSET INLRT @ 0x000[E-]
N004. V01 MEM
N006. CNS_INT 1
N008. CMP
N010. JCC cond=SGT
BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
=====
N014. IL_OFFSET INLRT @ 0x004[E-]
N016. V01 MEM
N018. CNS_INT 0
N020. CMP
N022. JCC cond=SGE
BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
=====
N026. IL_OFFSET INLRT @ 0x008[E-]
N028. V01 MEM
Def:<I0>(#3)
N030. PUTARG_REG
Use:<I0>(#5) Fixed:rdx(#4) *
Def:<I1>(#7) rdx
N032. CNS_INT(h) 'You tried to access this vector at index: {0}'
Def:<I2>(#8)
N034. PUTARG_REG
Use:<I2>(#10) Fixed:rcx(#9) *
Def:<I3>(#12) rcx
N036. CNS_INT(h) 0x7ff7f13342a0 ftn
N038. IND
N040. CALL
Use:<I1>(#14) Fixed:rdx(#13) *
Use:<I3>(#16) Fixed:rcx(#15) *
Kill: [rax rcx rdx r8-r11]
BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
=====
N044. IL_OFFSET INLRT @ 0x013[E-]
N046. V00 MEM
Def:<I4>(#19)
N048. V03 MEM
Use:<I4>(#20) *
N050. V03 MEM
Def:<I5>(#21)
N052. V01 MEM
N054. CAST
Def:<I6>(#22)
N056. LEA(b+(i*4)+0)
N058. IND
Use:<I5>(#23) *
Use:<I6>(#24) *
Def:<I7>(#25)
N060. RETURN
Use:<I7>(#27) Fixed:mm0(#26) *
Linear scan intervals after buildIntervals:
Interval 0: int RefPositions {#3@29 #5@30} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 1: int RefPositions {#7@31 #14@40} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 2: ref (constant) RefPositions {#8@33 #10@34} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 3: ref RefPositions {#12@35 #16@40} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 4: byref RefPositions {#19@47 #20@48} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 5: long RefPositions {#21@51 #23@58} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 6: long RefPositions {#22@55 #24@58} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 7: float RefPositions {#25@59 #27@60} physReg:NA Preferences=[mm0] Aversions=[allMask]
*************** In LinearScan::allocateRegistersMinimal()
Linear scan intervals before allocateRegistersMinimal:
Interval 0: int RefPositions {#3@29 #5@30} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 1: int RefPositions {#7@31 #14@40} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 2: ref (constant) RefPositions {#8@33 #10@34} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 3: ref RefPositions {#12@35 #16@40} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 4: byref RefPositions {#19@47 #20@48} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 5: long RefPositions {#21@51 #23@58} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 6: long RefPositions {#22@55 #24@58} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 7: float RefPositions {#25@59 #27@60} physReg:NA Preferences=[mm0] Aversions=[allMask]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #1 @12 RefTypeBB BB02 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #2 @24 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #3 @29 RefTypeDef <Ivl:0> LCL_VAR BB03 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #4 @30 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #5 @30 RefTypeUse <Ivl:0> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #6 @31 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #7 @31 RefTypeDef <Ivl:1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00>
<RefPosition #8 @33 RefTypeDef <Ivl:2> CNS_INT BB03 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #9 @34 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #10 @34 RefTypeUse <Ivl:2> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #11 @35 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #12 @35 RefTypeDef <Ivl:3> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00>
<RefPosition #13 @40 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #14 @40 RefTypeUse <Ivl:1> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #15 @40 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #16 @40 RefTypeUse <Ivl:3> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #17 @41 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #18 @42 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #19 @47 RefTypeDef <Ivl:4> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #20 @48 RefTypeUse <Ivl:4> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #21 @51 RefTypeDef <Ivl:5> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #22 @55 RefTypeDef <Ivl:6> CAST BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #23 @58 RefTypeUse <Ivl:5> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #24 @58 RefTypeUse <Ivl:6> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #25 @59 RefTypeDef <Ivl:7> IND BB04 regmask=[mm0] minReg=1 wt=400.00>
<RefPosition #26 @60 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #27 @60 RefTypeUse <Ivl:7> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| | | | | | | | | | | | | | |
0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
12.#1 BB2 PredBB0 | | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
24.#2 BB3 PredBB0 | | | | | | | | | | | | | | |
[000005] 29.#3 I0 Def Alloc rdx | | |I0 a| | | | | | | | | | | |
[000031] 30.#4 rdx Fixd Keep rdx | | |I0 a| | | | | | | | | | | |
30.#5 I0 Use * Keep rdx | | |I0 a| | | | | | | | | | | |
31.#6 rdx Fixd Keep rdx | | | | | | | | | | | | | | |
31.#7 I1 Def Alloc rdx | | |I1 a| | | | | | | | | | | |
[000022] 33.#8 C2 Def Alloc rcx | |C2 a|I1 a| | | | | | | | | | | |
[000032] 34.#9 rcx Fixd Keep rcx | |C2 a|I1 a| | | | | | | | | | | |
34.#10 C2 Use * Keep rcx | |C2 a|I1 a| | | | | | | | | | | |
35.#11 rcx Fixd Keep rcx | | |I1 a| | | | | | | | | | | |
35.#12 I3 Def Alloc rcx | |I3 a|I1 a| | | | | | | | | | | |
[000006] 40.#13 rdx Fixd Keep rdx | |I3 a|I1 a| | | | | | | | | | | |
40.#14 I1 Use * Keep rdx | |I3 a|I1 a| | | | | | | | | | | |
40.#15 rcx Fixd Keep rcx | |I3 a|I1 a| | | | | | | | | | | |
40.#16 I3 Use * Keep rcx | |I3 a|I1 a| | | | | | | | | | | |
41.#17 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
42.#18 BB4 PredBB0 | | | | | | | | | | | | | | |
[000008] 47.#19 I4 Def ORDER(A) rax |I4 a| | | | | | | | | | | | | |
[000023] 48.#20 I4 Use * Keep rax |I4 a| | | | | | | | | | | | | |
[000024] 51.#21 I5 Def ORDER(A) rax |I5 a| | | | | | | | | | | | | |
[000011] 55.#22 I6 Def ORDER(A) rcx |I5 a|I6 a| | | | | | | | | | | | |
[000016] 58.#23 I5 Use * Keep rax |I5 a|I6 a| | | | | | | | | | | | |
58.#24 I6 Use * Keep rcx |I5 a|I6 a| | | | | | | | | | | | |
59.#25 I7 Def Alloc mm0 | | | | | | | | | |I7 a| | | | |
[000017] 60.#26 mm0 Fixd Keep mm0 | | | | | | | | | |I7 a| | | | |
60.#27 I7 Use * Keep mm0 | | | | | | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #1 @12 RefTypeBB BB02 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #2 @24 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #3 @29 RefTypeDef <Ivl:0> LCL_VAR BB03 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #4 @30 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #5 @30 RefTypeUse <Ivl:0> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #6 @31 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #7 @31 RefTypeDef <Ivl:1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00>
<RefPosition #8 @33 RefTypeDef <Ivl:2> CNS_INT BB03 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #9 @34 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #10 @34 RefTypeUse <Ivl:2> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #11 @35 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #12 @35 RefTypeDef <Ivl:3> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00>
<RefPosition #13 @40 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #14 @40 RefTypeUse <Ivl:1> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #15 @40 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #16 @40 RefTypeUse <Ivl:3> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #17 @41 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #18 @42 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #19 @47 RefTypeDef <Ivl:4> LCL_VAR BB04 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #20 @48 RefTypeUse <Ivl:4> BB04 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #21 @51 RefTypeDef <Ivl:5> LCL_VAR BB04 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #22 @55 RefTypeDef <Ivl:6> CAST BB04 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #23 @58 RefTypeUse <Ivl:5> BB04 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #24 @58 RefTypeUse <Ivl:6> BB04 regmask=[rcx] minReg=1 last wt=100.00>
<RefPosition #25 @59 RefTypeDef <Ivl:7> IND BB04 regmask=[mm0] minReg=1 wt=400.00>
<RefPosition #26 @60 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #27 @60 RefTypeUse <Ivl:7> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
Active intervals at end of allocation:
Trees after linear scan register allocator (LSRA)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i LIR
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
N002 (???,???) [000027] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N004 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1 NA REG NA
N006 (???,???) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
N008 (???,???) [000002] -----+-N--- * CMP void REG NA
N010 (???,???) [000003] -----+----- JCC void cond=SGT REG NA
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
N014 (???,???) [000028] ----------- IL_OFFSET void INLRT @ 0x004[E-] REG NA
N016 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1 NA REG NA
N018 (???,???) [000019] -c---+----- t19 = CNS_INT int 0 REG NA
/--* t18 int
+--* t19 int
N020 (???,???) [000020] -----+-N--- * CMP void REG NA
N022 (???,???) [000021] -----+----- JCC void cond=SGE REG NA
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
N026 (???,???) [000029] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
N028 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1 rdx REG rdx
/--* t5 int
N030 (???,???) [000031] ----------- t31 = * PUTARG_REG int REG rdx
N032 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}' REG rcx
/--* t22 ref
N034 (???,???) [000032] ----------- t32 = * PUTARG_REG ref REG rcx
N036 (???,???) [000033] Hc--------- t33 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t33 long
N038 (???,???) [000034] nc--G------ t34 = * IND long REG NA
/--* t31 int arg1 rdx
+--* t32 ref arg0 rcx
+--* t34 long control expr
N040 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
N044 (???,???) [000030] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
N046 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 rax REG rax
/--* t8 byref
N048 (???,???) [000023] DA---+----- * STORE_LCL_VAR long V03 tmp1 NA REG NA
N050 (???,???) [000024] -----+----- t24 = LCL_VAR long V03 tmp1 rax REG rax
N052 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1 NA REG NA
/--* t10 int
N054 (???,???) [000011] -----+----- t11 = * CAST long <- int REG rcx
/--* t24 long
+--* t11 long
N056 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
N058 (???,???) [000016] -A-XG+----- t16 = * IND float REG mm0
/--* t16 float
N060 (???,???) [000017] -A-XG+----- * RETURN float REG NA
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
12.#1 BB2 PredBB0 | | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
24.#2 BB3 PredBB0 | | | | | | | | | | | | | | |
[000005] 29.#3 I0 Def Alloc rdx | | |I0 a| | | | | | | | | | | |
[000031] 30.#4 rdx Fixd Keep rdx | | |I0 a| | | | | | | | | | | |
30.#5 I0 Use * Keep rdx | | |I0 i| | | | | | | | | | | |
31.#6 rdx Fixd Keep rdx | | | | | | | | | | | | | | |
31.#7 I1 Def Alloc rdx | | |I1 a| | | | | | | | | | | |
[000022] 33.#8 C2 Def Alloc rcx | |C2 a|I1 a| | | | | | | | | | | |
[000032] 34.#9 rcx Fixd Keep rcx | |C2 a|I1 a| | | | | | | | | | | |
34.#10 C2 Use * Keep rcx | |C2 i|I1 a| | | | | | | | | | | |
35.#11 rcx Fixd Keep rcx | | |I1 a| | | | | | | | | | | |
35.#12 I3 Def Alloc rcx | |I3 a|I1 a| | | | | | | | | | | |
[000006] 40.#13 rdx Fixd Keep rdx | |I3 a|I1 a| | | | | | | | | | | |
40.#14 I1 Use * Keep rdx | |I3 a|I1 i| | | | | | | | | | | |
40.#15 rcx Fixd Keep rcx | |I3 a| | | | | | | | | | | | |
40.#16 I3 Use * Keep rcx | |I3 i| | | | | | | | | | | | |
41.#17 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
42.#18 BB4 PredBB0 | | | | | | | | | | | | | | |
[000008] 47.#19 I4 Def Alloc rax |I4 a| | | | | | | | | | | | | |
[000023] 48.#20 I4 Use * Keep rax |I4 i| | | | | | | | | | | | | |
[000024] 51.#21 I5 Def Alloc rax |I5 a| | | | | | | | | | | | | |
[000011] 55.#22 I6 Def Alloc rcx |I5 a|I6 a| | | | | | | | | | | | |
[000016] 58.#23 I5 Use * Keep rax |I5 i|I6 a| | | | | | | | | | | | |
58.#24 I6 Use * Keep rcx | |I6 i| | | | | | | | | | | | |
59.#25 I7 Def Alloc mm0 | | | | | | | | | |I7 a| | | | |
[000017] 60.#26 mm0 Fixd Keep mm0 | | | | | | | | | |I7 a| | | | |
60.#27 I7 Use * Keep mm0 | | | | | | | | | |I7 i| | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars: 0
Total Reg Cand Vars: 0
Total number of Intervals: 7
Total number of RefPositions: 27
Total Number of spill temps created: 0
..........
BB04 [ 100.00]: REG_ORDER = 3
..........
Total SpillCount : 0 Weighted: 0.000000
Total CopyReg : 0 Weighted: 0.000000
Total ResolutionMovs : 0 Weighted: 0.000000
Total SplitEdges : 0 Weighted: 0.000000
..........
Total REG_ORDER [#13] : 3 Weighted: 300.000000
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
=====
N002. IL_OFFSET INLRT @ 0x000[E-]
N004. V01 MEM
N006. CNS_INT 1
N008. CMP
N010. JCC cond=SGT
BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
=====
N014. IL_OFFSET INLRT @ 0x004[E-]
N016. V01 MEM
N018. CNS_INT 0
N020. CMP
N022. JCC cond=SGE
BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
=====
N026. IL_OFFSET INLRT @ 0x008[E-]
N028. rdx = V01 MEM
N030. rdx = PUTARG_REG; rdx
N032. rcx = CNS_INT(h) 'You tried to access this vector at index: {0}'
N034. rcx = PUTARG_REG; rcx
N036. CNS_INT(h) 0x7ff7f13342a0 ftn
N038. IND
N040. CALL ; rdx,rcx
BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
=====
N044. IL_OFFSET INLRT @ 0x013[E-]
N046. rax = V00 MEM
N048. V03 MEM; rax
N050. rax = V03 MEM
N052. V01 MEM
N054. rcx = CAST
N056. STK = LEA(b+(i*4)+0); rax,rcx
N058. mm0 = IND ; STK
N060. RETURN ; mm0
*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i LIR
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
N002 (???,???) [000027] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N004 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1 NA REG NA
N006 (???,???) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
N008 (???,???) [000002] -----+-N--- * CMP void REG NA
N010 (???,???) [000003] -----+----- JCC void cond=SGT REG NA
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
N014 (???,???) [000028] ----------- IL_OFFSET void INLRT @ 0x004[E-] REG NA
N016 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1 NA REG NA
N018 (???,???) [000019] -c---+----- t19 = CNS_INT int 0 REG NA
/--* t18 int
+--* t19 int
N020 (???,???) [000020] -----+-N--- * CMP void REG NA
N022 (???,???) [000021] -----+----- JCC void cond=SGE REG NA
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
N026 (???,???) [000029] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
N028 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1 rdx REG rdx
/--* t5 int
N030 (???,???) [000031] ----------- t31 = * PUTARG_REG int REG rdx
N032 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}' REG rcx
/--* t22 ref
N034 (???,???) [000032] ----------- t32 = * PUTARG_REG ref REG rcx
N036 (???,???) [000033] Hc--------- t33 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t33 long
N038 (???,???) [000034] nc--G------ t34 = * IND long REG NA
/--* t31 int arg1 rdx
+--* t32 ref arg0 rcx
+--* t34 long control expr
N040 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
N044 (???,???) [000030] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
N046 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 rax REG rax
/--* t8 byref
N048 (???,???) [000023] DA---+----- * STORE_LCL_VAR long V03 tmp1 NA REG NA
N050 (???,???) [000024] -----+----- t24 = LCL_VAR long V03 tmp1 rax REG rax
N052 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1 NA REG NA
/--* t10 int
N054 (???,???) [000011] -----+----- t11 = * CAST long <- int REG rcx
/--* t24 long
+--* t11 long
N056 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
N058 (???,???) [000016] -A-XG+----- t16 = * IND float REG mm0
/--* t16 float
N060 (???,???) [000017] -A-XG+----- * RETURN float REG NA
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Place 'align' instructions
*************** In placeLoopAlignInstructions()
Not aligning loops; ShouldAlignLoops is false
*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i LIR
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [rax rcx rdx r8-r11 mm0]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Set V00 to offset 0
Set V01 to offset 8
Assign V03 tmp1, size=8, stkOffs=-0x18
Assign V02 OutArgs, size=32, stkOffs=-0x38
--- delta bump 8 for RA
--- delta bump 8 for FP
--- delta bump 0 for FP frame
--- virtual stack offset to actual stack offset delta is 16
-- V00 was 0, now 16
-- V01 was 8, now 24
-- V02 was -56, now -40
-- V03 was -24, now -8
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) byref -> [rbp+0x10] do-not-enreg[] ld-addr-op
; V01 arg1 [V01 ] ( 1, 1 ) int -> [rbp+0x18] do-not-enreg[]
; V02 OutArgs [V02 ] ( 1, 1 ) struct (32) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <UNNAMED>
; V03 tmp1 [V03 ] ( 1, 1 ) long -> [rbp-0x08] do-not-enreg[] "Cast away GC"
;
; Lcl frame size = 48
Created:
G_M62292_IG02: ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
BB01 : first block
BB03 : branch target
BB04 : branch target
*************** After genMarkLabelsForCodegen()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR label
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i LIR
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i LIR label hascall gcsafe
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i LIR label
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
=============== Generating BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} flags=0x00000000.00001011: i LIR label
BB01 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB01:
Label: G_M62292_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB01, IL range [000..004)
Scope info: opening scope, LVnum=0 [000..022)
Debug: New V00 debug range: first
Scope info: opening scope, LVnum=1 [000..022)
Debug: New V01 debug range: first
Added IP mapping: 0x0000 STACK_EMPTY (G_M62292_IG02,ins#0,ofs#0) label
Generating: N002 (???,???) [000027] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N004 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1 NA REG NA
Generating: N006 (???,???) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
Generating: N008 (???,???) [000002] -----+-N--- * CMP void REG NA
Mapped BB01 to G_M62292_IG02
IN0001: cmp dword ptr [V01 rbp+0x18], 1
Generating: N010 (???,???) [000003] -----+----- JCC void cond=SGT REG NA
IN0002: jg L_M62292_BB03
Variable Live Range History Dump for BB01
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
=============== Generating BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.00000011: i LIR
BB02 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB02:
Scope info: begin block BB02, IL range [004..008)
Added IP mapping: 0x0004 STACK_EMPTY (G_M62292_IG02,ins#2,ofs#10) label
Generating: N014 (???,???) [000028] ----------- IL_OFFSET void INLRT @ 0x004[E-] REG NA
Generating: N016 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1 NA REG NA
Generating: N018 (???,???) [000019] -c---+----- t19 = CNS_INT int 0 REG NA
/--* t18 int
+--* t19 int
Generating: N020 (???,???) [000020] -----+-N--- * CMP void REG NA
Mapped BB02 to G_M62292_IG02
IN0003: cmp dword ptr [V01 rbp+0x18], 0
Generating: N022 (???,???) [000021] -----+----- JCC void cond=SGE REG NA
IN0004: jge L_M62292_BB04
Variable Live Range History Dump for BB02
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
=============== Generating BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04} flags=0x00000000.02011011: i LIR label hascall gcsafe
BB03 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB03:
Saved:
G_M62292_IG02: ; offs=0x000000, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref
Created:
G_M62292_IG03: ; offs=0x000014, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Label: G_M62292_IG03, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB03, IL range [008..013)
Added IP mapping: 0x0008 STACK_EMPTY (G_M62292_IG03,ins#0,ofs#0) label
Generating: N026 (???,???) [000029] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
Generating: N028 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1 rdx REG rdx
Mapped BB03 to G_M62292_IG03
IN0005: mov edx, dword ptr [V01 rbp+0x18]
/--* t5 int
Generating: N030 (???,???) [000031] ----------- t31 = * PUTARG_REG int REG rdx
Generating: N032 (???,???) [000022] H----+----- t22 = CNS_INT(h) ref 'You tried to access this vector at index: {0}' REG rcx
IN0006: mov rcx, 0x230618FF1E8 ; 'You tried to access this vector at index: {0}'
GC regs: 0000 {} => 0002 {rcx}
/--* t22 ref
Generating: N034 (???,???) [000032] ----------- t32 = * PUTARG_REG ref REG rcx
GC regs: 0002 {rcx} => 0000 {}
GC regs: 0000 {} => 0002 {rcx}
Generating: N036 (???,???) [000033] Hc--------- t33 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t33 long
Generating: N038 (???,???) [000034] nc--G------ t34 = * IND long REG NA
/--* t31 int arg1 rdx
+--* t32 ref arg0 rcx
+--* t34 long control expr
Generating: N040 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA
GC regs: 0002 {rcx} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0007: call [Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)]
Variable Live Range History Dump for BB03
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
=============== Generating BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={} flags=0x00000000.00001011: i LIR label
BB04 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB04:
Saved:
G_M62292_IG03: ; offs=0x000014, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
Created:
G_M62292_IG04: ; offs=0x000027, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Label: G_M62292_IG04, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB04, IL range [013..022)
Added IP mapping: 0x0013 STACK_EMPTY (G_M62292_IG04,ins#0,ofs#0) label
Generating: N044 (???,???) [000030] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
Generating: N046 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 rax REG rax
Mapped BB04 to G_M62292_IG04
IN0008: mov rax, bword ptr [V00 rbp+0x10]
Byref regs: 0000 {} => 0001 {rax}
/--* t8 byref
Generating: N048 (???,???) [000023] DA---+----- * STORE_LCL_VAR long V03 tmp1 NA REG NA
Byref regs: 0001 {rax} => 0000 {}
IN0009: mov qword ptr [V03 rbp-0x08], rax
Generating: N050 (???,???) [000024] -----+----- t24 = LCL_VAR long V03 tmp1 rax REG rax
IN000a: mov rax, qword ptr [V03 rbp-0x08]
Generating: N052 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1 NA REG NA
/--* t10 int
Generating: N054 (???,???) [000011] -----+----- t11 = * CAST long <- int REG rcx
IN000b: movsxd rcx, dword ptr [V01 rbp+0x18]
/--* t24 long
+--* t11 long
Generating: N056 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
Generating: N058 (???,???) [000016] -A-XG+----- t16 = * IND float REG mm0
IN000c: vmovss xmm0, dword ptr [rax+4*rcx]
/--* t16 float
Generating: N060 (???,???) [000017] -A-XG+----- * RETURN float REG NA
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Added IP mapping: EPILOG (G_M62292_IG04,ins#5,ofs#21) label
Reserving epilog IG for block BB04
Saved:
G_M62292_IG04: ; offs=0x000027, size=0x0015, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
Created:
G_M62292_IG05: ; offs=0x00003C, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
*************** After placeholder IG creation
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62292_IG02: ; offs=0x000000, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref
G_M62292_IG03: ; offs=0x000014, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
G_M62292_IG04: ; offs=0x000027, size=0x0015, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
G_M62292_IG05: ; epilog placeholder, next placeholder=<END>, BB04 [0003], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
Variable Live Range History Dump for BB04
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), (G_M62292_IG04,ins#5,ofs#21)]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), (G_M62292_IG04,ins#5,ofs#21)]
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = -572662307, compSizeEstimate = -572662307 Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) byref -> [rbp+0x10] do-not-enreg[] ld-addr-op
; V01 arg1 [V01 ] ( 1, 1 ) int -> [rbp+0x18] do-not-enreg[]
; V02 OutArgs [V02 ] ( 1, 1 ) struct (32) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <UNNAMED>
; V03 tmp1 [V03 ] ( 1, 1 ) long -> [rbp-0x08] do-not-enreg[] "Cast away GC"
;
; Lcl frame size = 48
*************** Before prolog / epilog generation
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62292_IG02: ; offs=0x000000, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref
G_M62292_IG03: ; offs=0x000014, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
G_M62292_IG04: ; offs=0x000027, size=0x0015, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
G_M62292_IG05: ; epilog placeholder, next placeholder=<END>, BB04 [0003], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M62292_IG01,ins#0,ofs#0) label
__prolog:
Debug: New V00 debug range: first
Debug: New V01 debug range: first
IN000d: push rbp
IN000e: sub rsp, 48
IN000f: lea rbp, [rsp+0x30]
*************** In genHomeRegisterParams()
IN0010: mov bword ptr [V00 rbp+0x10], rcx
IN0011: mov dword ptr [V01 rbp+0x18], edx
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Saved:
G_M62292_IG01: ; offs=0x000000, size=0x0011, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
IN0012: add rsp, 48
IN0013: pop rbp
IN0014: ret
Saved:
G_M62292_IG05: ; offs=0x00003C, size=0x0006, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0011, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M62292_IG02: ; offs=0x000011, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref
G_M62292_IG03: ; offs=0x000025, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
G_M62292_IG04: ; offs=0x000038, size=0x0015, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
G_M62292_IG05: ; offs=0x00004D, size=0x0006, bbWeight=1, epilog, nogc, extend
*************** In emitJumpDistBind()
Emitter Jump List:
IG02 IN0002 jg[6] -> IG03
IG02 IN0004 jge[6] -> IG04
total jump count: 2
Binding: IN0002: 000000 jg L_M62292_BB03
Binding L_M62292_BB03 to G_M62292_IG03
Estimate of fwd jump [61857F44/002]: 0015 -> 0025 = 000E
Shrinking jump [61857F44/002]
Binding: IN0004: 000000 jge L_M62292_BB04
Binding L_M62292_BB04 to G_M62292_IG04
Estimate of fwd jump [61857F94/004]: 001B -> 0034 = 0017
Shrinking jump [61857F94/004]
Adjusted offset of BB03 from 0025 to 001D
Adjusted offset of BB04 from 0038 to 0030
Adjusted offset of BB05 from 004D to 0045
Total shrinkage = 8, min extra jump size = 4294967295
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x4B bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x8)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M62292_IG01: ; offs=0x000000, size=0x0011, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN000d: 000000 push rbp
IN000e: 000001 sub rsp, 48
IN000f: 000005 lea rbp, [rsp+0x30]
IN0010: 00000A mov bword ptr [rbp+0x10], rcx
IN0011: 00000E mov dword ptr [rbp+0x18], edx
;; size=17 bbWeight=1 PerfScore 3.75
G_M62292_IG02: ; offs=0x000011, size=0x000C, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref, isz
IN0001: 000011 cmp dword ptr [rbp+0x18], 1
IN0002: 000015 jg SHORT G_M62292_IG03
IN0003: 000017 cmp dword ptr [rbp+0x18], 0
IN0004: 00001B jge SHORT G_M62292_IG04
;; size=12 bbWeight=1 PerfScore 6.00
G_M62292_IG03: ; offs=0x00001D, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
IN0005: 00001D mov edx, dword ptr [rbp+0x18]
IN0006: 000020 mov rcx, 0x230618FF1E8 ; 'You tried to access this vector at index: {0}'
; gcrRegs +[rcx]
recordRelocation: 00007FF7F08C91AC (rw: 0000023061837634) => 00007FF7F13342A0, type 16 (IMAGE_REL_BASED_DISP32), delta 0
; Call at 002A [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0007: 00002A call [Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)]
; gcrRegs -[rcx]
;; size=19 bbWeight=1 PerfScore 4.25
G_M62292_IG04: ; offs=0x000030, size=0x0015, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
IN0008: 000030 mov rax, bword ptr [rbp+0x10]
; byrRegs +[rax]
IN0009: 000034 mov qword ptr [rbp-0x08], rax
IN000a: 000038 mov rax, qword ptr [rbp-0x08]
; byrRegs -[rax]
IN000b: 00003C movsxd rcx, dword ptr [rbp+0x18]
IN000c: 000040 vmovss xmm0, dword ptr [rax+4*rcx]
;; size=21 bbWeight=1 PerfScore 10.00
G_M62292_IG05: ; offs=0x000045, size=0x0006, bbWeight=1, epilog, nogc, extend
IN0012: 000045 add rsp, 48
IN0013: 000049 pop rbp
IN0014: 00004A ret
;; size=6 bbWeight=1 PerfScore 1.75
Allocated method code size = 75 , actual size = 75, unused size = 0
; Total bytes of code 75, prolog size 10, PerfScore 25.75, instruction count 20, allocated bytes for code 75 (MethodHash=2b4c0cab) for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float (Tier0)
; ============================================================
*************** After end code gen, before unwindEmit()
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0011, bbWeight=1, PerfScore 3.75, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN000d: 000000 push rbp
IN000e: 000001 sub rsp, 48
IN000f: 000005 lea rbp, [rsp+0x30]
IN0010: 00000A mov bword ptr [V00 rbp+0x10], rcx
IN0011: 00000E mov dword ptr [V01 rbp+0x18], edx
G_M62292_IG02: ; offs=0x000011, size=0x000C, bbWeight=1, PerfScore 6.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref, isz
IN0001: 000011 cmp dword ptr [V01 rbp+0x18], 1
IN0002: 000015 jg SHORT G_M62292_IG03
IN0003: 000017 cmp dword ptr [V01 rbp+0x18], 0
IN0004: 00001B jge SHORT G_M62292_IG04
G_M62292_IG03: ; offs=0x00001D, size=0x0013, bbWeight=1, PerfScore 4.25, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
IN0005: 00001D mov edx, dword ptr [V01 rbp+0x18]
IN0006: 000020 mov rcx, 0x230618FF1E8 ; 'You tried to access this vector at index: {0}'
IN0007: 00002A call [Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)]
G_M62292_IG04: ; offs=0x000030, size=0x0015, bbWeight=1, PerfScore 10.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
IN0008: 000030 mov rax, bword ptr [V00 rbp+0x10]
IN0009: 000034 mov qword ptr [V03 rbp-0x08], rax
IN000a: 000038 mov rax, qword ptr [V03 rbp-0x08]
IN000b: 00003C movsxd rcx, dword ptr [V01 rbp+0x18]
IN000c: 000040 vmovss xmm0, dword ptr [rax+4*rcx]
G_M62292_IG05: ; offs=0x000045, size=0x0006, bbWeight=1, PerfScore 1.75, epilog, nogc, extend
IN0012: 000045 add rsp, 48
IN0013: 000049 pop rbp
IN0014: 00004A ret
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x00004b (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x05
CountOfUnwindCodes: 2
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 5 * 8 + 8 = 48 = 0x30
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x00007FF7F08C9180, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x4b, unwindSize=0x8, pUnwindBlock=0x0000023061851308, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 6
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000011 ( STACK_EMPTY )
IL offs 0x0004 : 0x00000017 ( STACK_EMPTY )
IL offs 0x0008 : 0x0000001D ( STACK_EMPTY )
IL offs 0x0013 : 0x00000030 ( STACK_EMPTY )
IL offs EPILOG : 0x00000045 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 4
; Variable debug info: 4 live ranges, 2 vars for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
(V00 arg0) : From 00000000h to 00000011h, in rcx
(V00 arg0) : From 00000011h to 00000045h, in rbp[16] (1 slot)
(V01 arg1) : From 00000000h to 00000011h, in rdx
(V01 arg1) : From 00000011h to 00000045h, in rbp[24] (1 slot)
*************** In gcInfoBlockHdrSave()
Set code length to 75.
Set stack base register to rbp.
Set Outgoing stack arg area size to 32.
Stack slot id for offset 16 (0x10) (frame) (byref, untracked) = 0.
Defining 0 call sites:
*************** Finishing PHASE Emit GC+EH tables
Method code size: 75
Allocations for Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float (MethodHash=2b4c0cab)
count: 479, size: 53152, max = 7576
allocateMemory: 65536, nraUsed: 57264
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
ABI | 0 | 0.00%
AssertionProp | 0 | 0.00%
ASTNode | 5216 | 9.81%
InstDesc | 3816 | 7.18%
ImpStack | 384 | 0.72%
BasicBlock | 1720 | 3.24%
CallArgs | 160 | 0.30%
FlowEdge | 200 | 0.38%
DepthFirstSearch | 56 | 0.11%
Loops | 0 | 0.00%
TreeStatementList | 0 | 0.00%
SiScope | 0 | 0.00%
DominatorMemory | 0 | 0.00%
LSRA | 9400 | 17.69%
LSRA_Interval | 768 | 1.44%
LSRA_RefPosition | 2240 | 4.21%
Reachability | 0 | 0.00%
SSA | 0 | 0.00%
ValueNumber | 0 | 0.00%
LvaTable | 1584 | 2.98%
UnwindInfo | 0 | 0.00%
hashBv | 128 | 0.24%
bitset | 32 | 0.06%
FixedBitVect | 24 | 0.05%
Generic | 968 | 1.82%
LocalAddressVisitor | 0 | 0.00%
FieldSeqStore | 0 | 0.00%
MemorySsaMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 0 | 0.00%
GC | 1300 | 2.45%
CorTailCallInfo | 0 | 0.00%
Inlining | 272 | 0.51%
ArrayStack | 0 | 0.00%
DebugInfo | 368 | 0.69%
DebugOnly | 20738 | 39.02%
Codegen | 2720 | 5.12%
LoopOpt | 0 | 0.00%
LoopClone | 0 | 0.00%
LoopUnroll | 0 | 0.00%
LoopHoist | 0 | 0.00%
LoopIVOpts | 0 | 0.00%
Unknown | 90 | 0.17%
RangeCheck | 0 | 0.00%
CopyProp | 0 | 0.00%
Promotion | 120 | 0.23%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 648 | 1.22%
ClassLayout | 200 | 0.38%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 0 | 0.00%
Pgo | 0 | 0.00%
MaskConversionOpt | 0 | 0.00%
TryRegionClone | 0 | 0.00%
Async | 0 | 0.00%
RangeCheckCloning | 0 | 0.00%
Final metrics:
ActualCodeBytes : 75
AllocatedHotCodeBytes : 75
AllocatedColdCodeBytes : 0
ReadOnlyDataBytes : 0
GCInfoBytes : 4
EHClauseCount : 0
PhysicallyPromotedFields : 0
LoopsFoundDuringOpts : 0
LoopsInverted : 0
LoopsCloned : 0
LoopsUnrolled : 0
LoopAlignmentCandidates : 0
LoopsAligned : 0
LoopsIVWidened : 0
WidenedIVs : 0
UnusedIVsRemoved : 0
LoopsMadeDownwardsCounted : 0
LoopsStrengthReduced : 0
VarsInSsa : 0
HoistedExpressions : 0
RedundantBranchesEliminated : 0
JumpThreadingsPerformed : 0
CseCount : 0
BasicBlocksAtCodegen : 4
PerfScore : 25.750000
BytesAllocated : 57264
ImporterBranchFold : 0
ImporterSwitchFold : 0
DevirtualizedCall : 0
DevirtualizedCallUnboxedEntry : 0
DevirtualizedCallRemovedBox : 0
GDV : 0
ClassGDV : 0
MethodGDV : 0
MultiGuessGDV : 0
ChainedGDV : 0
EnumeratorGDV : 0
InlinerBranchFold : 0
InlineAttempt : 0
InlineCount : 0
ProfileConsistentBeforeInline : 0
ProfileConsistentAfterInline : 0
ProfileConsistentBeforeMorph : 0
ProfileConsistentAfterMorph : 0
ProfileSynthesizedBlendedOrRepaired : 0
ProfileInconsistentInitially : 0
ProfileInconsistentResetLeave : 0
ProfileInconsistentImporterBranchFold : 0
ProfileInconsistentImporterSwitchFold : 0
ProfileInconsistentChainedGDV : 0
ProfileInconsistentScratchBB : 0
ProfileInconsistentInlinerBranchFold : 0
ProfileInconsistentInlineeScale : 0
ProfileInconsistentInlinee : 0
ProfileInconsistentNoReturnInlinee : 0
ProfileInconsistentMayThrowInlinee : 0
NewRefClassHelperCalls : 0
StackAllocatedRefClasses : 0
NewBoxedValueClassHelperCalls : 0
StackAllocatedBoxedValueClasses : 0
NewArrayHelperCalls : 0
StackAllocatedArrays : 0
LocalAssertionCount : 0
LocalAssertionOverflow : 0
MorphTrackedLocals : 0
MorphLocals : 0
EnumeratorGDVProvisionalNoEscape : 0
EnumeratorGDVCanCloneToEnsureNoEscape : 0
****** DONE compiling Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
****** START compiling Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float (MethodHash=2b4c0cab)
Generating code for Windows x64
OPTIONS: Tier-0 compilation (set DOTNET_TieredCompilation=0 to disable)
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000 03 ldarg.1
IL_0001 17 ldc.i4.1
IL_0002 30 04 bgt.s 4 (IL_0008)
IL_0004 03 ldarg.1
IL_0005 16 ldc.i4.0
IL_0006 2f 0b bge.s 11 (IL_0013)
IL_0008 72 01 00 00 70 ldstr 0x70000001
IL_000d 03 ldarg.1
IL_000e 28 01 00 00 2b call 0x2B000001
IL_0013 0f 00 ldarga.s 0x0
IL_0015 7c f8 01 00 04 ldflda 0x40001F8
IL_001a e0 conv.u
IL_001b 03 ldarg.1
IL_001c d3 conv.i
IL_001d 1a ldc.i4.4
IL_001e 5a mul
IL_001f 58 add
IL_0020 4e ldind.r4
IL_0021 2a ret
1 return registers for return type float
[00..04) reg mm0
Parameter V00 ABI info: [00..08) reg rcx (implicit by-ref)
Parameter V01 ABI info: [00..04) reg rdx
lvaGrabTemp returning 2 (V02 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
Local V02 should not be enregistered because: it is address exposed
; Initial local variable assignments
;
; V00 arg0 struct <Program.EntryPoint+Vector2, 12> <Program.EntryPoint+Vector2>
; V01 arg1 int
; V02 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
*************** In compInitDebuggingInfo() for Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 2
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 022h
1: 01h 01h V01 arg1 000h 022h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
Jump targets:
IL_0008
IL_0013
New Basic Block BB01 [0000] created.
BB01 [0000] [000..004)
New Basic Block BB02 [0001] created.
BB02 [0001] [004..008)
New Basic Block BB03 [0002] created.
BB03 [0002] [008..013)
New Basic Block BB04 [0003] created.
BB04 [0003] [013..022)
setting likelihood of BB01 -> BB03 to 0.5
setting likelihood of BB01 -> BB02 to 0.5
setting likelihood of BB02 -> BB04 to 0.5
setting likelihood of BB02 -> BB03 to 0.5
setting likelihood of BB03 -> BB04 to 1
CLFLG_MINOPT set for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
IL Code Size,Instr 34, 19, Basic Block count 4, Local Variable Num,Ref count 3, 5 for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
IL Code Size,Instr 34, 19, Basic Block count 4, Local Variable Num,Ref count 3, 5 for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
OPTIONS: opts.MinOpts() == true
Basic block list for 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond )
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond )
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always)
BB04 [0003] 2 BB02,BB03 1 [013..022) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
Trees after Pre-import
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond )
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond )
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always)
BB04 [0003] 2 BB02,BB03 1 [013..022) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Profile instrumentation prep
Using edge profiling
EfficientEdgeCountInstrumentor: preparing for instrumentation
[0] New probe for BB04 -> BB01 [source]
[1] New probe for BB02 -> BB04 [edge]
[2] New probe for BB02 -> BB03 [edge]
4 blocks, 3 probes (2 on critical edges)
*************** Finishing PHASE Profile instrumentation prep [no changes]
*************** Starting PHASE Profile incorporation
not optimizing, so not incorporating any profile data
*************** Finishing PHASE Profile incorporation [no changes]
*************** Starting PHASE Canonicalize entry
*************** Finishing PHASE Canonicalize entry [no changes]
*************** Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 0 (0x000) ldarg.1
[ 1] 1 (0x001) ldc.i4.1 1
[ 2] 2 (0x002) bgt.s
STMT00000 ( 0x000[E-] ... ??? )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB03 (PC=008) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 8 (0x008) ldstr 70000001
[ 1] 13 (0x00d) ldarg.1
[ 2] 14 (0x00e) call 2B000001
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
STMT00001 ( 0x008[E-] ... ??? )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
impImportBlockPending for BB04
Importing BB04 (PC=019) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 19 (0x013) ldarga.s 0
[ 1] 21 (0x015) ldflda 040001F8
[ 1] 26 (0x01a) conv.u
[ 1] 27 (0x01b) ldarg.1
[ 2] 28 (0x01c) conv.i
[ 2] 29 (0x01d) ldc.i4.4 4
[ 3] 30 (0x01e) mul
[ 2] 31 (0x01f) add
[ 1] 32 (0x020) ldind.r4
[ 1] 33 (0x021) ret
STMT00002 ( 0x013[E-] ... ??? )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
Importing BB02 (PC=004) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 4 (0x004) ldarg.1
[ 1] 5 (0x005) ldc.i4.0 0
[ 2] 6 (0x006) bge.s
STMT00003 ( 0x004[E-] ... ??? )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
impImportBlockPending for BB03
impImportBlockPending for BB04
*************** Finishing PHASE Importation
Trees after Importation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond ) i
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always) i
BB04 [0003] 2 BB02,BB03 1 [013..022) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Profile instrumentation
EfficientEdgeCountInstrumentor: splitting up to 2 critical edges
New Basic Block BB05 [0004] created.
Splitting edge from BB02 to BB03; adding BB05
setting likelihood of BB05 -> BB03 to 1
New relocated probe for BB02 -> BB03 [reloc to BB05 ]
fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB02, jumpBlk=BB00, runRarely=false)
fgNewBBinRegion(jumpKind=BBJ_ALWAYS, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB04
New Basic Block BB06 [0005] created.
Splitting edge from BB02 to BB04; adding BB06
setting likelihood of BB06 -> BB04 to 1
New relocated probe for BB02 -> BB04 [reloc to BB06 ]
Instrumenting method: 3 count probes, 0 class probes and 0 value probes
Instrumentation data base address is 00007FF7F15423B0
Using scalable probes
Using scalable probes
Using scalable probes
Using scalable probes
Using scalable probes
Using scalable probes
*************** Finishing PHASE Profile instrumentation
Trees after Profile instrumentation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i internal
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
***** BB05 [0004]
STMT00004 ( ??? ... ??? )
[000023] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000022] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c0 bbc
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
***** BB04 [0003]
STMT00005 ( ??? ... ??? )
[000025] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000024] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c4 bbc
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
***** BB06 [0005]
STMT00006 ( ??? ... ??? )
[000027] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000026] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c8 bbc
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import [no changes]
*************** Starting PHASE Save contexts around async calls
No async calls where execution context capture/restore is necessary
*************** Finishing PHASE Save contexts around async calls [no changes]
*************** Starting PHASE Morph - Init
*************** Finishing PHASE Morph - Init [no changes]
*************** Starting PHASE Morph - Inlining
*************** Finishing PHASE Morph - Inlining [no changes]
*************** Starting PHASE Allocate Objects
no newobjs or newarr in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i internal
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks [no changes]
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty try/catch/fault
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try/catch/fault [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Morph - Promote Structs
promotion opt flag not enabled
*************** Finishing PHASE Morph - Promote Structs [no changes]
*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00004 ( ??? ... ??? )
[000023] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000022] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c0 bbc
LocalAddressVisitor visiting statement:
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
LocalAddressVisitor visiting statement:
STMT00005 ( ??? ... ??? )
[000025] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000024] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c4 bbc
LocalAddressVisitor visiting statement:
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
Local V00 should not be enregistered because: it is address exposed
LocalAddressVisitor modified statement:
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
LocalAddressVisitor visiting statement:
STMT00006 ( ??? ... ??? )
[000027] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000026] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c8 bbc
*************** Finishing PHASE Morph - Structs/AddrExp
Trees after Morph - Structs/AddrExp
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i internal
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
***** BB05 [0004]
STMT00004 ( ??? ... ??? )
[000023] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000022] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c0 bbc
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
***** BB04 [0003]
STMT00005 ( ??? ... ??? )
[000025] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000024] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c4 bbc
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
***** BB06 [0005]
STMT00006 ( ??? ... ??? )
[000027] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000026] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c8 bbc
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Optimize mask conversions
Skipping. Optimizations Disabled
*************** Finishing PHASE Optimize mask conversions [no changes]
*************** Starting PHASE Early liveness
*************** Finishing PHASE Early liveness [no changes]
*************** Starting PHASE Forward Substitution
*************** Finishing PHASE Forward Substitution [no changes]
*************** Starting PHASE Physical promotion
*************** Finishing PHASE Physical promotion [no changes]
*************** Starting PHASE Identify candidates for implicit byref copy omission
*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]
*************** Starting PHASE Morph - ByRefs
Changing the lvType for struct parameter V00 to TYP_BYREF.
*************** Finishing PHASE Morph - ByRefs
Trees after Morph - ByRefs
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i internal
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
***** BB05 [0004]
STMT00004 ( ??? ... ??? )
[000023] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000022] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c0 bbc
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
***** BB04 [0003]
STMT00005 ( ??? ... ??? )
[000025] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000024] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c4 bbc
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
***** BB06 [0005]
STMT00006 ( ??? ... ??? )
[000027] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000026] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c8 bbc
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Morph - Global
compEnregLocals() is false, setting doNotEnreg flag for all locals.
Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V01 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V02 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Morphing BB01
fgMorphTree BB01, STMT00000 (before)
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
Morphing BB02
fgMorphTree BB02, STMT00003 (before)
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
Morphing BB05
fgMorphTree BB05, STMT00004 (before)
[000023] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000022] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c0 bbc
Adding final args and determining ABI info for [000023]:
Argument 0 ABI info: [00..08) reg rcx
Args for call [000023] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000022].CNS_INT long (By value), 1 segments: <[00..08) reg rcx>]
Morphing args for 23.CALL:
Sorting the arguments:
Deferred argument:
[000022] H----+----- * CNS_INT(h) long 0x7ff7f15423c0 bbc
Moved to late list
Register placement order: rcx
Args for [000023].CALL after fgMorphArgs:
CallArg[[000022].CNS_INT long (By value), 1 segments: <[00..08) reg rcx>, processed]
OutgoingArgsStackSize is 32
Morphing BB03
fgMorphTree BB03, STMT00001 (before)
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
Adding final args and determining ABI info for [000006]:
Argument 0 ABI info: [00..08) reg rcx
Argument 1 ABI info: [00..04) reg rdx
Args for call [000006] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000004].CNS_STR ref (By value), 1 segments: <[00..08) reg rcx>]
CallArg[[000005].LCL_VAR int (By value), 1 segments: <[00..04) reg rdx>]
Morphing args for 6.CALL:
Sorting the arguments:
Deferred argument:
[000005] -----+----- * LCL_VAR int V01 arg1
Moved to late list
Deferred argument:
[000028] H----+----- * CNS_INT(h) ref 'You tried to access this vector at index: {0}'
Moved to late list
Register placement order: rdx rcx
Args for [000006].CALL after fgMorphArgs:
CallArg[[000028].CNS_INT ref (By value), 1 segments: <[00..08) reg rcx>, processed]
CallArg[[000005].LCL_VAR int (By value), 1 segments: <[00..04) reg rdx>, processed]
OutgoingArgsStackSize is 32
fgMorphTree BB03, STMT00001 (after)
[000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
[000028] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
Morphing BB04
fgMorphTree BB04, STMT00005 (before)
[000025] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000024] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c4 bbc
Adding final args and determining ABI info for [000025]:
Argument 0 ABI info: [00..08) reg rcx
Args for call [000025] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000024].CNS_INT long (By value), 1 segments: <[00..08) reg rcx>]
Morphing args for 25.CALL:
Sorting the arguments:
Deferred argument:
[000024] H----+----- * CNS_INT(h) long 0x7ff7f15423c4 bbc
Moved to late list
Register placement order: rcx
Args for [000025].CALL after fgMorphArgs:
CallArg[[000024].CNS_INT long (By value), 1 segments: <[00..08) reg rcx>, processed]
OutgoingArgsStackSize is 32
fgMorphTree BB04, STMT00002 (before)
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CAST long <- int
[000012] ----------- \--* CNS_INT int 4
lvaGrabTemp returning 3 (V03 tmp1) called for Cast away GC.
Rewriting an implicit by-ref parameter reference:
[000008] ----------- * LCL_ADDR byref V00 arg0 [+0]
Transformed into:
[000008] ----------- * LCL_VAR byref V00 arg0
Folding long operator with constant nodes into a constant:
[000013] ----------- * CAST long <- int
[000012] -----+----- \--* CNS_INT int 4
Bashed to long constant:
[000013] ----------- * CNS_INT long 4
fgMorphTree BB04, STMT00002 (after)
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000032] -A---+----- +--* COMMA long
[000029] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000030] -----+----- | \--* LCL_VAR long V03 tmp1
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
Morphing BB06
fgMorphTree BB06, STMT00006 (before)
[000027] --CXG------ * CALL help int CORINFO_HELP_COUNTPROFILE32
[000026] H---------- arg0 \--* CNS_INT(h) long 0x7ff7f15423c8 bbc
Adding final args and determining ABI info for [000027]:
Argument 0 ABI info: [00..08) reg rcx
Args for call [000027] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000026].CNS_INT long (By value), 1 segments: <[00..08) reg rcx>]
Morphing args for 27.CALL:
Sorting the arguments:
Deferred argument:
[000026] H----+----- * CNS_INT(h) long 0x7ff7f15423c8 bbc
Moved to late list
Register placement order: rcx
Args for [000027].CALL after fgMorphArgs:
CallArg[[000026].CNS_INT long (By value), 1 segments: <[00..08) reg rcx>, processed]
OutgoingArgsStackSize is 32
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
***** BB05 [0004]
STMT00004 ( ??? ... ??? )
[000023] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
[000022] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c0 bbc
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
[000028] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
***** BB04 [0003]
STMT00005 ( ??? ... ??? )
[000025] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
[000024] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c4 bbc
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000032] -A---+----- +--* COMMA long
[000029] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000030] -----+----- | \--* LCL_VAR long V03 tmp1
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
***** BB06 [0005]
STMT00006 ( ??? ... ??? )
[000027] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
[000026] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c8 bbc
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Post-Morph
*************** In fgMarkDemotedImplicitByRefArgs()
Clearing annotation for V00
*************** Finishing PHASE Post-Morph
Trees after Post-Morph
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
***** BB05 [0004]
STMT00004 ( ??? ... ??? )
[000023] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
[000022] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c0 bbc
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
[000028] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
***** BB04 [0003]
STMT00005 ( ??? ... ??? )
[000025] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
[000024] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c4 bbc
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000032] -A---+----- +--* COMMA long
[000029] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000030] -----+----- | \--* LCL_VAR long V03 tmp1
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
***** BB06 [0005]
STMT00006 ( ??? ... ??? )
[000027] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
[000026] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c8 bbc
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie [no changes]
*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function
*************** Finishing PHASE Morph array ops [no changes]
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*************** Finishing PHASE Mark local vars [no changes]
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
Trees after Find oper order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
***** BB05 [0004]
STMT00004 ( ??? ... ??? )
[000023] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
[000022] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c0 bbc
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
[000028] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
***** BB04 [0003]
STMT00005 ( ??? ... ??? )
[000025] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
[000024] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c4 bbc
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000032] -A---+----- +--* COMMA long
[000029] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000030] -----+----- | \--* LCL_VAR long V03 tmp1
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
***** BB06 [0005]
STMT00006 ( ??? ... ??? )
[000027] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
[000026] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c8 bbc
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 11 tree nodes
*************** Finishing PHASE Set block order
Trees after Set block order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
N004 (???,???) [000003] -----+----- * JTRUE void
N003 (???,???) [000002] J----+-N--- \--* GT int
N001 (???,???) [000000] -----+----- +--* LCL_VAR int V01 arg1
N002 (???,???) [000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
N004 (???,???) [000021] -----+----- * JTRUE void
N003 (???,???) [000020] J----+-N--- \--* GE int
N001 (???,???) [000018] -----+----- +--* LCL_VAR int V01 arg1
N002 (???,???) [000019] -----+----- \--* CNS_INT int 0
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
***** BB05 [0004]
STMT00004 ( ??? ... ??? )
N002 (???,???) [000023] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
N001 (???,???) [000022] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c0 bbc
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
N001 (???,???) [000005] -----+----- arg1 rdx +--* LCL_VAR int V01 arg1
N002 (???,???) [000028] H----+----- arg0 rcx \--* CNS_INT(h) ref 'You tried to access this vector at index: {0}'
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
***** BB04 [0003]
STMT00005 ( ??? ... ??? )
N002 (???,???) [000025] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
N001 (???,???) [000024] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c4 bbc
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
N011 (???,???) [000017] -A-XG+----- * RETURN float
N010 (???,???) [000016] -A-XG+----- \--* IND float
N009 (???,???) [000015] -A---+----- \--* ADD long
N004 (???,???) [000032] -A---+----- +--* COMMA long
N002 (???,???) [000029] DA---+----- | +--* STORE_LCL_VAR long V03 tmp1
N001 (???,???) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0
N003 (???,???) [000030] -----+----- | \--* LCL_VAR long V03 tmp1
N008 (???,???) [000014] -----+----- \--* LSH long
N006 (???,???) [000011] -----+----- +--* CAST long <- int
N005 (???,???) [000010] -----+----- | \--* LCL_VAR int V01 arg1
N007 (???,???) [000013] -----+----- \--* CNS_INT long 2
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
***** BB06 [0005]
STMT00006 ( ??? ... ??? )
N002 (???,???) [000027] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32
N001 (???,???) [000026] H----+----- arg0 rcx \--* CNS_INT(h) long 0x7ff7f15423c8 bbc
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Stress gtSplitTree
*************** Finishing PHASE Stress gtSplitTree [no changes]
*************** Starting PHASE Remove empty finally 3
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 3 [no changes]
*************** Starting PHASE Remove empty try 3
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 3 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 3
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 3 [no changes]
*************** Starting PHASE Create EH funclets
*************** Finishing PHASE Create EH funclets [no changes]
*************** Starting PHASE Expand casts
*************** Finishing PHASE Expand casts [no changes]
*************** Starting PHASE Expand runtime lookups
*************** Finishing PHASE Expand runtime lookups [no changes]
*************** Starting PHASE Expand static init
Nothing to expand.
*************** Finishing PHASE Expand static init [no changes]
*************** Starting PHASE Expand TLS access
Nothing to expand.
*************** Finishing PHASE Expand TLS access [no changes]
*************** Starting PHASE Expand stack array allocation
*************** Finishing PHASE Expand stack array allocation [no changes]
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Create throw helper blocks
*************** Finishing PHASE Create throw helper blocks [no changes]
*************** Starting PHASE Rationalize IR
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i LIR
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i LIR internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i LIR hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i LIR internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
[000033] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 (???,???) [000000] -----+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -----+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] J----+-N--- t2 = * GT int
/--* t2 int
N004 (???,???) [000003] -----+----- * JTRUE void
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
[000034] ----------- IL_OFFSET void INLRT @ 0x004[E-]
N001 (???,???) [000018] -----+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -----+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] J----+-N--- t20 = * GE int
/--* t20 int
N004 (???,???) [000021] -----+----- * JTRUE void
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
N001 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc
/--* t22 long arg0 rcx
N002 (???,???) [000023] --CXG+----- u23 = * CALL help int CORINFO_HELP_COUNTPROFILE32
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
[000035] ----------- IL_OFFSET void INLRT @ 0x008[E-]
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
N002 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t5 int arg1 rdx
+--* t28 ref arg0 rcx
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
N001 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc
/--* t24 long arg0 rcx
N002 (???,???) [000025] --CXG+----- u25 = * CALL help int CORINFO_HELP_COUNTPROFILE32
[000036] ----------- IL_OFFSET void INLRT @ 0x013[E-]
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000029] DA---+----- * STORE_LCL_VAR long V03 tmp1
N003 (???,???) [000030] -----+----- t30 = LCL_VAR long V03 tmp1
N005 (???,???) [000010] -----+----- t10 = LCL_VAR int V01 arg1
/--* t10 int
N006 (???,???) [000011] -----+----- t11 = * CAST long <- int
N007 (???,???) [000013] -----+----- t13 = CNS_INT long 2
/--* t11 long
+--* t13 long
N008 (???,???) [000014] -----+----- t14 = * LSH long
/--* t30 long
+--* t14 long
N009 (???,???) [000015] -A---+----- t15 = * ADD long
/--* t15 long
N010 (???,???) [000016] -A-XG+----- t16 = * IND float
/--* t16 float
N011 (???,???) [000017] -A-XG+----- * RETURN float
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
N001 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc
/--* t26 long arg0 rcx
N002 (???,???) [000027] --CXG+----- u27 = * CALL help int CORINFO_HELP_COUNTPROFILE32
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Lowering nodeinfo
compEnregLocals() is false, setting doNotEnreg flag for all locals.
Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V01 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V02 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Local V03 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
Lowering JTRUE:
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] J----+-N--- t2 = * GT int
/--* t2 int
N004 (???,???) [000003] -----+----- * JTRUE void
Lowering condition:
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] J----+-N--- t2 = * GT int
Lowering JTRUE Result:
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] -----+-N--- * CMP void
N004 (???,???) [000003] -----+----- JCC void cond=SGT
Lowering JTRUE:
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] J----+-N--- t20 = * GE int
/--* t20 int
N004 (???,???) [000021] -----+----- * JTRUE void
Lowering condition:
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] J----+-N--- t20 = * GE int
Lowering JTRUE Result:
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] -----+-N--- * CMP void
N004 (???,???) [000021] -----+----- JCC void cond=SGE
lowering call (before):
N001 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc
/--* t22 long arg0 rcx
N002 (???,???) [000023] --CXG+----- u23 = * CALL help int CORINFO_HELP_COUNTPROFILE32
Args:
======
Late args:
======
Lowering arg:
N001 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc
Passed in [00..08) reg rcx
N001 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc
/--* t22 long
[000037] ----------- t37 = * PUTARG_REG long REG rcx
Bumping outgoing arg space size from 0 to 32 for [000023]
lowering call (after):
N001 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc
/--* t22 long
[000037] ----------- t37 = * PUTARG_REG long REG rcx
/--* t37 long arg0 rcx
N002 (???,???) [000023] --CXG+----- u23 = * CALL help int CORINFO_HELP_COUNTPROFILE32
lowering call (before):
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
N002 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t5 int arg1 rdx
+--* t28 ref arg0 rcx
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
Args:
======
Late args:
======
Lowering arg:
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
Passed in [00..04) reg rdx
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
/--* t5 int
[000038] ----------- t38 = * PUTARG_REG int REG rdx
Lowering arg:
N002 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
Passed in [00..08) reg rcx
N002 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t28 ref
[000039] ----------- t39 = * PUTARG_REG ref REG rcx
results of lowering call:
N001 (???,???) [000040] H---------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t40 long
N002 (???,???) [000041] n---G------ t41 = * IND long
lowering call (after):
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
/--* t5 int
[000038] ----------- t38 = * PUTARG_REG int REG rdx
N002 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t28 ref
[000039] ----------- t39 = * PUTARG_REG ref REG rcx
N001 (???,???) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t40 long
N002 (???,???) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 int arg1 rdx
+--* t39 ref arg0 rcx
+--* t41 long control expr
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
lowering call (before):
N001 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc
/--* t24 long arg0 rcx
N002 (???,???) [000025] --CXG+----- u25 = * CALL help int CORINFO_HELP_COUNTPROFILE32
Args:
======
Late args:
======
Lowering arg:
N001 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc
Passed in [00..08) reg rcx
N001 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc
/--* t24 long
[000042] ----------- t42 = * PUTARG_REG long REG rcx
lowering call (after):
N001 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc
/--* t24 long
[000042] ----------- t42 = * PUTARG_REG long REG rcx
/--* t42 long arg0 rcx
N002 (???,???) [000025] --CXG+----- u25 = * CALL help int CORINFO_HELP_COUNTPROFILE32
lowering store lcl var/field (before):
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000029] DA---+----- * STORE_LCL_VAR long V03 tmp1
lowering store lcl var/field (after):
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000029] DA---+----- * STORE_LCL_VAR long V03 tmp1
Addressing mode:
Base
N003 (???,???) [000030] -c---+----- * LCL_VAR long V03 tmp1
+ Index * 4 + 0
N006 (???,???) [000011] -----+----- * CAST long <- int
Removing unused node:
N008 (???,???) [000014] -----+----- * LSH long
Removing unused node:
N007 (???,???) [000013] -c---+----- * CNS_INT long 2
New addressing mode node:
N009 (???,???) [000015] -----+----- * LEA(b+(i*4)+0) long
lowering return node
N011 (???,???) [000017] -A-XG+----- * RETURN float
============
lowering call (before):
N001 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc
/--* t26 long arg0 rcx
N002 (???,???) [000027] --CXG+----- u27 = * CALL help int CORINFO_HELP_COUNTPROFILE32
Args:
======
Late args:
======
Lowering arg:
N001 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc
Passed in [00..08) reg rcx
N001 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc
/--* t26 long
[000043] ----------- t43 = * PUTARG_REG long REG rcx
lowering call (after):
N001 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc
/--* t26 long
[000043] ----------- t43 = * PUTARG_REG long REG rcx
/--* t43 long arg0 rcx
N002 (???,???) [000027] --CXG+----- u27 = * CALL help int CORINFO_HELP_COUNTPROFILE32
Lower has completed modifying nodes.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i LIR
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i LIR internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i LIR hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i LIR internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
[000033] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] -----+-N--- * CMP void
N004 (???,???) [000003] -----+----- JCC void cond=SGT
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
[000034] ----------- IL_OFFSET void INLRT @ 0x004[E-]
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] -----+-N--- * CMP void
N004 (???,???) [000021] -----+----- JCC void cond=SGE
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
N001 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc
/--* t22 long
[000037] ----------- t37 = * PUTARG_REG long REG rcx
/--* t37 long arg0 rcx
N002 (???,???) [000023] --CXG+----- u23 = * CALL help int CORINFO_HELP_COUNTPROFILE32
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
[000035] ----------- IL_OFFSET void INLRT @ 0x008[E-]
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
/--* t5 int
[000038] ----------- t38 = * PUTARG_REG int REG rdx
N002 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t28 ref
[000039] ----------- t39 = * PUTARG_REG ref REG rcx
N001 (???,???) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t40 long
N002 (???,???) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 int arg1 rdx
+--* t39 ref arg0 rcx
+--* t41 long control expr
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
N001 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc
/--* t24 long
[000042] ----------- t42 = * PUTARG_REG long REG rcx
/--* t42 long arg0 rcx
N002 (???,???) [000025] --CXG+----- u25 = * CALL help int CORINFO_HELP_COUNTPROFILE32
[000036] ----------- IL_OFFSET void INLRT @ 0x013[E-]
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000029] DA---+----- * STORE_LCL_VAR long V03 tmp1
N003 (???,???) [000030] -----+----- t30 = LCL_VAR long V03 tmp1
N005 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1
/--* t10 int
N006 (???,???) [000011] -----+----- t11 = * CAST long <- int
/--* t30 long
+--* t11 long
N009 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long
/--* t15 long
N010 (???,???) [000016] -A-XG+----- t16 = * IND float
/--* t16 float
N011 (???,???) [000017] -A-XG+----- * RETURN float
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
N001 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc
/--* t26 long
[000043] ----------- t43 = * PUTARG_REG long REG rcx
/--* t43 long arg0 rcx
N002 (???,???) [000027] --CXG+----- u27 = * CALL help int CORINFO_HELP_COUNTPROFILE32
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i LIR
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i LIR internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i LIR hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i LIR internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
[000033] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1
N002 (???,???) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 (???,???) [000002] -----+-N--- * CMP void
N004 (???,???) [000003] -----+----- JCC void cond=SGT
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
[000034] ----------- IL_OFFSET void INLRT @ 0x004[E-]
N001 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1
N002 (???,???) [000019] -c---+----- t19 = CNS_INT int 0
/--* t18 int
+--* t19 int
N003 (???,???) [000020] -----+-N--- * CMP void
N004 (???,???) [000021] -----+----- JCC void cond=SGE
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
N001 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc
/--* t22 long
[000037] ----------- t37 = * PUTARG_REG long REG rcx
/--* t37 long arg0 rcx
N002 (???,???) [000023] --CXG+----- u23 = * CALL help int CORINFO_HELP_COUNTPROFILE32
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
[000035] ----------- IL_OFFSET void INLRT @ 0x008[E-]
N001 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1
/--* t5 int
[000038] ----------- t38 = * PUTARG_REG int REG rdx
N002 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}'
/--* t28 ref
[000039] ----------- t39 = * PUTARG_REG ref REG rcx
N001 (???,???) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t40 long
N002 (???,???) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 int arg1 rdx
+--* t39 ref arg0 rcx
+--* t41 long control expr
N003 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
N001 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc
/--* t24 long
[000042] ----------- t42 = * PUTARG_REG long REG rcx
/--* t42 long arg0 rcx
N002 (???,???) [000025] --CXG+----- u25 = * CALL help int CORINFO_HELP_COUNTPROFILE32
[000036] ----------- IL_OFFSET void INLRT @ 0x013[E-]
N001 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0
/--* t8 byref
N002 (???,???) [000029] DA---+----- * STORE_LCL_VAR long V03 tmp1
N003 (???,???) [000030] -----+----- t30 = LCL_VAR long V03 tmp1
N005 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1
/--* t10 int
N006 (???,???) [000011] -----+----- t11 = * CAST long <- int
/--* t30 long
+--* t11 long
N009 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long
/--* t15 long
N010 (???,???) [000016] -A-XG+----- t16 = * IND float
/--* t16 float
N011 (???,???) [000017] -A-XG+----- * RETURN float
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
N001 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc
/--* t26 long
[000043] ----------- t43 = * PUTARG_REG long REG rcx
/--* t43 long arg0 rcx
N002 (???,???) [000027] --CXG+----- u27 = * CALL help int CORINFO_HELP_COUNTPROFILE32
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01
use: {}
def: {}
in: {}
out: {}
BB02
use: {}
def: {}
in: {}
out: {}
BB05
use: {}
def: {}
in: {}
out: {}
BB03
use: {}
def: {}
in: {}
out: {}
BB04
use: {}
def: {}
in: {}
out: {}
BB06
use: {}
def: {}
in: {}
out: {}
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence:
Current block: BB01
Current block: BB02
Current block: BB05
Current block: BB03
Current block: BB04
Current block: BB06
Final LSRA Block Sequence:
BB01 ( 1 ) critical-out
BB02 ( 1 )
BB05 ( 0.50)
BB03 ( 1 ) critical-in
BB04 ( 1 )
BB06 ( 0.50)
BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. V01 MEM
N002. CNS_INT 1
N003. CMP
N004. JCC cond=SGT
BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
=====
N000. IL_OFFSET INLRT @ 0x004[E-]
N001. V01 MEM
N002. CNS_INT 0
N003. CMP
N004. JCC cond=SGE
BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
=====
N001. t22 = CNS_INT(h) 0x7ff7f15423c0 bbc
N000. t37 = PUTARG_REG; t22
N002. CALL help; t37
BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
=====
N000. IL_OFFSET INLRT @ 0x008[E-]
N001. t5 = V01 MEM
N000. t38 = PUTARG_REG; t5
N002. t28 = CNS_INT(h) 'You tried to access this vector at index: {0}'
N000. t39 = PUTARG_REG; t28
N001. CNS_INT(h) 0x7ff7f13342a0 ftn
N002. IND
N003. CALL ; t38,t39
BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
=====
N001. t24 = CNS_INT(h) 0x7ff7f15423c4 bbc
N000. t42 = PUTARG_REG; t24
N002. CALL help; t42
N000. IL_OFFSET INLRT @ 0x013[E-]
N001. t8 = V00 MEM
N002. V03 MEM; t8
N003. t30 = V03 MEM
N005. V01 MEM
N006. t11 = CAST
N009. t15 = LEA(b+(i*4)+0); t30,t11
N010. t16 = IND ; t15
N011. RETURN ; t16
BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
=====
N001. t26 = CNS_INT(h) 0x7ff7f15423c8 bbc
N000. t43 = PUTARG_REG; t26
N002. CALL help; t43
buildIntervals second part ========
Arg V00 is live in reg rcx
Arg V01 is live in reg rdx
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N002 (???,???) [000033] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N004 (???,???) [000000] -c---+----- * LCL_VAR int V01 arg1 NA REG NA
Contained
DefList: { }
N006 (???,???) [000001] -c---+----- * CNS_INT int 1 REG NA
Contained
DefList: { }
N008 (???,???) [000002] -----+-N--- * CMP void REG NA
DefList: { }
N010 (???,???) [000003] -----+----- * JCC void cond=SGT REG NA
NEW BLOCK BB02
<RefPosition #1 @12 RefTypeBB BB02 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N014 (???,???) [000034] ----------- * IL_OFFSET void INLRT @ 0x004[E-] REG NA
DefList: { }
N016 (???,???) [000018] -c---+----- * LCL_VAR int V01 arg1 NA REG NA
Contained
DefList: { }
N018 (???,???) [000019] -c---+----- * CNS_INT int 0 REG NA
Contained
DefList: { }
N020 (???,???) [000020] -----+-N--- * CMP void REG NA
DefList: { }
N022 (???,???) [000021] -----+----- * JCC void cond=SGE REG NA
NEW BLOCK BB05
<RefPosition #2 @24 RefTypeBB BB05 regmask=[allMask] minReg=1 wt=50.00>
DefList: { }
N026 (???,???) [000022] H----+----- * CNS_INT(h) long 0x7ff7f15423c0 bbc REG NA
Interval 0: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #3 @27 RefTypeDef <Ivl:0> CNS_INT BB05 regmask=[allIntButFP] minReg=1 wt=200.00>
DefList: { N026.t22. CNS_INT }
N028 (???,???) [000037] ----------- * PUTARG_REG long REG rcx
<RefPosition #4 @28 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #5 @28 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed wt=50.00>
Interval 1: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #6 @29 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #7 @29 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed wt=200.00>
DefList: { N028.t37. PUTARG_REG }
N030 (???,???) [000023] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32 REG NA
<RefPosition #8 @30 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #9 @30 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #10 @31 RefTypeKill BB05 regmask=[rax rcx rdx r8-r11] minReg=1>
Interval 2: int RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #11 @31 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1 wt=50.00>
<RefPosition #12 @31 RefTypeDef <Ivl:2> CALL BB05 regmask=[rax] minReg=1 fixed wt=200.00>
NEW BLOCK BB03
<RefPosition #13 @32 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N034 (???,???) [000035] ----------- * IL_OFFSET void INLRT @ 0x008[E-] REG NA
DefList: { }
N036 (???,???) [000005] -----+----- * LCL_VAR int V01 arg1 NA REG NA
Interval 3: int RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #14 @37 RefTypeDef <Ivl:3> LCL_VAR BB03 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N036.t5. LCL_VAR }
N038 (???,???) [000038] ----------- * PUTARG_REG int REG rdx
<RefPosition #15 @38 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #16 @38 RefTypeUse <Ivl:3> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
Interval 4: int RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #17 @39 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #18 @39 RefTypeDef <Ivl:4> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00>
DefList: { N038.t38. PUTARG_REG }
N040 (???,???) [000028] H----+----- * CNS_INT(h) ref 'You tried to access this vector at index: {0}' REG NA
Interval 5: ref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #19 @41 RefTypeDef <Ivl:5> CNS_INT BB03 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N038.t38. PUTARG_REG; N040.t28. CNS_INT }
N042 (???,???) [000039] ----------- * PUTARG_REG ref REG rcx
<RefPosition #20 @42 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #21 @42 RefTypeUse <Ivl:5> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
Interval 6: ref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #22 @43 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #23 @43 RefTypeDef <Ivl:6> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00>
DefList: { N038.t38. PUTARG_REG; N042.t39. PUTARG_REG }
N044 (???,???) [000040] Hc--------- * CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
Contained
DefList: { N038.t38. PUTARG_REG; N042.t39. PUTARG_REG }
N046 (???,???) [000041] nc--G------ * IND long REG NA
Contained
DefList: { N038.t38. PUTARG_REG; N042.t39. PUTARG_REG }
N048 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA
<RefPosition #24 @48 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #25 @48 RefTypeUse <Ivl:4> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #26 @48 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #27 @48 RefTypeUse <Ivl:6> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #28 @49 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11] minReg=1>
NEW BLOCK BB04
<RefPosition #29 @50 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N052 (???,???) [000024] H----+----- * CNS_INT(h) long 0x7ff7f15423c4 bbc REG NA
Interval 7: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #30 @53 RefTypeDef <Ivl:7> CNS_INT BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N052.t24. CNS_INT }
N054 (???,???) [000042] ----------- * PUTARG_REG long REG rcx
<RefPosition #31 @54 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #32 @54 RefTypeUse <Ivl:7> BB04 regmask=[rcx] minReg=1 last fixed wt=100.00>
Interval 8: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #33 @55 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #34 @55 RefTypeDef <Ivl:8> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed wt=400.00>
DefList: { N054.t42. PUTARG_REG }
N056 (???,???) [000025] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32 REG NA
<RefPosition #35 @56 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #36 @56 RefTypeUse <Ivl:8> BB04 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #37 @57 RefTypeKill BB04 regmask=[rax rcx rdx r8-r11] minReg=1>
Interval 9: int RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #38 @57 RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #39 @57 RefTypeDef <Ivl:9> CALL BB04 regmask=[rax] minReg=1 fixed wt=400.00>
DefList: { }
N058 (???,???) [000036] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA
DefList: { }
N060 (???,???) [000008] -----+----- * LCL_VAR byref V00 arg0 NA REG NA
Interval 10: byref RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #40 @61 RefTypeDef <Ivl:10> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N060.t8. LCL_VAR }
N062 (???,???) [000029] DA---+----- * STORE_LCL_VAR long V03 tmp1 NA REG NA
<RefPosition #41 @62 RefTypeUse <Ivl:10> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
DefList: { }
N064 (???,???) [000030] -----+----- * LCL_VAR long V03 tmp1 NA REG NA
Interval 11: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #42 @65 RefTypeDef <Ivl:11> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N064.t30. LCL_VAR }
N066 (???,???) [000010] -c---+----- * LCL_VAR int V01 arg1 NA REG NA
Contained
DefList: { N064.t30. LCL_VAR }
N068 (???,???) [000011] -----+----- * CAST long <- int REG NA
Interval 12: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #43 @69 RefTypeDef <Ivl:12> CAST BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
DefList: { N064.t30. LCL_VAR; N068.t11. CAST }
N070 (???,???) [000015] -c---+----- * LEA(b+(i*4)+0) long REG NA
Contained
DefList: { N064.t30. LCL_VAR; N068.t11. CAST }
N072 (???,???) [000016] -A-XG+----- * IND float REG NA
<RefPosition #44 @72 RefTypeUse <Ivl:11> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #45 @72 RefTypeUse <Ivl:12> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
Interval 13: float RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[allMask]
<RefPosition #46 @73 RefTypeDef <Ivl:13> IND BB04 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N072.t16. IND }
N074 (???,???) [000017] -A-XG+----- * RETURN float REG NA
<RefPosition #47 @74 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #48 @74 RefTypeUse <Ivl:13> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
NEW BLOCK BB06
<RefPosition #49 @76 RefTypeBB BB06 regmask=[allMask] minReg=1 wt=50.00>
DefList: { }
N078 (???,???) [000026] H----+----- * CNS_INT(h) long 0x7ff7f15423c8 bbc REG NA
Interval 14: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #50 @79 RefTypeDef <Ivl:14> CNS_INT BB06 regmask=[allIntButFP] minReg=1 wt=200.00>
DefList: { N078.t26. CNS_INT }
N080 (???,???) [000043] ----------- * PUTARG_REG long REG rcx
<RefPosition #51 @80 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #52 @80 RefTypeUse <Ivl:14> BB06 regmask=[rcx] minReg=1 last fixed wt=50.00>
Interval 15: long RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #53 @81 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #54 @81 RefTypeDef <Ivl:15> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed wt=200.00>
DefList: { N080.t43. PUTARG_REG }
N082 (???,???) [000027] --CXG+----- * CALL help int CORINFO_HELP_COUNTPROFILE32 REG NA
<RefPosition #55 @82 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #56 @82 RefTypeUse <Ivl:15> BB06 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #57 @83 RefTypeKill BB06 regmask=[rax rcx rdx r8-r11] minReg=1>
Interval 16: int RefPositions {} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
<RefPosition #58 @83 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1 wt=50.00>
<RefPosition #59 @83 RefTypeDef <Ivl:16> CALL BB06 regmask=[rax] minReg=1 fixed wt=200.00>
<RefPosition #60 @84 RefTypeBB BB06 regmask=[allMask] minReg=1 wt=50.00>
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: long (constant) RefPositions {#3@27 #5@28} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 1: long RefPositions {#7@29 #9@30} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 2: int RefPositions {#12@31} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 3: int RefPositions {#14@37 #16@38} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 4: int RefPositions {#18@39 #25@48} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 5: ref (constant) RefPositions {#19@41 #21@42} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 6: ref RefPositions {#23@43 #27@48} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 7: long (constant) RefPositions {#30@53 #32@54} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 8: long RefPositions {#34@55 #36@56} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 9: int RefPositions {#39@57} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 10: byref RefPositions {#40@61 #41@62} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 11: long RefPositions {#42@65 #44@72} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 12: long RefPositions {#43@69 #45@72} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 13: float RefPositions {#46@73 #48@74} physReg:NA Preferences=[mm0] Aversions=[allMask]
Interval 14: long (constant) RefPositions {#50@79 #52@80} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 15: long RefPositions {#54@81 #56@82} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 16: int RefPositions {#59@83} physReg:NA Preferences=[rax] Aversions=[allMask]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #1 @12 RefTypeBB BB02 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #2 @24 RefTypeBB BB05 regmask=[allMask] minReg=1 wt=50.00>
<RefPosition #3 @27 RefTypeDef <Ivl:0> CNS_INT BB05 regmask=[rcx] minReg=1 wt=200.00>
<RefPosition #4 @28 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #5 @28 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #6 @29 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #7 @29 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed wt=200.00>
<RefPosition #8 @30 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #9 @30 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #10 @31 RefTypeKill BB05 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #11 @31 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1 wt=50.00>
<RefPosition #12 @31 RefTypeDef <Ivl:2> CALL BB05 regmask=[rax] minReg=1 last fixed local wt=200.00>
<RefPosition #13 @32 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #14 @37 RefTypeDef <Ivl:3> LCL_VAR BB03 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #15 @38 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #16 @38 RefTypeUse <Ivl:3> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #17 @39 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #18 @39 RefTypeDef <Ivl:4> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00>
<RefPosition #19 @41 RefTypeDef <Ivl:5> CNS_INT BB03 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #20 @42 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #21 @42 RefTypeUse <Ivl:5> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #22 @43 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #23 @43 RefTypeDef <Ivl:6> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00>
<RefPosition #24 @48 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #25 @48 RefTypeUse <Ivl:4> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #26 @48 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #27 @48 RefTypeUse <Ivl:6> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #28 @49 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #29 @50 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #30 @53 RefTypeDef <Ivl:7> CNS_INT BB04 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #31 @54 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #32 @54 RefTypeUse <Ivl:7> BB04 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #33 @55 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #34 @55 RefTypeDef <Ivl:8> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed wt=400.00>
<RefPosition #35 @56 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #36 @56 RefTypeUse <Ivl:8> BB04 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #37 @57 RefTypeKill BB04 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #38 @57 RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #39 @57 RefTypeDef <Ivl:9> CALL BB04 regmask=[rax] minReg=1 last fixed local wt=400.00>
<RefPosition #40 @61 RefTypeDef <Ivl:10> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #41 @62 RefTypeUse <Ivl:10> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #42 @65 RefTypeDef <Ivl:11> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #43 @69 RefTypeDef <Ivl:12> CAST BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #44 @72 RefTypeUse <Ivl:11> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #45 @72 RefTypeUse <Ivl:12> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #46 @73 RefTypeDef <Ivl:13> IND BB04 regmask=[mm0] minReg=1 wt=400.00>
<RefPosition #47 @74 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #48 @74 RefTypeUse <Ivl:13> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
<RefPosition #49 @76 RefTypeBB BB06 regmask=[allMask] minReg=1 wt=50.00>
<RefPosition #50 @79 RefTypeDef <Ivl:14> CNS_INT BB06 regmask=[rcx] minReg=1 wt=200.00>
<RefPosition #51 @80 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #52 @80 RefTypeUse <Ivl:14> BB06 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #53 @81 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #54 @81 RefTypeDef <Ivl:15> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed wt=200.00>
<RefPosition #55 @82 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #56 @82 RefTypeUse <Ivl:15> BB06 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #57 @83 RefTypeKill BB06 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #58 @83 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1 wt=50.00>
<RefPosition #59 @83 RefTypeDef <Ivl:16> CALL BB06 regmask=[rax] minReg=1 last fixed local wt=200.00>
<RefPosition #60 @84 RefTypeBB BB06 regmask=[allMask] minReg=1 wt=50.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
=====
N002. IL_OFFSET INLRT @ 0x000[E-]
N004. V01 MEM
N006. CNS_INT 1
N008. CMP
N010. JCC cond=SGT
BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
=====
N014. IL_OFFSET INLRT @ 0x004[E-]
N016. V01 MEM
N018. CNS_INT 0
N020. CMP
N022. JCC cond=SGE
BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
=====
N026. CNS_INT(h) 0x7ff7f15423c0 bbc
Def:<I0>(#3)
N028. PUTARG_REG
Use:<I0>(#5) Fixed:rcx(#4) *
Def:<I1>(#7) rcx
N030. CALL help
Use:<I1>(#9) Fixed:rcx(#8) *
Kill: [rax rcx rdx r8-r11]
Def:<I2>(#12) rax LocalDefUse *
BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
=====
N034. IL_OFFSET INLRT @ 0x008[E-]
N036. V01 MEM
Def:<I3>(#14)
N038. PUTARG_REG
Use:<I3>(#16) Fixed:rdx(#15) *
Def:<I4>(#18) rdx
N040. CNS_INT(h) 'You tried to access this vector at index: {0}'
Def:<I5>(#19)
N042. PUTARG_REG
Use:<I5>(#21) Fixed:rcx(#20) *
Def:<I6>(#23) rcx
N044. CNS_INT(h) 0x7ff7f13342a0 ftn
N046. IND
N048. CALL
Use:<I4>(#25) Fixed:rdx(#24) *
Use:<I6>(#27) Fixed:rcx(#26) *
Kill: [rax rcx rdx r8-r11]
BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
=====
N052. CNS_INT(h) 0x7ff7f15423c4 bbc
Def:<I7>(#30)
N054. PUTARG_REG
Use:<I7>(#32) Fixed:rcx(#31) *
Def:<I8>(#34) rcx
N056. CALL help
Use:<I8>(#36) Fixed:rcx(#35) *
Kill: [rax rcx rdx r8-r11]
Def:<I9>(#39) rax LocalDefUse *
N058. IL_OFFSET INLRT @ 0x013[E-]
N060. V00 MEM
Def:<I10>(#40)
N062. V03 MEM
Use:<I10>(#41) *
N064. V03 MEM
Def:<I11>(#42)
N066. V01 MEM
N068. CAST
Def:<I12>(#43)
N070. LEA(b+(i*4)+0)
N072. IND
Use:<I11>(#44) *
Use:<I12>(#45) *
Def:<I13>(#46)
N074. RETURN
Use:<I13>(#48) Fixed:mm0(#47) *
BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
=====
N078. CNS_INT(h) 0x7ff7f15423c8 bbc
Def:<I14>(#50)
N080. PUTARG_REG
Use:<I14>(#52) Fixed:rcx(#51) *
Def:<I15>(#54) rcx
N082. CALL help
Use:<I15>(#56) Fixed:rcx(#55) *
Kill: [rax rcx rdx r8-r11]
Def:<I16>(#59) rax LocalDefUse *
Linear scan intervals after buildIntervals:
Interval 0: long (constant) RefPositions {#3@27 #5@28} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 1: long RefPositions {#7@29 #9@30} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 2: int RefPositions {#12@31} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 3: int RefPositions {#14@37 #16@38} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 4: int RefPositions {#18@39 #25@48} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 5: ref (constant) RefPositions {#19@41 #21@42} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 6: ref RefPositions {#23@43 #27@48} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 7: long (constant) RefPositions {#30@53 #32@54} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 8: long RefPositions {#34@55 #36@56} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 9: int RefPositions {#39@57} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 10: byref RefPositions {#40@61 #41@62} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 11: long RefPositions {#42@65 #44@72} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 12: long RefPositions {#43@69 #45@72} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 13: float RefPositions {#46@73 #48@74} physReg:NA Preferences=[mm0] Aversions=[allMask]
Interval 14: long (constant) RefPositions {#50@79 #52@80} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 15: long RefPositions {#54@81 #56@82} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 16: int RefPositions {#59@83} physReg:NA Preferences=[rax] Aversions=[allMask]
*************** In LinearScan::allocateRegistersMinimal()
Linear scan intervals before allocateRegistersMinimal:
Interval 0: long (constant) RefPositions {#3@27 #5@28} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 1: long RefPositions {#7@29 #9@30} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 2: int RefPositions {#12@31} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 3: int RefPositions {#14@37 #16@38} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 4: int RefPositions {#18@39 #25@48} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 5: ref (constant) RefPositions {#19@41 #21@42} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 6: ref RefPositions {#23@43 #27@48} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 7: long (constant) RefPositions {#30@53 #32@54} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 8: long RefPositions {#34@55 #36@56} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 9: int RefPositions {#39@57} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 10: byref RefPositions {#40@61 #41@62} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 11: long RefPositions {#42@65 #44@72} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 12: long RefPositions {#43@69 #45@72} physReg:NA Preferences=[allIntButFP] Aversions=[allMask]
Interval 13: float RefPositions {#46@73 #48@74} physReg:NA Preferences=[mm0] Aversions=[allMask]
Interval 14: long (constant) RefPositions {#50@79 #52@80} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 15: long RefPositions {#54@81 #56@82} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 16: int RefPositions {#59@83} physReg:NA Preferences=[rax] Aversions=[allMask]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #1 @12 RefTypeBB BB02 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #2 @24 RefTypeBB BB05 regmask=[allMask] minReg=1 wt=50.00>
<RefPosition #3 @27 RefTypeDef <Ivl:0> CNS_INT BB05 regmask=[rcx] minReg=1 wt=200.00>
<RefPosition #4 @28 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #5 @28 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #6 @29 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #7 @29 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed wt=200.00>
<RefPosition #8 @30 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #9 @30 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #10 @31 RefTypeKill BB05 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #11 @31 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1 wt=50.00>
<RefPosition #12 @31 RefTypeDef <Ivl:2> CALL BB05 regmask=[rax] minReg=1 last fixed local wt=200.00>
<RefPosition #13 @32 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #14 @37 RefTypeDef <Ivl:3> LCL_VAR BB03 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #15 @38 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #16 @38 RefTypeUse <Ivl:3> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #17 @39 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #18 @39 RefTypeDef <Ivl:4> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00>
<RefPosition #19 @41 RefTypeDef <Ivl:5> CNS_INT BB03 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #20 @42 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #21 @42 RefTypeUse <Ivl:5> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #22 @43 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #23 @43 RefTypeDef <Ivl:6> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00>
<RefPosition #24 @48 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #25 @48 RefTypeUse <Ivl:4> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #26 @48 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #27 @48 RefTypeUse <Ivl:6> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #28 @49 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #29 @50 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #30 @53 RefTypeDef <Ivl:7> CNS_INT BB04 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #31 @54 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #32 @54 RefTypeUse <Ivl:7> BB04 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #33 @55 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #34 @55 RefTypeDef <Ivl:8> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed wt=400.00>
<RefPosition #35 @56 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #36 @56 RefTypeUse <Ivl:8> BB04 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #37 @57 RefTypeKill BB04 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #38 @57 RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #39 @57 RefTypeDef <Ivl:9> CALL BB04 regmask=[rax] minReg=1 last fixed local wt=400.00>
<RefPosition #40 @61 RefTypeDef <Ivl:10> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #41 @62 RefTypeUse <Ivl:10> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #42 @65 RefTypeDef <Ivl:11> LCL_VAR BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #43 @69 RefTypeDef <Ivl:12> CAST BB04 regmask=[allIntButFP] minReg=1 wt=400.00>
<RefPosition #44 @72 RefTypeUse <Ivl:11> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #45 @72 RefTypeUse <Ivl:12> BB04 regmask=[allIntButFP] minReg=1 last wt=100.00>
<RefPosition #46 @73 RefTypeDef <Ivl:13> IND BB04 regmask=[mm0] minReg=1 wt=400.00>
<RefPosition #47 @74 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #48 @74 RefTypeUse <Ivl:13> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
<RefPosition #49 @76 RefTypeBB BB06 regmask=[allMask] minReg=1 wt=50.00>
<RefPosition #50 @79 RefTypeDef <Ivl:14> CNS_INT BB06 regmask=[rcx] minReg=1 wt=200.00>
<RefPosition #51 @80 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #52 @80 RefTypeUse <Ivl:14> BB06 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #53 @81 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #54 @81 RefTypeDef <Ivl:15> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed wt=200.00>
<RefPosition #55 @82 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #56 @82 RefTypeUse <Ivl:15> BB06 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #57 @83 RefTypeKill BB06 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #58 @83 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1 wt=50.00>
<RefPosition #59 @83 RefTypeDef <Ivl:16> CALL BB06 regmask=[rax] minReg=1 last fixed local wt=200.00>
<RefPosition #60 @84 RefTypeBB BB06 regmask=[allMask] minReg=1 wt=50.00>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| | | | | | | | | | | | | | |
0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
12.#1 BB2 PredBB0 | | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
24.#2 BB5 PredBB0 | | | | | | | | | | | | | | |
[000022] 27.#3 C0 Def Alloc rcx | |C0 a| | | | | | | | | | | | |
[000037] 28.#4 rcx Fixd Keep rcx | |C0 a| | | | | | | | | | | | |
28.#5 C0 Use * Keep rcx | |C0 a| | | | | | | | | | | | |
29.#6 rcx Fixd Keep rcx | | | | | | | | | | | | | | |
29.#7 I1 Def Alloc rcx | |I1 a| | | | | | | | | | | | |
[000023] 30.#8 rcx Fixd Keep rcx | |I1 a| | | | | | | | | | | | |
30.#9 I1 Use * Keep rcx | |I1 a| | | | | | | | | | | | |
31.#10 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
31.#11 rax Fixd Keep rax | | | | | | | | | | | | | | |
31.#12 I2 Def * Alloc rax |I2 a| | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
32.#13 BB3 PredBB0 | | | | | | | | | | | | | | |
[000005] 37.#14 I3 Def Alloc rdx | | |I3 a| | | | | | | | | | | |
[000038] 38.#15 rdx Fixd Keep rdx | | |I3 a| | | | | | | | | | | |
38.#16 I3 Use * Keep rdx | | |I3 a| | | | | | | | | | | |
39.#17 rdx Fixd Keep rdx | | | | | | | | | | | | | | |
39.#18 I4 Def Alloc rdx | | |I4 a| | | | | | | | | | | |
[000028] 41.#19 C5 Def Alloc rcx | |C5 a|I4 a| | | | | | | | | | | |
[000039] 42.#20 rcx Fixd Keep rcx | |C5 a|I4 a| | | | | | | | | | | |
42.#21 C5 Use * Keep rcx | |C5 a|I4 a| | | | | | | | | | | |
43.#22 rcx Fixd Keep rcx | | |I4 a| | | | | | | | | | | |
43.#23 I6 Def Alloc rcx | |I6 a|I4 a| | | | | | | | | | | |
[000006] 48.#24 rdx Fixd Keep rdx | |I6 a|I4 a| | | | | | | | | | | |
48.#25 I4 Use * Keep rdx | |I6 a|I4 a| | | | | | | | | | | |
48.#26 rcx Fixd Keep rcx | |I6 a|I4 a| | | | | | | | | | | |
48.#27 I6 Use * Keep rcx | |I6 a|I4 a| | | | | | | | | | | |
49.#28 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
50.#29 BB4 PredBB0 | | | | | | | | | | | | | | |
[000024] 53.#30 C7 Def Alloc rcx | |C7 a| | | | | | | | | | | | |
[000042] 54.#31 rcx Fixd Keep rcx | |C7 a| | | | | | | | | | | | |
54.#32 C7 Use * Keep rcx | |C7 a| | | | | | | | | | | | |
55.#33 rcx Fixd Keep rcx | | | | | | | | | | | | | | |
55.#34 I8 Def Alloc rcx | |I8 a| | | | | | | | | | | | |
[000025] 56.#35 rcx Fixd Keep rcx | |I8 a| | | | | | | | | | | | |
56.#36 I8 Use * Keep rcx | |I8 a| | | | | | | | | | | | |
57.#37 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
57.#38 rax Fixd Keep rax | | | | | | | | | | | | | | |
57.#39 I9 Def * Alloc rax |I9 a| | | | | | | | | | | | | |
[000008] 61.#40 I10 Def ORDER(A) rax |I10a| | | | | | | | | | | | | |
[000029] 62.#41 I10 Use * Keep rax |I10a| | | | | | | | | | | | | |
[000030] 65.#42 I11 Def ORDER(A) rax |I11a| | | | | | | | | | | | | |
[000011] 69.#43 I12 Def ORDER(A) rcx |I11a|I12a| | | | | | | | | | | | |
[000016] 72.#44 I11 Use * Keep rax |I11a|I12a| | | | | | | | | | | | |
72.#45 I12 Use * Keep rcx |I11a|I12a| | | | | | | | | | | | |
73.#46 I13 Def Alloc mm0 | | | | | | | | | |I13a| | | | |
[000017] 74.#47 mm0 Fixd Keep mm0 | | | | | | | | | |I13a| | | | |
74.#48 I13 Use * Keep mm0 | | | | | | | | | |I13a| | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
76.#49 BB6 PredBB0 | | | | | | | | | | | | | | |
[000026] 79.#50 C14 Def Alloc rcx | |C14a| | | | | | | | | | | | |
[000043] 80.#51 rcx Fixd Keep rcx | |C14a| | | | | | | | | | | | |
80.#52 C14 Use * Keep rcx | |C14a| | | | | | | | | | | | |
81.#53 rcx Fixd Keep rcx | | | | | | | | | | | | | | |
81.#54 I15 Def Alloc rcx | |I15a| | | | | | | | | | | | |
[000027] 82.#55 rcx Fixd Keep rcx | |I15a| | | | | | | | | | | | |
82.#56 I15 Use * Keep rcx | |I15a| | | | | | | | | | | | |
83.#57 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
83.#58 rax Fixd Keep rax | | | | | | | | | | | | | | |
83.#59 I16 Def * Alloc rax |I16a| | | | | | | | | | | | | |
84.#60 END | | | | | | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #1 @12 RefTypeBB BB02 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #2 @24 RefTypeBB BB05 regmask=[allMask] minReg=1 wt=50.00>
<RefPosition #3 @27 RefTypeDef <Ivl:0> CNS_INT BB05 regmask=[rcx] minReg=1 wt=200.00>
<RefPosition #4 @28 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #5 @28 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #6 @29 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #7 @29 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed wt=200.00>
<RefPosition #8 @30 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #9 @30 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #10 @31 RefTypeKill BB05 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #11 @31 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1 wt=50.00>
<RefPosition #12 @31 RefTypeDef <Ivl:2> CALL BB05 regmask=[rax] minReg=1 last fixed local wt=200.00>
<RefPosition #13 @32 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #14 @37 RefTypeDef <Ivl:3> LCL_VAR BB03 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #15 @38 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #16 @38 RefTypeUse <Ivl:3> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #17 @39 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #18 @39 RefTypeDef <Ivl:4> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=400.00>
<RefPosition #19 @41 RefTypeDef <Ivl:5> CNS_INT BB03 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #20 @42 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #21 @42 RefTypeUse <Ivl:5> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #22 @43 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #23 @43 RefTypeDef <Ivl:6> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=400.00>
<RefPosition #24 @48 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=100.00>
<RefPosition #25 @48 RefTypeUse <Ivl:4> BB03 regmask=[rdx] minReg=1 last fixed wt=100.00>
<RefPosition #26 @48 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #27 @48 RefTypeUse <Ivl:6> BB03 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #28 @49 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #29 @50 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #30 @53 RefTypeDef <Ivl:7> CNS_INT BB04 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #31 @54 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #32 @54 RefTypeUse <Ivl:7> BB04 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #33 @55 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #34 @55 RefTypeDef <Ivl:8> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed wt=400.00>
<RefPosition #35 @56 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1 wt=100.00>
<RefPosition #36 @56 RefTypeUse <Ivl:8> BB04 regmask=[rcx] minReg=1 last fixed wt=100.00>
<RefPosition #37 @57 RefTypeKill BB04 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #38 @57 RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #39 @57 RefTypeDef <Ivl:9> CALL BB04 regmask=[rax] minReg=1 last fixed local wt=400.00>
<RefPosition #40 @61 RefTypeDef <Ivl:10> LCL_VAR BB04 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #41 @62 RefTypeUse <Ivl:10> BB04 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #42 @65 RefTypeDef <Ivl:11> LCL_VAR BB04 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #43 @69 RefTypeDef <Ivl:12> CAST BB04 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #44 @72 RefTypeUse <Ivl:11> BB04 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #45 @72 RefTypeUse <Ivl:12> BB04 regmask=[rcx] minReg=1 last wt=100.00>
<RefPosition #46 @73 RefTypeDef <Ivl:13> IND BB04 regmask=[mm0] minReg=1 wt=400.00>
<RefPosition #47 @74 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #48 @74 RefTypeUse <Ivl:13> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
<RefPosition #49 @76 RefTypeBB BB06 regmask=[allMask] minReg=1 wt=50.00>
<RefPosition #50 @79 RefTypeDef <Ivl:14> CNS_INT BB06 regmask=[rcx] minReg=1 wt=200.00>
<RefPosition #51 @80 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #52 @80 RefTypeUse <Ivl:14> BB06 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #53 @81 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #54 @81 RefTypeDef <Ivl:15> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed wt=200.00>
<RefPosition #55 @82 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1 wt=50.00>
<RefPosition #56 @82 RefTypeUse <Ivl:15> BB06 regmask=[rcx] minReg=1 last fixed wt=50.00>
<RefPosition #57 @83 RefTypeKill BB06 regmask=[rax rcx rdx r8-r11] minReg=1>
<RefPosition #58 @83 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1 wt=50.00>
<RefPosition #59 @83 RefTypeDef <Ivl:16> CALL BB06 regmask=[rax] minReg=1 last fixed local wt=200.00>
<RefPosition #60 @84 RefTypeBB BB06 regmask=[allMask] minReg=1 wt=50.00>
Active intervals at end of allocation:
Trees after linear scan register allocator (LSRA)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i LIR
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i LIR internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i LIR hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i LIR internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
N002 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N004 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1 NA REG NA
N006 (???,???) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
N008 (???,???) [000002] -----+-N--- * CMP void REG NA
N010 (???,???) [000003] -----+----- JCC void cond=SGT REG NA
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
N014 (???,???) [000034] ----------- IL_OFFSET void INLRT @ 0x004[E-] REG NA
N016 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1 NA REG NA
N018 (???,???) [000019] -c---+----- t19 = CNS_INT int 0 REG NA
/--* t18 int
+--* t19 int
N020 (???,???) [000020] -----+-N--- * CMP void REG NA
N022 (???,???) [000021] -----+----- JCC void cond=SGE REG NA
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
N026 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc REG rcx
/--* t22 long
N028 (???,???) [000037] ----------- t37 = * PUTARG_REG long REG rcx
/--* t37 long arg0 rcx
N030 (???,???) [000023] --CXG+----- u23 = * CALL help int CORINFO_HELP_COUNTPROFILE32 REG rax
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
N034 (???,???) [000035] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
N036 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1 rdx REG rdx
/--* t5 int
N038 (???,???) [000038] ----------- t38 = * PUTARG_REG int REG rdx
N040 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}' REG rcx
/--* t28 ref
N042 (???,???) [000039] ----------- t39 = * PUTARG_REG ref REG rcx
N044 (???,???) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t40 long
N046 (???,???) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 int arg1 rdx
+--* t39 ref arg0 rcx
+--* t41 long control expr
N048 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
N052 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc REG rcx
/--* t24 long
N054 (???,???) [000042] ----------- t42 = * PUTARG_REG long REG rcx
/--* t42 long arg0 rcx
N056 (???,???) [000025] --CXG+----- u25 = * CALL help int CORINFO_HELP_COUNTPROFILE32 REG rax
N058 (???,???) [000036] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
N060 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 rax REG rax
/--* t8 byref
N062 (???,???) [000029] DA---+----- * STORE_LCL_VAR long V03 tmp1 NA REG NA
N064 (???,???) [000030] -----+----- t30 = LCL_VAR long V03 tmp1 rax REG rax
N066 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1 NA REG NA
/--* t10 int
N068 (???,???) [000011] -----+----- t11 = * CAST long <- int REG rcx
/--* t30 long
+--* t11 long
N070 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
N072 (???,???) [000016] -A-XG+----- t16 = * IND float REG mm0
/--* t16 float
N074 (???,???) [000017] -A-XG+----- * RETURN float REG NA
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
N078 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc REG rcx
/--* t26 long
N080 (???,???) [000043] ----------- t43 = * PUTARG_REG long REG rcx
/--* t43 long arg0 rcx
N082 (???,???) [000027] --CXG+----- u27 = * CALL help int CORINFO_HELP_COUNTPROFILE32 REG rax
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
12.#1 BB2 PredBB0 | | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
24.#2 BB5 PredBB0 | | | | | | | | | | | | | | |
[000022] 27.#3 C0 Def Alloc rcx | |C0 a| | | | | | | | | | | | |
[000037] 28.#4 rcx Fixd Keep rcx | |C0 a| | | | | | | | | | | | |
28.#5 C0 Use * Keep rcx | |C0 i| | | | | | | | | | | | |
29.#6 rcx Fixd Keep rcx | | | | | | | | | | | | | | |
29.#7 I1 Def Alloc rcx | |I1 a| | | | | | | | | | | | |
[000023] 30.#8 rcx Fixd Keep rcx | |I1 a| | | | | | | | | | | | |
30.#9 I1 Use * Keep rcx | |I1 i| | | | | | | | | | | | |
31.#10 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
31.#11 rax Fixd Keep rax | | | | | | | | | | | | | | |
31.#12 I2 Def * Alloc rax |I2 i| | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
32.#13 BB3 PredBB0 | | | | | | | | | | | | | | |
[000005] 37.#14 I3 Def Alloc rdx | | |I3 a| | | | | | | | | | | |
[000038] 38.#15 rdx Fixd Keep rdx | | |I3 a| | | | | | | | | | | |
38.#16 I3 Use * Keep rdx | | |I3 i| | | | | | | | | | | |
39.#17 rdx Fixd Keep rdx | | | | | | | | | | | | | | |
39.#18 I4 Def Alloc rdx | | |I4 a| | | | | | | | | | | |
[000028] 41.#19 C5 Def Alloc rcx | |C5 a|I4 a| | | | | | | | | | | |
[000039] 42.#20 rcx Fixd Keep rcx | |C5 a|I4 a| | | | | | | | | | | |
42.#21 C5 Use * Keep rcx | |C5 i|I4 a| | | | | | | | | | | |
43.#22 rcx Fixd Keep rcx | | |I4 a| | | | | | | | | | | |
43.#23 I6 Def Alloc rcx | |I6 a|I4 a| | | | | | | | | | | |
[000006] 48.#24 rdx Fixd Keep rdx | |I6 a|I4 a| | | | | | | | | | | |
48.#25 I4 Use * Keep rdx | |I6 a|I4 i| | | | | | | | | | | |
48.#26 rcx Fixd Keep rcx | |I6 a| | | | | | | | | | | | |
48.#27 I6 Use * Keep rcx | |I6 i| | | | | | | | | | | | |
49.#28 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
50.#29 BB4 PredBB0 | | | | | | | | | | | | | | |
[000024] 53.#30 C7 Def Alloc rcx | |C7 a| | | | | | | | | | | | |
[000042] 54.#31 rcx Fixd Keep rcx | |C7 a| | | | | | | | | | | | |
54.#32 C7 Use * Keep rcx | |C7 i| | | | | | | | | | | | |
55.#33 rcx Fixd Keep rcx | | | | | | | | | | | | | | |
55.#34 I8 Def Alloc rcx | |I8 a| | | | | | | | | | | | |
[000025] 56.#35 rcx Fixd Keep rcx | |I8 a| | | | | | | | | | | | |
56.#36 I8 Use * Keep rcx | |I8 i| | | | | | | | | | | | |
57.#37 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
57.#38 rax Fixd Keep rax | | | | | | | | | | | | | | |
57.#39 I9 Def * Alloc rax |I9 i| | | | | | | | | | | | | |
[000008] 61.#40 I10 Def Alloc rax |I10a| | | | | | | | | | | | | |
[000029] 62.#41 I10 Use * Keep rax |I10i| | | | | | | | | | | | | |
[000030] 65.#42 I11 Def Alloc rax |I11a| | | | | | | | | | | | | |
[000011] 69.#43 I12 Def Alloc rcx |I11a|I12a| | | | | | | | | | | | |
[000016] 72.#44 I11 Use * Keep rax |I11i|I12a| | | | | | | | | | | | |
72.#45 I12 Use * Keep rcx | |I12i| | | | | | | | | | | | |
73.#46 I13 Def Alloc mm0 | | | | | | | | | |I13a| | | | |
[000017] 74.#47 mm0 Fixd Keep mm0 | | | | | | | | | |I13a| | | | |
74.#48 I13 Use * Keep mm0 | | | | | | | | | |I13i| | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
76.#49 BB6 PredBB0 | | | | | | | | | | | | | | |
[000026] 79.#50 C14 Def Alloc rcx | |C14a| | | | | | | | | | | | |
[000043] 80.#51 rcx Fixd Keep rcx | |C14a| | | | | | | | | | | | |
80.#52 C14 Use * Keep rcx | |C14i| | | | | | | | | | | | |
81.#53 rcx Fixd Keep rcx | | | | | | | | | | | | | | |
81.#54 I15 Def Alloc rcx | |I15a| | | | | | | | | | | | |
[000027] 82.#55 rcx Fixd Keep rcx | |I15a| | | | | | | | | | | | |
82.#56 I15 Use * Keep rcx | |I15i| | | | | | | | | | | | |
83.#57 Kill None [rax rcx rdx r8-r11]
| | | | | | | | | | | | | | |
83.#58 rax Fixd Keep rax | | | | | | | | | | | | | | |
83.#59 I16 Def * Alloc rax |I16i| | | | | | | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars: 0
Total Reg Cand Vars: 0
Total number of Intervals: 16
Total number of RefPositions: 60
Total Number of spill temps created: 0
..........
BB04 [ 100.00]: REG_ORDER = 3
..........
Total SpillCount : 0 Weighted: 0.000000
Total CopyReg : 0 Weighted: 0.000000
Total ResolutionMovs : 0 Weighted: 0.000000
Total SplitEdges : 0 Weighted: 0.000000
..........
Total REG_ORDER [#13] : 3 Weighted: 300.000000
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
=====
N002. IL_OFFSET INLRT @ 0x000[E-]
N004. V01 MEM
N006. CNS_INT 1
N008. CMP
N010. JCC cond=SGT
BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
=====
N014. IL_OFFSET INLRT @ 0x004[E-]
N016. V01 MEM
N018. CNS_INT 0
N020. CMP
N022. JCC cond=SGE
BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
=====
N026. rcx = CNS_INT(h) 0x7ff7f15423c0 bbc
N028. rcx = PUTARG_REG; rcx
* N030. rax = CALL help; rcx
BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
=====
N034. IL_OFFSET INLRT @ 0x008[E-]
N036. rdx = V01 MEM
N038. rdx = PUTARG_REG; rdx
N040. rcx = CNS_INT(h) 'You tried to access this vector at index: {0}'
N042. rcx = PUTARG_REG; rcx
N044. CNS_INT(h) 0x7ff7f13342a0 ftn
N046. IND
N048. CALL ; rdx,rcx
BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
=====
N052. rcx = CNS_INT(h) 0x7ff7f15423c4 bbc
N054. rcx = PUTARG_REG; rcx
* N056. rax = CALL help; rcx
N058. IL_OFFSET INLRT @ 0x013[E-]
N060. rax = V00 MEM
N062. V03 MEM; rax
N064. rax = V03 MEM
N066. V01 MEM
N068. rcx = CAST
N070. STK = LEA(b+(i*4)+0); rax,rcx
N072. mm0 = IND ; STK
N074. RETURN ; mm0
BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
=====
N078. rcx = CNS_INT(h) 0x7ff7f15423c8 bbc
N080. rcx = PUTARG_REG; rcx
* N082. rax = CALL help; rcx
*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i LIR
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i LIR internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i LIR hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i LIR internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
N002 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N004 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1 NA REG NA
N006 (???,???) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
N008 (???,???) [000002] -----+-N--- * CMP void REG NA
N010 (???,???) [000003] -----+----- JCC void cond=SGT REG NA
------------ BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06}
N014 (???,???) [000034] ----------- IL_OFFSET void INLRT @ 0x004[E-] REG NA
N016 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1 NA REG NA
N018 (???,???) [000019] -c---+----- t19 = CNS_INT int 0 REG NA
/--* t18 int
+--* t19 int
N020 (???,???) [000020] -----+-N--- * CMP void REG NA
N022 (???,???) [000021] -----+----- JCC void cond=SGE REG NA
------------ BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03}
N026 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc REG rcx
/--* t22 long
N028 (???,???) [000037] ----------- t37 = * PUTARG_REG long REG rcx
/--* t37 long arg0 rcx
N030 (???,???) [000023] --CXG+----- u23 = * CALL help int CORINFO_HELP_COUNTPROFILE32 REG rax
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04}
N034 (???,???) [000035] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
N036 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1 rdx REG rdx
/--* t5 int
N038 (???,???) [000038] ----------- t38 = * PUTARG_REG int REG rdx
N040 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}' REG rcx
/--* t28 ref
N042 (???,???) [000039] ----------- t39 = * PUTARG_REG ref REG rcx
N044 (???,???) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t40 long
N046 (???,???) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 int arg1 rdx
+--* t39 ref arg0 rcx
+--* t41 long control expr
N048 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA
------------ BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={}
N052 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc REG rcx
/--* t24 long
N054 (???,???) [000042] ----------- t42 = * PUTARG_REG long REG rcx
/--* t42 long arg0 rcx
N056 (???,???) [000025] --CXG+----- u25 = * CALL help int CORINFO_HELP_COUNTPROFILE32 REG rax
N058 (???,???) [000036] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
N060 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 rax REG rax
/--* t8 byref
N062 (???,???) [000029] DA---+----- * STORE_LCL_VAR long V03 tmp1 NA REG NA
N064 (???,???) [000030] -----+----- t30 = LCL_VAR long V03 tmp1 rax REG rax
N066 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1 NA REG NA
/--* t10 int
N068 (???,???) [000011] -----+----- t11 = * CAST long <- int REG rcx
/--* t30 long
+--* t11 long
N070 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
N072 (???,???) [000016] -A-XG+----- t16 = * IND float REG mm0
/--* t16 float
N074 (???,???) [000017] -A-XG+----- * RETURN float REG NA
------------ BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04}
N078 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc REG rcx
/--* t26 long
N080 (???,???) [000043] ----------- t43 = * PUTARG_REG long REG rcx
/--* t43 long arg0 rcx
N082 (???,???) [000027] --CXG+----- u27 = * CALL help int CORINFO_HELP_COUNTPROFILE32 REG rax
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Place 'align' instructions
*************** In placeLoopAlignInstructions()
Not aligning loops; ShouldAlignLoops is false
*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i LIR
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i LIR internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i LIR hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i LIR hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i LIR internal hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [rax rcx rdx r8-r11 mm0]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Set V00 to offset 0
Set V01 to offset 8
Assign V03 tmp1, size=8, stkOffs=-0x18
Assign V02 OutArgs, size=32, stkOffs=-0x38
--- delta bump 8 for RA
--- delta bump 8 for FP
--- delta bump 0 for FP frame
--- virtual stack offset to actual stack offset delta is 16
-- V00 was 0, now 16
-- V01 was 8, now 24
-- V02 was -56, now -40
-- V03 was -24, now -8
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) byref -> [rbp+0x10] do-not-enreg[] ld-addr-op
; V01 arg1 [V01 ] ( 1, 1 ) int -> [rbp+0x18] do-not-enreg[]
; V02 OutArgs [V02 ] ( 1, 1 ) struct (32) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <UNNAMED>
; V03 tmp1 [V03 ] ( 1, 1 ) long -> [rbp-0x08] do-not-enreg[] "Cast away GC"
;
; Lcl frame size = 48
Created:
G_M62292_IG02: ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
BB01 : first block
BB03 : branch target
BB06 : branch target
BB04 : branch target
*************** After genMarkLabelsForCodegen()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond ) i LIR label
BB02 [0001] 1 BB01 1 [004..008)-> BB06(0.5),BB05(0.5) ( cond ) i LIR
BB05 [0004] 1 BB02 0.50 [???..???)-> BB03(1) (always) i LIR internal hascall
BB03 [0002] 2 BB01,BB05 1 [008..013)-> BB04(1) (always) i LIR label hascall gcsafe
BB04 [0003] 2 BB03,BB06 1 [013..022) (return) i LIR label hascall
BB06 [0005] 1 BB02 0.50 [???..???)-> BB04(1) (always) i LIR internal label hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
=============== Generating BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} flags=0x00000000.00001011: i LIR label
BB01 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB01:
Label: G_M62292_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB01, IL range [000..004)
Scope info: opening scope, LVnum=0 [000..022)
Debug: New V00 debug range: first
Scope info: opening scope, LVnum=1 [000..022)
Debug: New V01 debug range: first
Added IP mapping: 0x0000 STACK_EMPTY (G_M62292_IG02,ins#0,ofs#0) label
Generating: N002 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N004 (???,???) [000000] -c---+----- t0 = LCL_VAR int V01 arg1 NA REG NA
Generating: N006 (???,???) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
Generating: N008 (???,???) [000002] -----+-N--- * CMP void REG NA
Mapped BB01 to G_M62292_IG02
IN0001: cmp dword ptr [V01 rbp+0x18], 1
Generating: N010 (???,???) [000003] -----+----- JCC void cond=SGT REG NA
IN0002: jg L_M62292_BB03
Variable Live Range History Dump for BB01
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
=============== Generating BB02 [0001] [004..008) -> BB06(0.5),BB05(0.5) (cond), preds={BB01} succs={BB05,BB06} flags=0x00000000.00000011: i LIR
BB02 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB02:
Scope info: begin block BB02, IL range [004..008)
Added IP mapping: 0x0004 STACK_EMPTY (G_M62292_IG02,ins#2,ofs#10) label
Generating: N014 (???,???) [000034] ----------- IL_OFFSET void INLRT @ 0x004[E-] REG NA
Generating: N016 (???,???) [000018] -c---+----- t18 = LCL_VAR int V01 arg1 NA REG NA
Generating: N018 (???,???) [000019] -c---+----- t19 = CNS_INT int 0 REG NA
/--* t18 int
+--* t19 int
Generating: N020 (???,???) [000020] -----+-N--- * CMP void REG NA
Mapped BB02 to G_M62292_IG02
IN0003: cmp dword ptr [V01 rbp+0x18], 0
Generating: N022 (???,???) [000021] -----+----- JCC void cond=SGE REG NA
IN0004: jge L_M62292_BB06
Variable Live Range History Dump for BB02
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
=============== Generating BB05 [0004] [???..???) -> BB03(1) (always), preds={BB02} succs={BB03} flags=0x00000000.02000031: i LIR internal hascall
BB05 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB05:
Adding label due to BB weight difference: BBJ_COND BB02 with weight 100 different from BB05 with weight 50
Saved:
G_M62292_IG02: ; offs=0x000000, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref
Created:
G_M62292_IG03: ; offs=0x000014, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {}
Label: G_M62292_IG03, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB05, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP (G_M62292_IG03,ins#0,ofs#0) label
Generating: N026 (???,???) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f15423c0 bbc REG rcx
Mapped BB05 to G_M62292_IG03
IN0005: mov rcx, 0x7FF7F15423C0
/--* t22 long
Generating: N028 (???,???) [000037] ----------- t37 = * PUTARG_REG long REG rcx
/--* t37 long arg0 rcx
Generating: N030 (???,???) [000023] --CXG+----- u23 = * CALL help int CORINFO_HELP_COUNTPROFILE32 REG rax
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0006: call CORINFO_HELP_COUNTPROFILE32
Scope info: ignoring block end
Variable Live Range History Dump for BB05
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
=============== Generating BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB05} succs={BB04} flags=0x00000000.02011011: i LIR label hascall gcsafe
BB03 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB03:
Saved:
G_M62292_IG03: ; offs=0x000014, size=0x000F, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0004], byref
Created:
G_M62292_IG04: ; offs=0x000023, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Label: G_M62292_IG04, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB03, IL range [008..013)
Added IP mapping: 0x0008 STACK_EMPTY (G_M62292_IG04,ins#0,ofs#0) label
Generating: N034 (???,???) [000035] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
Generating: N036 (???,???) [000005] -----+----- t5 = LCL_VAR int V01 arg1 rdx REG rdx
Mapped BB03 to G_M62292_IG04
IN0007: mov edx, dword ptr [V01 rbp+0x18]
/--* t5 int
Generating: N038 (???,???) [000038] ----------- t38 = * PUTARG_REG int REG rdx
Generating: N040 (???,???) [000028] H----+----- t28 = CNS_INT(h) ref 'You tried to access this vector at index: {0}' REG rcx
IN0008: mov rcx, 0x230618FF1E8 ; 'You tried to access this vector at index: {0}'
GC regs: 0000 {} => 0002 {rcx}
/--* t28 ref
Generating: N042 (???,???) [000039] ----------- t39 = * PUTARG_REG ref REG rcx
GC regs: 0002 {rcx} => 0000 {}
GC regs: 0000 {} => 0002 {rcx}
Generating: N044 (???,???) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t40 long
Generating: N046 (???,???) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 int arg1 rdx
+--* t39 ref arg0 rcx
+--* t41 long control expr
Generating: N048 (???,???) [000006] --CXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA
GC regs: 0002 {rcx} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0009: call [Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)]
Variable Live Range History Dump for BB03
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
=============== Generating BB04 [0003] [013..022) (return), preds={BB03,BB06} succs={} flags=0x00000000.02001011: i LIR label hascall
BB04 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB04:
Saved:
G_M62292_IG04: ; offs=0x000023, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
Created:
G_M62292_IG05: ; offs=0x000036, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Label: G_M62292_IG05, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB04, IL range [013..022)
Generating: N052 (???,???) [000024] H----+----- t24 = CNS_INT(h) long 0x7ff7f15423c4 bbc REG rcx
Mapped BB04 to G_M62292_IG05
IN000a: mov rcx, 0x7FF7F15423C4
/--* t24 long
Generating: N054 (???,???) [000042] ----------- t42 = * PUTARG_REG long REG rcx
/--* t42 long arg0 rcx
Generating: N056 (???,???) [000025] --CXG+----- u25 = * CALL help int CORINFO_HELP_COUNTPROFILE32 REG rax
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN000b: call CORINFO_HELP_COUNTPROFILE32
Added IP mapping: 0x0013 STACK_EMPTY (G_M62292_IG05,ins#2,ofs#15) label
Generating: N058 (???,???) [000036] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
Generating: N060 (???,???) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 rax REG rax
IN000c: mov rax, bword ptr [V00 rbp+0x10]
Byref regs: 0000 {} => 0001 {rax}
/--* t8 byref
Generating: N062 (???,???) [000029] DA---+----- * STORE_LCL_VAR long V03 tmp1 NA REG NA
Byref regs: 0001 {rax} => 0000 {}
IN000d: mov qword ptr [V03 rbp-0x08], rax
Generating: N064 (???,???) [000030] -----+----- t30 = LCL_VAR long V03 tmp1 rax REG rax
IN000e: mov rax, qword ptr [V03 rbp-0x08]
Generating: N066 (???,???) [000010] -c---+----- t10 = LCL_VAR int V01 arg1 NA REG NA
/--* t10 int
Generating: N068 (???,???) [000011] -----+----- t11 = * CAST long <- int REG rcx
IN000f: movsxd rcx, dword ptr [V01 rbp+0x18]
/--* t30 long
+--* t11 long
Generating: N070 (???,???) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
Generating: N072 (???,???) [000016] -A-XG+----- t16 = * IND float REG mm0
IN0010: vmovss xmm0, dword ptr [rax+4*rcx]
/--* t16 float
Generating: N074 (???,???) [000017] -A-XG+----- * RETURN float REG NA
Added IP mapping: EPILOG (G_M62292_IG05,ins#7,ofs#36) label
Reserving epilog IG for block BB04
Saved:
G_M62292_IG05: ; offs=0x000036, size=0x0024, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
Created:
G_M62292_IG06: ; offs=0x00005A, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Created:
G_M62292_IG07: ; offs=0x00015A, size=0x0000, bbWeight=1, gcrefRegs=0000 {}, epilog
*************** After placeholder IG creation
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62292_IG02: ; offs=0x000000, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref
G_M62292_IG03: ; offs=0x000014, size=0x000F, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0004], byref
G_M62292_IG04: ; offs=0x000023, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
G_M62292_IG05: ; offs=0x000036, size=0x0024, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
G_M62292_IG06: ; epilog placeholder, next placeholder=<END>, BB04 [0003], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
G_M62292_IG07: ; offs=0x00015A, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Current IG
Variable Live Range History Dump for BB04
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), ...]
=============== Generating BB06 [0005] [???..???) -> BB04(1) (always), preds={BB02} succs={BB04} flags=0x00000000.02001031: i LIR internal label hascall
BB06 IN (0)={}
OUT(0)={}
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB06:
Label: G_M62292_IG07, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB06, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP (G_M62292_IG07,ins#0,ofs#0) label
Generating: N078 (???,???) [000026] H----+----- t26 = CNS_INT(h) long 0x7ff7f15423c8 bbc REG rcx
Mapped BB06 to G_M62292_IG07
IN0011: mov rcx, 0x7FF7F15423C8
/--* t26 long
Generating: N080 (???,???) [000043] ----------- t43 = * PUTARG_REG long REG rcx
/--* t43 long arg0 rcx
Generating: N082 (???,???) [000027] --CXG+----- u27 = * CALL help int CORINFO_HELP_COUNTPROFILE32 REG rax
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0012: call CORINFO_HELP_COUNTPROFILE32
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Scope info: ignoring block end
IN0013: jmp L_M62292_BB04
Variable Live Range History Dump for BB06
V00 arg0: rbp[16] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), (G_M62292_IG07,ins#2,ofs#15)]
V01 arg1: rbp[24] (1 slot) [(G_M62292_IG02,ins#0,ofs#0), (G_M62292_IG07,ins#2,ofs#15)]
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = -572662307, compSizeEstimate = -572662307 Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) byref -> [rbp+0x10] do-not-enreg[] ld-addr-op
; V01 arg1 [V01 ] ( 1, 1 ) int -> [rbp+0x18] do-not-enreg[]
; V02 OutArgs [V02 ] ( 1, 1 ) struct (32) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <UNNAMED>
; V03 tmp1 [V03 ] ( 1, 1 ) long -> [rbp-0x08] do-not-enreg[] "Cast away GC"
;
; Lcl frame size = 48
*************** Before prolog / epilog generation
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62292_IG02: ; offs=0x000000, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref
G_M62292_IG03: ; offs=0x000014, size=0x000F, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0004], byref
G_M62292_IG04: ; offs=0x000023, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
G_M62292_IG05: ; offs=0x000036, size=0x0024, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
G_M62292_IG06: ; epilog placeholder, next placeholder=<END>, BB04 [0003], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
G_M62292_IG07: ; offs=0x00015A, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {}, BB06 [0005] <-- Current IG
Saved:
G_M62292_IG07: ; offs=0x00015A, size=0x0014, bbWeight=0.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB06 [0005], gcvars, byref
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M62292_IG01,ins#0,ofs#0) label
__prolog:
Debug: New V00 debug range: first
Debug: New V01 debug range: first
IN0014: push rbp
IN0015: sub rsp, 48
IN0016: lea rbp, [rsp+0x30]
*************** In genHomeRegisterParams()
IN0017: mov bword ptr [V00 rbp+0x10], rcx
IN0018: mov dword ptr [V01 rbp+0x18], edx
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Saved:
G_M62292_IG01: ; offs=0x000000, size=0x0011, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
IN0019: add rsp, 48
IN001a: pop rbp
IN001b: ret
Saved:
G_M62292_IG06: ; offs=0x00005A, size=0x0006, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0011, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M62292_IG02: ; offs=0x000011, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref
G_M62292_IG03: ; offs=0x000025, size=0x000F, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0004], byref
G_M62292_IG04: ; offs=0x000034, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
G_M62292_IG05: ; offs=0x000047, size=0x0024, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
G_M62292_IG06: ; offs=0x00006B, size=0x0006, bbWeight=1, epilog, nogc, extend
G_M62292_IG07: ; offs=0x000071, size=0x0014, bbWeight=0.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB06 [0005], gcvars, byref
*************** In emitRemoveJumpToNextInst()
Emitter Jump List:
IG02 IN0002 jg[6] -> IG04
IG02 IN0004 jge[6] -> IG07
IG07 IN0013 jmp[5] -> IG05 ; removal candidate ; after call before epilog
total jump count: 3
IG07 IN0013 does not jump to the next instruction group, keeping.
emitRemoveJumpToNextInst removed no unconditional jumps
*************** In emitJumpDistBind()
Emitter Jump List:
IG02 IN0002 jg[6] -> IG04
IG02 IN0004 jge[6] -> IG07
IG07 IN0013 jmp[5] -> IG05 ; after call before epilog
total jump count: 3
Binding: IN0002: 000000 jg L_M62292_BB03
Binding L_M62292_BB03 to G_M62292_IG04
Estimate of fwd jump [62036DC4/002]: 0015 -> 0034 = 001D
Shrinking jump [62036DC4/002]
Binding: IN0004: 000000 jge L_M62292_BB06
Binding L_M62292_BB06 to G_M62292_IG07
Estimate of fwd jump [62036E14/004]: 001B -> 006D = 0050
Shrinking jump [62036E14/004]
Adjusted offset of BB03 from 0025 to 001D
Adjusted offset of BB04 from 0034 to 002C
Adjusted offset of BB05 from 0047 to 003F
Adjusted offset of BB06 from 006B to 0063
Adjusted offset of BB07 from 0071 to 0069
Binding: IN0013: 000000 jmp L_M62292_BB04
Binding L_M62292_BB04 to G_M62292_IG05
Estimate of bwd jump [62037CAC/019]: 0078 -> 003F = 003B
Shrinking jump [62037CAC/019]
Total shrinkage = 11, min extra jump size = 4294967295
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x7A bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x8)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M62292_IG01: ; offs=0x000000, size=0x0011, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0014: 000000 push rbp
IN0015: 000001 sub rsp, 48
IN0016: 000005 lea rbp, [rsp+0x30]
IN0017: 00000A mov bword ptr [rbp+0x10], rcx
IN0018: 00000E mov dword ptr [rbp+0x18], edx
;; size=17 bbWeight=1 PerfScore 3.75
G_M62292_IG02: ; offs=0x000011, size=0x000C, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref, isz
IN0001: 000011 cmp dword ptr [rbp+0x18], 1
IN0002: 000015 jg SHORT G_M62292_IG04
IN0003: 000017 cmp dword ptr [rbp+0x18], 0
IN0004: 00001B jge SHORT G_M62292_IG07
;; size=12 bbWeight=1 PerfScore 6.00
G_M62292_IG03: ; offs=0x00001D, size=0x000F, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0004], byref
IN0005: 00001D mov rcx, 0x7FF7F15423C0
recordRelocation: 00007FF7F08ED678 (rw: 0000023061EA1450) => 00007FF84FFB1810, type 16 (IMAGE_REL_BASED_REL32), delta 0
; Call at 0027 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0006: 000027 call CORINFO_HELP_COUNTPROFILE32
;; size=15 bbWeight=0.50 PerfScore 0.62
G_M62292_IG04: ; offs=0x00002C, size=0x0013, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
IN0007: 00002C mov edx, dword ptr [rbp+0x18]
IN0008: 00002F mov rcx, 0x230618FF1E8 ; 'You tried to access this vector at index: {0}'
; gcrRegs +[rcx]
recordRelocation: 00007FF7F08ED68B (rw: 0000023061EA1463) => 00007FF7F13342A0, type 16 (IMAGE_REL_BASED_DISP32), delta 0
; Call at 0039 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0009: 000039 call [Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)]
; gcrRegs -[rcx]
;; size=19 bbWeight=1 PerfScore 4.25
G_M62292_IG05: ; offs=0x00003F, size=0x0024, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
IN000a: 00003F mov rcx, 0x7FF7F15423C4
recordRelocation: 00007FF7F08ED69A (rw: 0000023061EA1472) => 00007FF84FFB1810, type 16 (IMAGE_REL_BASED_REL32), delta 0
; Call at 0049 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN000b: 000049 call CORINFO_HELP_COUNTPROFILE32
IN000c: 00004E mov rax, bword ptr [rbp+0x10]
; byrRegs +[rax]
IN000d: 000052 mov qword ptr [rbp-0x08], rax
IN000e: 000056 mov rax, qword ptr [rbp-0x08]
; byrRegs -[rax]
IN000f: 00005A movsxd rcx, dword ptr [rbp+0x18]
IN0010: 00005E vmovss xmm0, dword ptr [rax+4*rcx]
;; size=36 bbWeight=1 PerfScore 11.25
G_M62292_IG06: ; offs=0x000063, size=0x0006, bbWeight=1, epilog, nogc, extend
IN0019: 000063 add rsp, 48
IN001a: 000067 pop rbp
IN001b: 000068 ret
;; size=6 bbWeight=1 PerfScore 1.75
G_M62292_IG07: ; offs=0x000069, size=0x0011, bbWeight=0.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB06 [0005], gcvars, byref, isz
IN0011: 000069 mov rcx, 0x7FF7F15423C8
recordRelocation: 00007FF7F08ED6C4 (rw: 0000023061EA149C) => 00007FF84FFB1810, type 16 (IMAGE_REL_BASED_REL32), delta 0
; Call at 0073 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0012: 000073 call CORINFO_HELP_COUNTPROFILE32
IN0013: 000078 jmp SHORT G_M62292_IG05
;; size=17 bbWeight=0.50 PerfScore 1.62
Allocated method code size = 122 , actual size = 122, unused size = 0
; Total bytes of code 122, prolog size 10, PerfScore 29.25, instruction count 27, allocated bytes for code 122 (MethodHash=2b4c0cab) for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float (Instrumented Tier0)
; ============================================================
*************** After end code gen, before unwindEmit()
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0011, bbWeight=1, PerfScore 3.75, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0014: 000000 push rbp
IN0015: 000001 sub rsp, 48
IN0016: 000005 lea rbp, [rsp+0x30]
IN0017: 00000A mov bword ptr [V00 rbp+0x10], rcx
IN0018: 00000E mov dword ptr [V01 rbp+0x18], edx
G_M62292_IG02: ; offs=0x000011, size=0x000C, bbWeight=1, PerfScore 6.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], byref, isz
IN0001: 000011 cmp dword ptr [V01 rbp+0x18], 1
IN0002: 000015 jg SHORT G_M62292_IG04
IN0003: 000017 cmp dword ptr [V01 rbp+0x18], 0
IN0004: 00001B jge SHORT G_M62292_IG07
G_M62292_IG03: ; offs=0x00001D, size=0x000F, bbWeight=0.50, PerfScore 0.62, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB05 [0004], byref
IN0005: 00001D mov rcx, 0x7FF7F15423C0
IN0006: 000027 call CORINFO_HELP_COUNTPROFILE32
G_M62292_IG04: ; offs=0x00002C, size=0x0013, bbWeight=1, PerfScore 4.25, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], byref
IN0007: 00002C mov edx, dword ptr [V01 rbp+0x18]
IN0008: 00002F mov rcx, 0x230618FF1E8 ; 'You tried to access this vector at index: {0}'
IN0009: 000039 call [Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)]
G_M62292_IG05: ; offs=0x00003F, size=0x0024, bbWeight=1, PerfScore 11.25, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], byref
IN000a: 00003F mov rcx, 0x7FF7F15423C4
IN000b: 000049 call CORINFO_HELP_COUNTPROFILE32
IN000c: 00004E mov rax, bword ptr [V00 rbp+0x10]
IN000d: 000052 mov qword ptr [V03 rbp-0x08], rax
IN000e: 000056 mov rax, qword ptr [V03 rbp-0x08]
IN000f: 00005A movsxd rcx, dword ptr [V01 rbp+0x18]
IN0010: 00005E vmovss xmm0, dword ptr [rax+4*rcx]
G_M62292_IG06: ; offs=0x000063, size=0x0006, bbWeight=1, PerfScore 1.75, epilog, nogc, extend
IN0019: 000063 add rsp, 48
IN001a: 000067 pop rbp
IN001b: 000068 ret
G_M62292_IG07: ; offs=0x000069, size=0x0011, bbWeight=0.50, PerfScore 1.62, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB06 [0005], gcvars, byref, isz
IN0011: 000069 mov rcx, 0x7FF7F15423C8
IN0012: 000073 call CORINFO_HELP_COUNTPROFILE32
IN0013: 000078 jmp SHORT G_M62292_IG05
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x00007a (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x05
CountOfUnwindCodes: 2
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 5 * 8 + 8 = 48 = 0x30
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x00007FF7F08ED650, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x7a, unwindSize=0x8, pUnwindBlock=0x000002306202F070, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 8
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000011 ( STACK_EMPTY )
IL offs 0x0004 : 0x00000017 ( STACK_EMPTY )
IL offs NO_MAP : 0x0000001D ( STACK_EMPTY )
IL offs 0x0008 : 0x0000002C ( STACK_EMPTY )
IL offs 0x0013 : 0x0000004E ( STACK_EMPTY )
IL offs EPILOG : 0x00000063 ( STACK_EMPTY )
IL offs NO_MAP : 0x00000069 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 4
; Variable debug info: 4 live ranges, 2 vars for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
(V00 arg0) : From 00000000h to 00000011h, in rcx
(V00 arg0) : From 00000011h to 00000078h, in rbp[16] (1 slot)
(V01 arg1) : From 00000000h to 00000011h, in rdx
(V01 arg1) : From 00000011h to 00000078h, in rbp[24] (1 slot)
*************** In gcInfoBlockHdrSave()
Set code length to 122.
Set stack base register to rbp.
Set Outgoing stack arg area size to 32.
Stack slot id for offset 16 (0x10) (frame) (byref, untracked) = 0.
Defining 0 call sites:
*************** Finishing PHASE Emit GC+EH tables
Method code size: 122
Allocations for Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float (MethodHash=2b4c0cab)
count: 666, size: 65636, max = 7576
allocateMemory: 131072, nraUsed: 69800
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
ABI | 0 | 0.00%
AssertionProp | 0 | 0.00%
ASTNode | 7040 | 10.73%
InstDesc | 4696 | 7.15%
ImpStack | 384 | 0.59%
BasicBlock | 2280 | 3.47%
CallArgs | 400 | 0.61%
FlowEdge | 280 | 0.43%
DepthFirstSearch | 72 | 0.11%
Loops | 0 | 0.00%
TreeStatementList | 0 | 0.00%
SiScope | 0 | 0.00%
DominatorMemory | 0 | 0.00%
LSRA | 9624 | 14.66%
LSRA_Interval | 1632 | 2.49%
LSRA_RefPosition | 4880 | 7.43%
Reachability | 0 | 0.00%
SSA | 0 | 0.00%
ValueNumber | 0 | 0.00%
LvaTable | 1584 | 2.41%
UnwindInfo | 0 | 0.00%
hashBv | 128 | 0.20%
bitset | 32 | 0.05%
FixedBitVect | 24 | 0.04%
Generic | 968 | 1.47%
LocalAddressVisitor | 0 | 0.00%
FieldSeqStore | 0 | 0.00%
MemorySsaMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 0 | 0.00%
GC | 1444 | 2.20%
CorTailCallInfo | 0 | 0.00%
Inlining | 272 | 0.41%
ArrayStack | 0 | 0.00%
DebugInfo | 464 | 0.71%
DebugOnly | 25166 | 38.34%
Codegen | 2720 | 4.14%
LoopOpt | 0 | 0.00%
LoopClone | 0 | 0.00%
LoopUnroll | 0 | 0.00%
LoopHoist | 0 | 0.00%
LoopIVOpts | 0 | 0.00%
Unknown | 90 | 0.14%
RangeCheck | 0 | 0.00%
CopyProp | 0 | 0.00%
Promotion | 120 | 0.18%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 648 | 0.99%
ClassLayout | 200 | 0.30%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 0 | 0.00%
Pgo | 488 | 0.74%
MaskConversionOpt | 0 | 0.00%
TryRegionClone | 0 | 0.00%
Async | 0 | 0.00%
RangeCheckCloning | 0 | 0.00%
Final metrics:
ActualCodeBytes : 122
AllocatedHotCodeBytes : 122
AllocatedColdCodeBytes : 0
ReadOnlyDataBytes : 0
GCInfoBytes : 4
EHClauseCount : 0
PhysicallyPromotedFields : 0
LoopsFoundDuringOpts : 0
LoopsInverted : 0
LoopsCloned : 0
LoopsUnrolled : 0
LoopAlignmentCandidates : 0
LoopsAligned : 0
LoopsIVWidened : 0
WidenedIVs : 0
UnusedIVsRemoved : 0
LoopsMadeDownwardsCounted : 0
LoopsStrengthReduced : 0
VarsInSsa : 0
HoistedExpressions : 0
RedundantBranchesEliminated : 0
JumpThreadingsPerformed : 0
CseCount : 0
BasicBlocksAtCodegen : 6
PerfScore : 29.250000
BytesAllocated : 69800
ImporterBranchFold : 0
ImporterSwitchFold : 0
DevirtualizedCall : 0
DevirtualizedCallUnboxedEntry : 0
DevirtualizedCallRemovedBox : 0
GDV : 0
ClassGDV : 0
MethodGDV : 0
MultiGuessGDV : 0
ChainedGDV : 0
EnumeratorGDV : 0
InlinerBranchFold : 0
InlineAttempt : 0
InlineCount : 0
ProfileConsistentBeforeInline : 0
ProfileConsistentAfterInline : 0
ProfileConsistentBeforeMorph : 0
ProfileConsistentAfterMorph : 0
ProfileSynthesizedBlendedOrRepaired : 0
ProfileInconsistentInitially : 0
ProfileInconsistentResetLeave : 0
ProfileInconsistentImporterBranchFold : 0
ProfileInconsistentImporterSwitchFold : 0
ProfileInconsistentChainedGDV : 0
ProfileInconsistentScratchBB : 0
ProfileInconsistentInlinerBranchFold : 0
ProfileInconsistentInlineeScale : 0
ProfileInconsistentInlinee : 0
ProfileInconsistentNoReturnInlinee : 0
ProfileInconsistentMayThrowInlinee : 0
NewRefClassHelperCalls : 0
StackAllocatedRefClasses : 0
NewBoxedValueClassHelperCalls : 0
StackAllocatedBoxedValueClasses : 0
NewArrayHelperCalls : 0
StackAllocatedArrays : 0
LocalAssertionCount : 0
LocalAssertionOverflow : 0
MorphTrackedLocals : 0
MorphLocals : 0
EnumeratorGDVProvisionalNoEscape : 0
EnumeratorGDVCanCloneToEnsureNoEscape : 0
****** DONE compiling Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
****** START compiling Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float (MethodHash=2b4c0cab)
Generating code for Windows x64
OPTIONS: Tier-1 compilation
OPTIONS: compCodeOpt = FAST_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: optimizer should use profile data
IL to import:
IL_0000 03 ldarg.1
IL_0001 17 ldc.i4.1
IL_0002 30 04 bgt.s 4 (IL_0008)
IL_0004 03 ldarg.1
IL_0005 16 ldc.i4.0
IL_0006 2f 0b bge.s 11 (IL_0013)
IL_0008 72 01 00 00 70 ldstr 0x70000001
IL_000d 03 ldarg.1
IL_000e 28 01 00 00 2b call 0x2B000001
IL_0013 0f 00 ldarga.s 0x0
IL_0015 7c f8 01 00 04 ldflda 0x40001F8
IL_001a e0 conv.u
IL_001b 03 ldarg.1
IL_001c d3 conv.i
IL_001d 1a ldc.i4.4
IL_001e 5a mul
IL_001f 58 add
IL_0020 4e ldind.r4
IL_0021 2a ret
1 return registers for return type float
[00..04) reg mm0
Parameter V00 ABI info: [00..08) reg rcx (implicit by-ref)
Parameter V01 ABI info: [00..04) reg rdx
lvaGrabTemp returning 2 (V02 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
Local V02 should not be enregistered because: it is address exposed
; Initial local variable assignments
;
; V00 arg0 struct <Program.EntryPoint+Vector2, 12> <Program.EntryPoint+Vector2>
; V01 arg1 int
; V02 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
*************** In compInitDebuggingInfo() for Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 2
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 022h
1: 01h 01h V01 arg1 000h 022h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
Jump targets:
IL_0008
IL_0013
New Basic Block BB01 [0000] created.
BB01 [0000] [000..004)
New Basic Block BB02 [0001] created.
BB02 [0001] [004..008)
New Basic Block BB03 [0002] created.
BB03 [0002] [008..013)
New Basic Block BB04 [0003] created.
BB04 [0003] [013..022)
setting likelihood of BB01 -> BB03 to 0.5
setting likelihood of BB01 -> BB02 to 0.5
setting likelihood of BB02 -> BB04 to 0.5
setting likelihood of BB02 -> BB03 to 0.5
setting likelihood of BB03 -> BB04 to 1
IL Code Size,Instr 34, 19, Basic Block count 4, Local Variable Num,Ref count 3, 5 for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond )
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond )
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always)
BB04 [0003] 2 BB02,BB03 1 [013..022) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
Trees after Pre-import
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03(0.5),BB02(0.5) ( cond )
BB02 [0001] 1 BB01 1 [004..008)-> BB04(0.5),BB03(0.5) ( cond )
BB03 [0002] 2 BB01,BB02 1 [008..013)-> BB04(1) (always)
BB04 [0003] 2 BB02,BB03 1 [013..022) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03}
------------ BB02 [0001] [004..008) -> BB04(0.5),BB03(0.5) (cond), preds={BB01} succs={BB03,BB04}
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Profile incorporation
Have Dynamic PGO: 3 schema records (schema at 00000230620B1EA0, data at 00000230620B1EE8)
Profile summary: 1 runs, 0 block probes, 3 edge probes, 0 class profiles, 0 method profiles, 0 other records
Reconstructing block counts from sparse edge instrumentation
... adding known edge BB02 -> BB03: weight 0
... adding known edge BB04 -> BB01: weight 2
... adding known edge BB02 -> BB04: weight 2
... unknown edge BB01 -> BB02
... unknown edge BB01 -> BB03
... unknown edge BB03 -> BB04
... pseudo edge BB04 -> BB01
... known edge BB02 -> BB04
... known edge BB02 -> BB03
Solver: 4 blocks, 4 unknown; 6 edges, 3 unknown, 0 zero
Pass [1]: 4 unknown blocks, 3 unknown edges
BB04: 1 incoming unknown, 0 outgoing unknown
BB04: all outgoing edge weights known, summing...
BB04 -> BB01 has weight 2
BB04: all outgoing edge weights known, sum is 2
BB03 -> BB04: target block weight and all other incoming edge weights known, so weight is 0
BB03: 1 incoming unknown, 0 outgoing unknown
BB03: all outgoing edge weights known, summing...
BB03 -> BB04 has weight 0
BB03: all outgoing edge weights known, sum is 0
BB01 -> BB03: target block weight and all other incoming edge weights known, so weight is 0
BB02: 1 incoming unknown, 0 outgoing unknown
BB02: all outgoing edge weights known, summing...
BB02 -> BB03 has weight 0
BB02 -> BB04 has weight 2
BB02: all outgoing edge weights known, sum is 2
BB01 -> BB02: target block weight and all other incoming edge weights known, so weight is 2
BB01: 0 incoming unknown, 0 outgoing unknown
BB01: all incoming edge weights known, summing...
BB04 -> BB01 has weight 2
BB01: all incoming edge weights known, sum is 2
Solver: converged in 1 passes
Normalizing successor likelihoods with factor 1/2
Setting likelihood of BB01 -> BB03 to 0 (pgo)
setting likelihood of BB01 -> BB03 from 0.5 to 0
Setting likelihood of BB01 -> BB02 to 1 (pgo)
setting likelihood of BB01 -> BB02 from 0.5 to 1
Normalizing successor likelihoods with factor 1/2
Setting likelihood of BB02 -> BB03 to 0 (pgo)
setting likelihood of BB02 -> BB03 from 0.5 to 0
Setting likelihood of BB02 -> BB04 to 1 (pgo)
setting likelihood of BB02 -> BB04 from 0.5 to 1
BB03 has zero weight , setting outgoing likelihoods heuristically
Setting likelihood of BB03 -> BB04 to 1 (heur)
setting likelihood of BB03 -> BB04 from 1 to 1
Repairing profile...
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 3]
01 -> BB02[1, 2]
02 -> BB03[2, 1]
03 -> BB04[3, 0]
Flow graph has no cycles; skipping identification of natural loops
Repairing inconsistent or missing edge likelihoods
setting likelihood of BB03 -> BB04 from 1 to 1
Synthesis: entry BB01 has input weight 2
Synthesis: exception weight 1e-05
Computing block weights
Synthesis solver: flow graph has 0 improper loop headers
converged at iteration 0 rel residual 2e+12 eigenvalue 0
fgCalledCount is 2
Checking Profile Weights (flags:0x24)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Finishing PHASE Profile incorporation
Trees after Profile incorporation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013)-> BB04(1) (always) IBC rare
BB04 [0003] 2 BB02,BB03 1 2 [013..022) (return) IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Canonicalize entry
*************** Finishing PHASE Canonicalize entry [no changes]
*************** Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 0 (0x000) ldarg.1
[ 1] 1 (0x001) ldc.i4.1 1
[ 2] 2 (0x002) bgt.s
STMT00000 ( 0x000[E-] ... ??? )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB03 (PC=008) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 8 (0x008) ldstr 70000001
[ 1] 13 (0x00d) ldarg.1
[ 2] 14 (0x00e) call 2B000001
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
CheckCanInline: fetching method info for inline candidate ThrowOutOfRangeException -- context 00007FF7F132C8B8
Method context: Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
Callee and root has trusted profile
INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float' calling 'Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)'
INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success'
STMT00001 ( 0x008[E-] ... ??? )
[000006] I-C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) (exactContextHandle=0x00007FF7F132C8B8)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
impImportBlockPending for BB04
Importing BB04 (PC=019) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 19 (0x013) ldarga.s 0
[ 1] 21 (0x015) ldflda 040001F8
[ 1] 26 (0x01a) conv.u
[ 1] 27 (0x01b) ldarg.1
[ 2] 28 (0x01c) conv.i
[ 2] 29 (0x01d) ldc.i4.4 4
[ 3] 30 (0x01e) mul
Folding long operator with constant nodes into a constant:
[000013] ----------- * CAST long <- int
[000012] ----------- \--* CNS_INT int 4
Bashed to long constant:
[000013] ----------- * CNS_INT long 4
[ 2] 31 (0x01f) add
[ 1] 32 (0x020) ldind.r4
[ 1] 33 (0x021) ret
STMT00002 ( 0x013[E-] ... ??? )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CNS_INT long 4
Importing BB02 (PC=004) of 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float'
[ 0] 4 (0x004) ldarg.1
[ 1] 5 (0x005) ldc.i4.0 0
[ 2] 6 (0x006) bge.s
STMT00003 ( 0x004[E-] ... ??? )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
impImportBlockPending for BB03
impImportBlockPending for BB04
*************** Finishing PHASE Importation
Trees after Importation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013)-> BB04(1) (always) i IBC rare
BB04 [0003] 2 BB02,BB03 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] I-C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) (exactContextHandle=0x00007FF7F132C8B8)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CNS_INT long 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import [no changes]
*************** Starting PHASE Save contexts around async calls
No async calls where execution context capture/restore is necessary
*************** Finishing PHASE Save contexts around async calls [no changes]
*************** Starting PHASE Morph - Init
*************** Finishing PHASE Morph - Init [no changes]
*************** Starting PHASE Morph - Inlining
INLINER: pgo source is Dynamic PGO; pgo data is consistent; trusted; sufficient
Expanding INLINE_CANDIDATE in statement STMT00001 in BB03:
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] I-C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) (exactContextHandle=0x00007FF7F132C8B8)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
IL argument #0: is a constant or invariant
[000004] ----------- * CNS_STR ref <string constant>
IL argument #1: is a local var
[000005] ----------- * LCL_VAR int V01 arg1
INLINER: inlineInfo.tokenLookupContextHandle for Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) set to 0x00007FF7F132C8B8:
Invoking compiler for the inlinee method Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) :
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 8c 5e 00 00 1b box 0x1B00005E
IL_0007 28 21 00 00 0a call 0xA000021
IL_000c 73 22 00 00 0a newobj 0xA000022
IL_0011 7a throw
INLINER impTokenLookupContextHandle for Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) is 0x00007FF7F132C8B8.
0 return registers for return type void
*************** In compInitDebuggingInfo() for Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
Callee and root has trusted profile
weight= 10 : state 3 [ ldarg.0 ]
weight= 16 : state 4 [ ldarg.1 ]
weight=247 : state 117 [ box ]
weight= 79 : state 40 [ call ]
weight=227 : state 103 [ newobj ]
weight=210 : state 108 [ throw ]
Inline candidate is generic and caller is not. Multiplier increased to 2.
Callsite passes a constant. Multiplier increased to 5.
Inline candidate callsite is rare. Multiplier limited to 1.3.
Callsite has profile data: 0. Multiplier limited to 0.39.
calleeNativeSizeEstimate=789
callsiteNativeSizeEstimate=115
benefit multiplier=0.39
threshold=44
Native estimate for function size exceeds threshold for inlining 78.9 > 4.4 (multiplier = 0.39)
Inline expansion aborted, inline not profitable
INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float' calling 'Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)'
INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline'
**************** Inline Tree
Inlines into 06000001 [via ExtendedDefaultPolicy] Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float:
[INL00 IL=-572662307 TR=000006 06000003] [FAILED: call site: unprofitable inline] Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[INL00 IL=0014 TR=000006 06000003] [FAILED: call site: unprofitable inline] Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
Budget: initialTime=162, finalTime=162, initialBudget=3240, currentBudget=3240
Budget: initialSize=906, finalSize=906
*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013)-> BB04(1) (always) i IBC rare
BB04 [0003] 2 BB02,BB03 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CNS_INT long 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Resolve GDV Checks
*************** Finishing PHASE Resolve GDV Checks [no changes]
*************** Starting PHASE DFS blocks and remove dead code 1
*************** Finishing PHASE DFS blocks and remove dead code 1 [no changes]
*************** Starting PHASE Allocate Objects
no newobjs or newarr in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013)-> BB04(1) (always) i IBC rare
BB04 [0003] 2 BB02,BB03 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks [no changes]
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty try/catch/fault
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try/catch/fault [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Head and tail merge
*************** Finishing PHASE Head and tail merge
Trees after Head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013)-> BB04(1) (always) i IBC rare
BB04 [0003] 2 BB02,BB03 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CNS_INT long 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks [no changes]
*************** Starting PHASE Update flow graph early pass
*************** Finishing PHASE Update flow graph early pass [no changes]
*************** Starting PHASE Morph - Promote Structs
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 struct <Program.EntryPoint+Vector2, 12> ld-addr-op <Program.EntryPoint+Vector2>
; V01 arg1 int
; V02 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
Promoting struct local V00 (Program.EntryPoint+Vector2):
lvaGrabTemp returning 3 (V03 tmp1) (a long lifetime temp) called for field V00.X (fldOffset=0x0).
lvaGrabTemp returning 4 (V04 tmp2) (a long lifetime temp) called for field V00.Y (fldOffset=0x4).
lvaGrabTemp returning 5 (V05 tmp3) (a long lifetime temp) called for field V00.Z (fldOffset=0x8).
struct promotion of V02 is disabled because it has already been marked DNER
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 struct <Program.EntryPoint+Vector2, 12> ld-addr-op <Program.EntryPoint+Vector2>
; V01 arg1 int
; V02 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
; V03 tmp1 float "field V00.X (fldOffset=0x0)" P-INDEP
; V04 tmp2 float "field V00.Y (fldOffset=0x4)" P-INDEP
; V05 tmp3 float "field V00.Z (fldOffset=0x8)" P-INDEP
*************** Finishing PHASE Morph - Promote Structs
Trees after Morph - Promote Structs
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013)-> BB04(1) (always) i IBC rare
BB04 [0003] 2 BB02,BB03 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
| * float field V00.X (fldOffset=0x0) -> V03 tmp1
| * float field V00.Y (fldOffset=0x4) -> V04 tmp2
| * float field V00.Z (fldOffset=0x8) -> V05 tmp3
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CNS_INT long 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE DFS blocks and remove dead code 2
*************** Finishing PHASE DFS blocks and remove dead code 2 [no changes]
*************** Starting PHASE Morph - Structs/AddrExp
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 3]
01 -> BB02[1, 2]
02 -> BB03[2, 1]
03 -> BB04[3, 0]
Flow graph has no cycles; skipping identification of natural loops
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
LocalAddressVisitor visiting statement:
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* FIELD_ADDR byref Program.EntryPoint+Vector2:X
[000007] ----------- | \--* LCL_ADDR byref V00 arg0 [+0]
| * float field V00.X (fldOffset=0x0) -> V03 tmp1
| * float field V00.Y (fldOffset=0x4) -> V04 tmp2
| * float field V00.Z (fldOffset=0x8) -> V05 tmp3
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CNS_INT long 4
Replacing the field in promoted struct with local var V03
On exposed: V00
LocalAddressVisitor modified statement:
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V03 tmp1 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CNS_INT long 4
Local V03 should not be enregistered because: it is address exposed
Local V04 should not be enregistered because: it is address exposed
Local V05 should not be enregistered because: it is address exposed
Local V00 should not be enregistered because: it is address exposed
*************** Finishing PHASE Morph - Structs/AddrExp
Trees after Morph - Structs/AddrExp
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013)-> BB04(1) (always) i IBC rare
BB04 [0003] 2 BB02,BB03 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V03 tmp1 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1
[000013] ----------- \--* CNS_INT long 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Optimize mask conversions
Skipping. There are no converts of locals
*************** Finishing PHASE Optimize mask conversions [no changes]
*************** Starting PHASE Early liveness
Local V02 should not be enregistered because: struct size does not match reg size
Local V03 should not be enregistered because: field of a dependently promoted struct
Local V04 should not be enregistered because: field of a dependently promoted struct
Local V05 should not be enregistered because: field of a dependently promoted struct
Tracked variable (1 out of 6) table:
V01 arg1 [ int]: refCnt = 4, refCntWtd = 0
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V01}
DEF(0)={ }
BB02 USE(1)={V01}
DEF(0)={ }
BB03 USE(1)={V01}
DEF(0)={ }
BB04 USE(1)={V01} + ByrefExposed
DEF(0)={ }
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V01} + ByrefExposed
OUT(1)={V01} + ByrefExposed
BB02 IN (1)={V01} + ByrefExposed
OUT(1)={V01} + ByrefExposed
BB03 IN (1)={V01} + ByrefExposed
OUT(1)={V01} + ByrefExposed
BB04 IN (1)={V01} + ByrefExposed
OUT(0)={ }
*************** Finishing PHASE Early liveness
Trees after Early liveness
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013)-> BB04(1) (always) i IBC rare
BB04 [0003] 2 BB02,BB03 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V03 tmp1 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1 (last use)
[000013] ----------- \--* CNS_INT long 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Forward Substitution
===> BB01
===> BB02
===> BB03
===> BB04
*************** Finishing PHASE Forward Substitution [no changes]
*************** Starting PHASE Physical promotion
*************** Finishing PHASE Physical promotion [no changes]
*************** Starting PHASE Identify candidates for implicit byref copy omission
*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]
*************** Starting PHASE Morph - ByRefs
lvaGrabTemp returning 6 (V06 tmp4) (a long lifetime temp) called for Promoted implicit byref.
Undoing promotion of implicit by-ref V00: dependent; total: 1 non-call: 1 fields: 3
Changing the lvType for struct parameter V00 to TYP_BYREF.
*************** Finishing PHASE Morph - ByRefs
Trees after Morph - ByRefs
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013)-> BB04(1) (always) i IBC rare
BB04 [0003] 2 BB02,BB03 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) -> BB04(1) (always), preds={BB01,BB02} succs={BB04}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02,BB03} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V03 tmp1 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1 (last use)
[000013] ----------- \--* CNS_INT long 4
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Morph - Global
Cross-block table size 64 (for 1 tracked locals)
Morphing BB01
BB01 ineligible for cross-block
Assertions in: #NA
fgMorphTree BB01, STMT00000 (before)
[000003] ----------- * JTRUE void
[000002] ----------- \--* GT int
[000000] ----------- +--* LCL_VAR int V01 arg1
[000001] ----------- \--* CNS_INT int 1
Morphing BB02
Using `if false` assertions from pred BB01
Assertions in: #NA
fgMorphTree BB02, STMT00003 (before)
[000021] ----------- * JTRUE void
[000020] ----------- \--* GE int
[000018] ----------- +--* LCL_VAR int V01 arg1
[000019] ----------- \--* CNS_INT int 0
Morphing BB03
Using `if true` assertions from pred BB01
Using `if false` assertions from pred BB02
Assertions in: #NA
fgMorphTree BB03, STMT00001 (before)
[000006] --C-G------ * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000004] ----------- arg0 +--* CNS_STR ref <string constant>
[000005] ----------- arg1 \--* LCL_VAR int V01 arg1
Adding final args and determining ABI info for [000006]:
Argument 0 ABI info: [00..08) reg rcx
Argument 1 ABI info: [00..04) reg rdx
Args for call [000006] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000004].CNS_STR ref (By value), 1 segments: <[00..08) reg rcx>]
CallArg[[000005].LCL_VAR int (By value), 1 segments: <[00..04) reg rdx>]
Morphing args for 6.CALL:
Adding final args and determining ABI info for [000024]:
Argument 0 ABI info: [00..04) reg rcx
Argument 1 ABI info: [00..08) reg rdx
Args for call [000024] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000023].CNS_INT int (By value), 1 segments: <[00..04) reg rcx>]
CallArg[[000022].CNS_INT long (By value), 1 segments: <[00..08) reg rdx>]
Morphing args for 24.CALL:
Sorting the arguments:
Deferred argument:
[000023] -----+----- * CNS_INT int 1
Moved to late list
Deferred argument:
[000022] H----+----- * CNS_INT(h) long 0x7ff7f1188938 scope
Moved to late list
Register placement order: rcx rdx
Args for [000024].CALL after fgMorphArgs:
CallArg[[000023].CNS_INT int (By value), 1 segments: <[00..04) reg rcx>, processed]
CallArg[[000022].CNS_INT long (By value), 1 segments: <[00..08) reg rdx>, processed]
OutgoingArgsStackSize is 32
Sorting the arguments:
Argument with 'side effect'...
[000024] --C-G+----- * CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx +--* CNS_INT int 1
[000022] H----+----- arg1 rdx \--* CNS_INT(h) long 0x7ff7f1188938 scope
lvaGrabTemp returning 7 (V07 tmp5) called for argument with side effect.
Evaluate to a temp:
[000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5
[000024] --C-G+----- \--* CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx +--* CNS_INT int 1
[000022] H----+----- arg1 rdx \--* CNS_INT(h) long 0x7ff7f1188938 scope
Deferred argument:
[000005] -----+----- * LCL_VAR int V01 arg1
Moved to late list
Register placement order: rcx rdx
Args for [000006].CALL after fgMorphArgs:
CallArg[[000026].LCL_VAR ref (By value), 1 segments: <[00..08) reg rcx>, processed]
CallArg[[000005].LCL_VAR int (By value), 1 segments: <[00..04) reg rdx>, processed]
OutgoingArgsStackSize is 32
fgMorphTree BB03, STMT00001 (after)
[000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
[000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx | +--* CNS_INT int 1
[000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
[000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
[000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
Removing trees after no-return call [000006]
New final statement:
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
[000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx | +--* CNS_INT int 1
[000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
[000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
[000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
Converting BB03 to BBJ_THROW
Morphing BB04
Using `if true` assertions from pred BB02
Assertions in: #NA
fgMorphTree BB04, STMT00002 (before)
[000017] ---XG------ * RETURN float
[000016] ---XG------ \--* IND float
[000015] ----------- \--* ADD long
[000009] ---------U- +--* CAST long <- ulong <- byref
[000008] ----------- | \--* LCL_ADDR byref V03 tmp1 [+0]
[000014] ----------- \--* MUL long
[000011] ----------- +--* CAST long <- int
[000010] ----------- | \--* LCL_VAR int V01 arg1 (last use)
[000013] ----------- \--* CNS_INT long 4
lvaGrabTemp returning 8 (V08 tmp6) called for Cast away GC.
Rewriting an implicit by-ref parameter reference:
[000008] ----------- * LCL_ADDR byref V03 tmp1 [+0]
Transformed into:
[000008] ----------- * LCL_VAR byref V00 arg0
fgMorphTree BB04, STMT00002 (after)
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000030] -A---+----- +--* COMMA long
[000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000028] -----+----- | \--* LCL_VAR long V08 tmp6
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1 (last use)
[000013] -----+----- \--* CNS_INT long 2
morph assertion stats: 64 table size, 0 assertions, 0 dropped
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
[000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx | +--* CNS_INT int 1
[000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
[000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
[000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000030] -A---+----- +--* COMMA long
[000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000028] -----+----- | \--* LCL_VAR long V08 tmp6
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1 (last use)
[000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Post-Morph
*************** In fgMarkDemotedImplicitByRefArgs()
Clearing annotation for V00
Fixing pointer for field V03 from V00 to V06
Fixing pointer for field V04 from V00 to V06
Fixing pointer for field V05 from V00 to V06
*************** Finishing PHASE Post-Morph
Trees after Post-Morph
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
[000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx | +--* CNS_INT int 1
[000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
[000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
[000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000030] -A---+----- +--* COMMA long
[000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000028] -----+----- | \--* LCL_VAR long V08 tmp6
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie [no changes]
*************** Starting PHASE Compute block weights
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute block weights [no changes]
*************** Starting PHASE Remove empty finally 2
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 2 [no changes]
*************** Starting PHASE Remove empty try 2
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 2 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 2
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 2 [no changes]
*************** Starting PHASE Optimize control flow
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize control flow [no changes]
*************** Starting PHASE Post-morph head and tail merge
*************** Finishing PHASE Post-morph head and tail merge
Trees after Post-morph head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
[000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx | +--* CNS_INT int 1
[000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
[000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
[000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000030] -A---+----- +--* COMMA long
[000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000028] -----+----- | \--* LCL_VAR long V08 tmp6
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE DFS blocks and remove dead code 3
*************** Finishing PHASE DFS blocks and remove dead code 3 [no changes]
*************** Starting PHASE Adjust throw edge likelihoods
BB03 will throw.
*************** Finishing PHASE Adjust throw edge likelihoods
Trees after Adjust throw edge likelihoods
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
[000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx | +--* CNS_INT int 1
[000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
[000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
[000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000030] -A---+----- +--* COMMA long
[000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000028] -----+----- | \--* LCL_VAR long V08 tmp6
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Find loops
*************** In optFindLoopsPhase()
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 3]
01 -> BB02[1, 2]
02 -> BB04[3, 1]
03 -> BB03[2, 0]
Flow graph has no cycles; skipping identification of natural loops
*************** Finishing PHASE Find loops
Trees after Find loops
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
[000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx | +--* CNS_INT int 1
[000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
[000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
[000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000030] -A---+----- +--* COMMA long
[000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000028] -----+----- | \--* LCL_VAR long V08 tmp6
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Repair profile post-morph
Profile is already consistent.
*************** Finishing PHASE Repair profile post-morph [no changes]
*************** Starting PHASE Invert loops
*************** Finishing PHASE Invert loops [no changes]
*************** Starting PHASE Set block weights
*************** Finishing PHASE Set block weights [no changes]
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
No loops to clone
*************** Finishing PHASE Clone loops [no changes]
*************** Starting PHASE Unroll loops
*************** Finishing PHASE Unroll loops [no changes]
*************** Starting PHASE Compute dominators
After computing the dominance tree:
BB01 : BB02 BB03
BB02 : BB04
*************** Finishing PHASE Compute dominators [no changes]
*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function
*************** Finishing PHASE Morph array ops [no changes]
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1)
STMT00000 ( 0x000[E-] ... 0x002 )
[000003] -----+----- * JTRUE void
[000002] J----+-N--- \--* GT int
[000000] -----+----- +--* LCL_VAR int V01 arg1
[000001] -----+----- \--* CNS_INT int 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
*** marking local variables in block BB02 (weight=1)
STMT00003 ( 0x004[E-] ... 0x006 )
[000021] -----+----- * JTRUE void
[000020] J----+-N--- \--* GE int
[000018] -----+----- +--* LCL_VAR int V01 arg1
[000019] -----+----- \--* CNS_INT int 0
New refCnts for V01: refCnt = 2, refCntWtd = 2
*** marking local variables in block BB03 (weight=0)
STMT00001 ( 0x008[E-] ... 0x00E )
[000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
[000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
[000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
[000023] -----+----- arg0 rcx | +--* CNS_INT int 1
[000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
[000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
[000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
New refCnts for V07: refCnt = 1, refCntWtd = 0
Marking EH Var V07 as a register candidate.
New refCnts for V07: refCnt = 2, refCntWtd = 0
New refCnts for V01: refCnt = 3, refCntWtd = 2
*** marking local variables in block BB04 (weight=1)
STMT00002 ( 0x013[E-] ... 0x021 )
[000017] -A-XG+----- * RETURN float
[000016] -A-XG+----- \--* IND float
[000015] -A---+----- \--* ADD long
[000030] -A---+----- +--* COMMA long
[000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6
[000008] -----+----- | | \--* LCL_VAR byref V00 arg0
[000028] -----+----- | \--* LCL_VAR long V08 tmp6
[000014] -----+----- \--* LSH long
[000011] -----+----- +--* CAST long <- int
[000010] -----+----- | \--* LCL_VAR int V01 arg1
[000013] -----+----- \--* CNS_INT long 2
New refCnts for V08: refCnt = 1, refCntWtd = 2
V08 needs explicit zero init. Disqualified as a single-def register candidate.
New refCnts for V00: refCnt = 1, refCntWtd = 2
New refCnts for V08: refCnt = 2, refCntWtd = 4
New refCnts for V01: refCnt = 4, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 4
New refCnts for V00: refCnt = 3, refCntWtd = 6
New refCnts for V01: refCnt = 5, refCntWtd = 4
New refCnts for V01: refCnt = 6, refCntWtd = 5
*************** Finishing PHASE Mark local vars [no changes]
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
Trees after Find oper order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
( 5, 5) [000003] -----+----- * JTRUE void
( 3, 3) [000002] J----+-N--- \--* GT int
( 1, 1) [000000] -----+----- +--* LCL_VAR int V01 arg1
( 1, 1) [000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
( 5, 5) [000021] -----+----- * JTRUE void
( 3, 3) [000020] J----+-N--- \--* GE int
( 1, 1) [000018] -----+----- +--* LCL_VAR int V01 arg1
( 1, 1) [000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
( 22, 21) [000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
( 18, 18) [000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
( 1, 1) [000023] -----+----- arg0 rcx | +--* CNS_INT int 1
( 3, 10) [000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
( 3, 2) [000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
( 1, 1) [000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
( 7, 7) [000017] -A-XG+----- * RETURN float
( 6, 6) [000016] -A-XG+----- \--* IND float
( 5, 8) [000015] -A---+-N--- \--* ADD long
( 2, 4) [000030] -A---+----- +--* COMMA long
( 1, 3) [000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6
( 1, 1) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0
( 1, 1) [000028] -----+----- | \--* LCL_VAR long V08 tmp6
( 3, 4) [000014] -----+-N--- \--* LSH long
( 2, 3) [000011] -----+----- +--* CAST long <- int
( 1, 1) [000010] -----+----- | \--* LCL_VAR int V01 arg1
( 1, 1) [000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 11 tree nodes
*************** Finishing PHASE Set block order
Trees after Set block order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
N004 ( 5, 5) [000003] -----+----- * JTRUE void
N003 ( 3, 3) [000002] J----+-N--- \--* GT int
N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR int V01 arg1
N002 ( 1, 1) [000001] -----+----- \--* CNS_INT int 1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
N004 ( 5, 5) [000021] -----+----- * JTRUE void
N003 ( 3, 3) [000020] J----+-N--- \--* GE int
N001 ( 1, 1) [000018] -----+----- +--* LCL_VAR int V01 arg1
N002 ( 1, 1) [000019] -----+----- \--* CNS_INT int 0
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
N004 ( 22, 21) [000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5
N003 ( 18, 18) [000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
N001 ( 1, 1) [000023] -----+----- arg0 rcx | +--* CNS_INT int 1
N002 ( 3, 10) [000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
N005 ( 3, 2) [000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5
N006 ( 1, 1) [000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float
N010 ( 6, 6) [000016] -A-XG+----- \--* IND float
N009 ( 5, 8) [000015] -A---+-N--- \--* ADD long
N004 ( 2, 4) [000030] -A---+----- +--* COMMA long
N002 ( 1, 3) [000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6
N001 ( 1, 1) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0
N003 ( 1, 1) [000028] -----+----- | \--* LCL_VAR long V08 tmp6
N008 ( 3, 4) [000014] -----+-N--- \--* LSH long
N006 ( 2, 3) [000011] -----+----- +--* CAST long <- int
N005 ( 1, 1) [000010] -----+----- | \--* LCL_VAR int V01 arg1
N007 ( 1, 1) [000013] -----+----- \--* CNS_INT long 2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Local V02 should not be enregistered because: struct size does not match reg size
Local V03 should not be enregistered because: field of a dependently promoted struct
Local V04 should not be enregistered because: field of a dependently promoted struct
Local V05 should not be enregistered because: field of a dependently promoted struct
Tracked variable (4 out of 9) table:
V00 arg0 [ byref]: refCnt = 3, refCntWtd = 6
V01 arg1 [ int]: refCnt = 6, refCntWtd = 5
V08 tmp6 [ long]: refCnt = 2, refCntWtd = 4
V07 tmp5 [ ref]: refCnt = 2, refCntWtd = 0
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V01}
DEF(0)={ }
BB02 USE(1)={V01}
DEF(0)={ }
BB03 USE(1)={V01 } + ByrefExposed + GcHeap
DEF(1)={ V07} + ByrefExposed* + GcHeap*
BB04 USE(2)={V00 V01 } + ByrefExposed + GcHeap
DEF(1)={ V08}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (2)={V00 V01} + ByrefExposed + GcHeap
OUT(2)={V00 V01} + ByrefExposed + GcHeap
BB02 IN (2)={V00 V01} + ByrefExposed + GcHeap
OUT(2)={V00 V01} + ByrefExposed + GcHeap
BB03 IN (1)={V01} + ByrefExposed + GcHeap
OUT(0)={ }
BB04 IN (2)={V00 V01} + ByrefExposed + GcHeap
OUT(0)={ }
*************** In optRemoveRedundantZeroInits()
Analyzing BB01
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
V00.1: defined in BB00 1 uses (global)
V01.1: defined in BB00 4 uses (global)
V07.1: defined in BB00 0 uses (local)
V07.2: defined in BB03 1 uses (local)
V08.1: defined in BB04 1 uses (local)
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
N004 ( 5, 5) [000003] -----+----- * JTRUE void
N003 ( 3, 3) [000002] J----+-N--- \--* GT int
N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR int V01 arg1 u:1
N002 ( 1, 1) [000001] -----+----- \--* CNS_INT int 1
SSA MEM: ByrefExposed, GcHeap = m:1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
N004 ( 5, 5) [000021] -----+----- * JTRUE void
N003 ( 3, 3) [000020] J----+-N--- \--* GE int
N001 ( 1, 1) [000018] -----+----- +--* LCL_VAR int V01 arg1 u:1
N002 ( 1, 1) [000019] -----+----- \--* CNS_INT int 0
SSA MEM: ByrefExposed, GcHeap = m:1
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
N004 ( 22, 21) [000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5 d:2
N003 ( 18, 18) [000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
N001 ( 1, 1) [000023] -----+----- arg0 rcx | +--* CNS_INT int 1
N002 ( 3, 10) [000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
N005 ( 3, 2) [000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5 u:2 (last use)
N006 ( 1, 1) [000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1 u:1 (last use)
SSA MEM: ByrefExposed, GcHeap = m:2
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float
N010 ( 6, 6) [000016] -A-XG+----- \--* IND float
N009 ( 5, 8) [000015] -A---+-N--- \--* ADD long
N004 ( 2, 4) [000030] -A---+----- +--* COMMA long
N002 ( 1, 3) [000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6 d:1
N001 ( 1, 1) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0 u:1 (last use)
N003 ( 1, 1) [000028] -----+----- | \--* LCL_VAR long V08 tmp6 u:1 (last use)
N008 ( 3, 4) [000014] -----+-N--- \--* LSH long
N006 ( 2, 3) [000011] -----+----- +--* CAST long <- int
N005 ( 1, 1) [000010] -----+----- | \--* LCL_VAR int V01 arg1 u:1 (last use)
N007 ( 1, 1) [000013] -----+----- \--* CNS_INT long 2
SSA MEM: ByrefExposed, GcHeap = m:1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
SSA checks completed successfully
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method
*************** Finishing PHASE Early Value Propagation [no changes]
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $100
Visiting BB01
The SSA definition for ByrefExposed (#1) at start of BB01 is $100 {InitVal($42)}
The SSA definition for GcHeap (#1) at start of BB01 is $100 {InitVal($42)}
***** BB01, STMT00000(before)
N004 ( 5, 5) [000003] -----+----- * JTRUE void
N003 ( 3, 3) [000002] J----+-N--- \--* GT int
N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR int V01 arg1 u:1
N002 ( 1, 1) [000001] -----+----- \--* CNS_INT int 1
N001 [000000] LCL_VAR V01 arg1 u:1 => $c0 {InitVal($41)}
N002 [000001] CNS_INT 1 => $41 {IntCns 1}
N003 [000002] GT => $140 {GT($c0, $41)}
N004 [000003] JTRUE => $VN.Void
***** BB01, STMT00000(after)
N004 ( 5, 5) [000003] -----+----- * JTRUE void $VN.Void
N003 ( 3, 3) [000002] J----+-N--- \--* GT int $140
N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -----+----- \--* CNS_INT int 1 $41
Visiting BB02
Reachable through pred BB01
The SSA definition for ByrefExposed (#1) at start of BB02 is $100 {InitVal($42)}
The SSA definition for GcHeap (#1) at start of BB02 is $100 {InitVal($42)}
***** BB02, STMT00003(before)
N004 ( 5, 5) [000021] -----+----- * JTRUE void
N003 ( 3, 3) [000020] J----+-N--- \--* GE int
N001 ( 1, 1) [000018] -----+----- +--* LCL_VAR int V01 arg1 u:1
N002 ( 1, 1) [000019] -----+----- \--* CNS_INT int 0
N001 [000018] LCL_VAR V01 arg1 u:1 => $c0 {InitVal($41)}
N002 [000019] CNS_INT 0 => $40 {IntCns 0}
N003 [000020] GE => $141 {GE($c0, $40)}
N004 [000021] JTRUE => $VN.Void
***** BB02, STMT00003(after)
N004 ( 5, 5) [000021] -----+----- * JTRUE void $VN.Void
N003 ( 3, 3) [000020] J----+-N--- \--* GE int $141
N001 ( 1, 1) [000018] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000019] -----+----- \--* CNS_INT int 0 $40
Visiting BB04
Reachable through pred BB02
The SSA definition for ByrefExposed (#1) at start of BB04 is $100 {InitVal($42)}
The SSA definition for GcHeap (#1) at start of BB04 is $100 {InitVal($42)}
***** BB04, STMT00002(before)
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float
N010 ( 6, 6) [000016] -A-XG+----- \--* IND float
N009 ( 5, 8) [000015] -A---+-N--- \--* ADD long
N004 ( 2, 4) [000030] -A---+----- +--* COMMA long
N002 ( 1, 3) [000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6 d:1
N001 ( 1, 1) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0 u:1 (last use)
N003 ( 1, 1) [000028] -----+----- | \--* LCL_VAR long V08 tmp6 u:1 (last use)
N008 ( 3, 4) [000014] -----+-N--- \--* LSH long
N006 ( 2, 3) [000011] -----+----- +--* CAST long <- int
N005 ( 1, 1) [000010] -----+----- | \--* LCL_VAR int V01 arg1 u:1 (last use)
N007 ( 1, 1) [000013] -----+----- \--* CNS_INT long 2
N001 [000008] LCL_VAR V00 arg0 u:1 (last use) => $80 {InitVal($40)}
Tree [000027] assigned VN to local var V08/1: $180 {$80, long <- byref}
N002 [000027] STORE_LCL_VAR V08 tmp6 d:1 => $VN.Void
N003 [000028] LCL_VAR V08 tmp6 u:1 (last use) => $180 {$80, long <- byref}
N004 [000030] COMMA => $180 {$80, long <- byref}
N005 [000010] LCL_VAR V01 arg1 u:1 (last use) => $c0 {InitVal($41)}
N006 [000011] CAST => $181 {$c0, long <- int}
N007 [000013] CNS_INT 2 => $1c0 {LngCns 2}
N008 [000014] LSH => $182 {LSH($181, $1c0)}
N009 [000015] ADD => $183 {ADD($180, $182)}
N010 [000016] IND => <l:$301 {norm=$200 {ByrefExposedLoad($44, $183, $100)}, exc=$2c0 {NullPtrExc($183)}}, c:$300 {norm=$240 {MemOpaque:NotInLoop}, exc=$2c0 {NullPtrExc($183)}}>
N011 [000017] RETURN => $2c1 {norm=$VN.Void, exc=$2c0 {NullPtrExc($183)}}
***** BB04, STMT00002(after)
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float $2c1
N010 ( 6, 6) [000016] -A-XG+----- \--* IND float <l:$301, c:$300>
N009 ( 5, 8) [000015] -A---+-N--- \--* ADD long $183
N004 ( 2, 4) [000030] -A---+----- +--* COMMA long $180
N002 ( 1, 3) [000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6 d:1 $VN.Void
N001 ( 1, 1) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000028] -----+----- | \--* LCL_VAR long V08 tmp6 u:1 (last use) $180
N008 ( 3, 4) [000014] -----+-N--- \--* LSH long $182
N006 ( 2, 3) [000011] -----+----- +--* CAST long <- int $181
N005 ( 1, 1) [000010] -----+----- | \--* LCL_VAR int V01 arg1 u:1 (last use) $c0
N007 ( 1, 1) [000013] -----+----- \--* CNS_INT long 2 $1c0
Visiting BB03
Reachable through pred BB01
The SSA definition for ByrefExposed (#1) at start of BB03 is $100 {InitVal($42)}
The SSA definition for GcHeap (#1) at start of BB03 is $100 {InitVal($42)}
***** BB03, STMT00001(before)
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)
N004 ( 22, 21) [000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5 d:2
N003 ( 18, 18) [000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS
N001 ( 1, 1) [000023] -----+----- arg0 rcx | +--* CNS_INT int 1
N002 ( 3, 10) [000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope
N005 ( 3, 2) [000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5 u:2 (last use)
N006 ( 1, 1) [000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1 u:1 (last use)
N001 [000023] CNS_INT 1 => $41 {IntCns 1}
N002 [000022] CNS_INT(h) 0x7ff7f1188938 scope => $340 {Hnd const: 0x00007FF7F1188938 GTF_ICON_SCOPE_HDL}
N003 [000024] CALL help => $2c2 {LazyStrCns($41, $340)}
Tree [000025] assigned VN to local var V07/2: $2c2 {LazyStrCns($41, $340)}
N004 [000025] STORE_LCL_VAR V07 tmp5 d:2 => $VN.Void
N005 [000026] LCL_VAR V07 tmp5 u:2 (last use) => $2c2 {LazyStrCns($41, $340)}
N006 [000005] LCL_VAR V01 arg1 u:1 (last use) => $c0 {InitVal($41)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000006] to VN: $101.
N007 [000006] CALL => $VN.Void
***** BB03, STMT00001(after)
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) $VN.Void
N004 ( 22, 21) [000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5 d:2 $VN.Void
N003 ( 18, 18) [000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS $2c2
N001 ( 1, 1) [000023] -----+----- arg0 rcx | +--* CNS_INT int 1 $41
N002 ( 3, 10) [000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope $340
N005 ( 3, 2) [000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
N006 ( 1, 1) [000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1 u:1 (last use) $c0
*************** Finishing PHASE Do value numbering
Trees after Do value numbering
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
N004 ( 5, 5) [000003] -----+----- * JTRUE void $VN.Void
N003 ( 3, 3) [000002] J----+-N--- \--* GT int $140
N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -----+----- \--* CNS_INT int 1 $41
SSA MEM: ByrefExposed, GcHeap = m:1
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
N004 ( 5, 5) [000021] -----+----- * JTRUE void $VN.Void
N003 ( 3, 3) [000020] J----+-N--- \--* GE int $141
N001 ( 1, 1) [000018] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000019] -----+----- \--* CNS_INT int 0 $40
SSA MEM: ByrefExposed, GcHeap = m:1
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) $VN.Void
N004 ( 22, 21) [000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5 d:2 $VN.Void
N003 ( 18, 18) [000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS $2c2
N001 ( 1, 1) [000023] -----+----- arg0 rcx | +--* CNS_INT int 1 $41
N002 ( 3, 10) [000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope $340
N005 ( 3, 2) [000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
N006 ( 1, 1) [000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1 u:1 (last use) $c0
SSA MEM: ByrefExposed, GcHeap = m:2
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float $2c1
N010 ( 6, 6) [000016] -A-XG+----- \--* IND float <l:$301, c:$300>
N009 ( 5, 8) [000015] -A---+-N--- \--* ADD long $183
N004 ( 2, 4) [000030] -A---+----- +--* COMMA long $180
N002 ( 1, 3) [000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6 d:1 $VN.Void
N001 ( 1, 1) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000028] -----+----- | \--* LCL_VAR long V08 tmp6 u:1 (last use) $180
N008 ( 3, 4) [000014] -----+-N--- \--* LSH long $182
N006 ( 2, 3) [000011] -----+----- +--* CAST long <- int $181
N005 ( 1, 1) [000010] -----+----- | \--* LCL_VAR int V01 arg1 u:1 (last use) $c0
N007 ( 1, 1) [000013] -----+----- \--* CNS_INT long 2 $1c0
SSA MEM: ByrefExposed, GcHeap = m:1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
SSA checks completed successfully
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Hoist loop code
No loops; no hoisting
*************** Finishing PHASE Hoist loop code [no changes]
*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
curSsaName stack: { }
Copy Assertion for BB02
curSsaName stack: { [000000]:V01/1 }
Copy Assertion for BB04
curSsaName stack: { [000000]:V01/1 }
Live vars after [000008]: {V00 V01} -{V00} => {V01}
orig [000008] copy [000000] VNs proved equivalent
Live vars after [000027]: {V01} +{V08} => {V01 V08}
Live vars after [000028]: {V01 V08} -{V08} => {V01}
orig [000028] copy [000008] VNs proved equivalent
orig [000028] copy [000000] VNs proved equivalent
Live vars after [000010]: {V01} -{V01} => {}
orig [000010] copy [000008] VNs proved equivalent
orig [000010] copy [000027] VNs proved equivalent
Copy Assertion for BB03
curSsaName stack: { [000008]:V00/1 [000000]:V01/1 }
Live vars after [000025]: {V01} +{V07} => {V01 V07}
Live vars after [000026]: {V01 V07} -{V07} => {V01}
orig [000026] copy [000008] VNs proved equivalent
orig [000026] copy [000000] VNs proved equivalent
Live vars after [000005]: {V01} -{V01} => {}
orig [000005] copy [000008] VNs proved equivalent
orig [000005] copy [000025] VNs proved equivalent
*************** Finishing PHASE VN based copy prop [no changes]
*************** Starting PHASE Redundant branch opts
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
--- Trying RBO in BB02 ---
Relop [000020] BB02 value unknown, trying inference
Dominator BB01 of BB02 can infer value of dominated relop
N003 ( 3, 3) [000002] J----+-N--- * GT int $140
N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -----+----- \--* CNS_INT int 1 $41
Redundant compare; current relop:
N003 ( 3, 3) [000020] J----+-N--- * GE int $141
N001 ( 1, 1) [000018] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000019] -----+----- \--* CNS_INT int 0 $40
inference failed -- will keep looking higher
No usable PhiDef VNs
--- Trying RBO in BB01 ---
*************** Finishing PHASE Redundant branch opts [no changes]
*************** Starting PHASE Optimize Valnum CSEs
CONST CSE is disabled
Standard CSE Heuristic
Standard CSE Heuristic
*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB02(1) ( cond ) i IBC
BB02 [0001] 1 BB01 1 2 [004..008)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 2 BB01,BB02 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB02 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
N004 ( 5, 5) [000003] -----+----- * JTRUE void $VN.Void
N003 ( 3, 3) [000002] J----+-N--- \--* GT int $140
N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -----+----- \--* CNS_INT int 1 $41
------------ BB02 [0001] [004..008) -> BB04(1),BB03(0) (cond), preds={BB01} succs={BB03,BB04}
***** BB02 [0001]
STMT00003 ( 0x004[E-] ... 0x006 )
N004 ( 5, 5) [000021] -----+----- * JTRUE void $VN.Void
N003 ( 3, 3) [000020] J----+-N--- \--* GE int $141
N001 ( 1, 1) [000018] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000019] -----+----- \--* CNS_INT int 0 $40
------------ BB03 [0002] [008..013) (throw), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) $VN.Void
N004 ( 22, 21) [000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5 d:2 $VN.Void
N003 ( 18, 18) [000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS $2c2
N001 ( 1, 1) [000023] -----+----- arg0 rcx | +--* CNS_INT int 1 $41
N002 ( 3, 10) [000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope $340
N005 ( 3, 2) [000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
N006 ( 1, 1) [000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1 u:1 (last use) $c0
------------ BB04 [0003] [013..022) (return), preds={BB02} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float $2c1
N010 ( 6, 6) [000016] -A-XG+----- \--* IND float <l:$301, c:$300>
N009 ( 5, 8) [000015] -A---+-N--- \--* ADD long $183
N004 ( 2, 4) [000030] -A---+----- +--* COMMA long $180
N002 ( 1, 3) [000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6 d:1 $VN.Void
N001 ( 1, 1) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000028] -----+----- | \--* LCL_VAR long V08 tmp6 u:1 (last use) $180
N008 ( 3, 4) [000014] -----+-N--- \--* LSH long $182
N006 ( 2, 3) [000011] -----+----- +--* CAST long <- int $181
N005 ( 1, 1) [000010] -----+----- | \--* LCL_VAR int V01 arg1 u:1 (last use) $c0
N007 ( 1, 1) [000013] -----+----- \--* CNS_INT long 2 $1c0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (4 profiled blocks, 0 unprofiled)
*************** Starting PHASE Assertion prop
GenTreeNode creates assertion:
N004 ( 5, 5) [000003] -----+----- * JTRUE void $VN.Void
In BB01 New Global Constant Assertion: ($140,$40) Const_Loop_Bnd {GT($c0, $41)} is not {IntCns 0}, index = #01
GenTreeNode creates assertion:
N004 ( 5, 5) [000003] -----+----- * JTRUE void $VN.Void
In BB01 New Global Constant Assertion: ($140,$40) Const_Loop_Bnd {GT($c0, $41)} is {IntCns 0}, index = #02
GenTreeNode creates assertion:
N004 ( 5, 5) [000021] -----+----- * JTRUE void $VN.Void
In BB02 New Global Constant Assertion: ($141,$40) Const_Loop_Bnd {GE($c0, $40)} is not {IntCns 0}, index = #03
GenTreeNode creates assertion:
N004 ( 5, 5) [000021] -----+----- * JTRUE void $VN.Void
In BB02 New Global Constant Assertion: ($141,$40) Const_Loop_Bnd {GE($c0, $40)} is {IntCns 0}, index = #04
BB01 valueGen = #02 => BB03 valueGen = #01
BB02 valueGen = #04 => BB04 valueGen = #03
BB03 valueGen = #NA
BB04 valueGen = #NA
BB01:
in = #NA
out = #02
BB03 = #01
BB02:
in = #02
out = #02 #04
BB04 = #02 #03
BB03:
in = #NA
out = #NA
BB04:
in = #02 #03
out = #02 #03
Propagating #NA for BB01, stmt STMT00000, tree [000000], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000001], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000002], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000003], tree -> #01
Propagating #02 for BB02, stmt STMT00003, tree [000018], tree -> #NA
Propagating #02 for BB02, stmt STMT00003, tree [000019], tree -> #NA
Propagating #02 for BB02, stmt STMT00003, tree [000020], tree -> #NA
Constant Assertion: ($140,$40) Const_Loop_Bnd {GT($c0, $41)} is {IntCns 0}, index = #02
Tightening pRange: [<Unknown, Unknown>] with assertedRange: [<Unknown, 1>] into [<Unknown, 1>]
Propagating #02 for BB02, stmt STMT00003, tree [000021], tree -> #03
Propagating #NA for BB03, stmt STMT00001, tree [000023], tree -> #NA
Propagating #NA for BB03, stmt STMT00001, tree [000022], tree -> #NA
Propagating #NA for BB03, stmt STMT00001, tree [000024], tree -> #NA
Propagating #NA for BB03, stmt STMT00001, tree [000025], tree -> #NA
Propagating #NA for BB03, stmt STMT00001, tree [000026], tree -> #NA
Propagating #NA for BB03, stmt STMT00001, tree [000005], tree -> #NA
Propagating #NA for BB03, stmt STMT00001, tree [000006], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000008], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000027], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000028], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000030], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000010], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000011], tree -> #NA
Constant Assertion: ($140,$40) Const_Loop_Bnd {GT($c0, $41)} is {IntCns 0}, index = #02
Tightening pRange: [<Unknown, Unknown>] with assertedRange: [<Unknown, 1>] into [<Unknown, 1>]
Constant Assertion: ($141,$40) Const_Loop_Bnd {GE($c0, $40)} is not {IntCns 0}, index = #03
Tightening pRange: [<Unknown, 1>] with assertedRange: [<0, 1>] into [<0, 1>]
Propagating #02 #03 for BB04, stmt STMT00002, tree [000013], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000014], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000015], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000016], tree -> #NA
Propagating #02 #03 for BB04, stmt STMT00002, tree [000017], tree -> #NA
*************** Finishing PHASE Assertion prop [no changes]
*************** Starting PHASE Optimize index checks
*************** Finishing PHASE Optimize index checks [no changes]
*************** Starting PHASE Optimize Induction Variables
*************** In optInductionVariables()
Skipping since this method has no natural loops
*************** Finishing PHASE Optimize Induction Variables [no changes]
*************** Starting PHASE VN-based dead store removal
Considering [000025] for removal...
-- no; last def not in the same block
*************** Finishing PHASE VN-based dead store removal [no changes]
*************** Starting PHASE Clone blocks with range checks
Current method has no bounds checks
*************** Finishing PHASE Clone blocks with range checks [no changes]
*************** Starting PHASE VN based intrinsic expansion
*************** Finishing PHASE VN based intrinsic expansion [no changes]
Removing PHI functions
*************** Starting PHASE Stress gtSplitTree
*************** Finishing PHASE Stress gtSplitTree [no changes]
*************** Starting PHASE Remove empty finally 3
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 3 [no changes]
*************** Starting PHASE Remove empty try 3
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 3 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 3
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 3 [no changes]
*************** Starting PHASE Create EH funclets
*************** Finishing PHASE Create EH funclets [no changes]
*************** Starting PHASE Expand casts
*************** Finishing PHASE Expand casts [no changes]
*************** Starting PHASE Expand runtime lookups
*************** Finishing PHASE Expand runtime lookups [no changes]
*************** Starting PHASE Expand static init
Nothing to expand.
*************** Finishing PHASE Expand static init [no changes]
*************** Starting PHASE Expand TLS access
Nothing to expand.
*************** Finishing PHASE Expand TLS access [no changes]
*************** Starting PHASE Expand stack array allocation
*************** Finishing PHASE Expand stack array allocation [no changes]
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Create throw helper blocks
*************** Finishing PHASE Create throw helper blocks [no changes]
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
setting likelihood of BB01 -> BB04 to 1
setting likelihood of BB01 -> BB03 from 0 to 0
fgRemoveBlock BB02, unreachable=true
Removing unreachable BB02
removing useless STMT00003 ( 0x004[E-] ... 0x006 )
N004 ( 5, 5) [000021] -----+----- * JTRUE void $VN.Void
N003 ( 3, 3) [000020] J----+-N--- \--* GE int $141
N001 ( 1, 1) [000018] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000019] -----+----- \--* CNS_INT int 0 $40
from BB02
BB02 becomes empty
optimized 1 BBJ_COND cases in 2 passes
*************** Finishing PHASE Optimize bools
Trees after Optimize bools
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB01 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x002 )
N004 ( 5, 5) [000003] -----+----- * JTRUE void $VN.Void
N003 ( 3, 3) [000002] J----+-N-U- \--* LE int
N001 ( 1, 1) [000000] -----+----- +--* LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -----+----- \--* CNS_INT int 1
------------ BB03 [0002] [008..013) (throw), preds={BB01} succs={}
***** BB03 [0002]
STMT00001 ( 0x008[E-] ... 0x00E )
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) $VN.Void
N004 ( 22, 21) [000025] DAC-G+----- arg0 setup +--* STORE_LCL_VAR ref V07 tmp5 d:2 $VN.Void
N003 ( 18, 18) [000024] --C-G+----- | \--* CALL help ref CORINFO_HELP_STRCNS $2c2
N001 ( 1, 1) [000023] -----+----- arg0 rcx | +--* CNS_INT int 1 $41
N002 ( 3, 10) [000022] H----+----- arg1 rdx | \--* CNS_INT(h) long 0x7ff7f1188938 scope $340
N005 ( 3, 2) [000026] -----+----- arg0 rcx +--* LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
N006 ( 1, 1) [000005] -----+----- arg1 rdx \--* LCL_VAR int V01 arg1 u:1 (last use) $c0
------------ BB04 [0003] [013..022) (return), preds={BB01} succs={}
***** BB04 [0003]
STMT00002 ( 0x013[E-] ... 0x021 )
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float $2c1
N010 ( 6, 6) [000016] -A-XG+----- \--* IND float <l:$301, c:$300>
N009 ( 5, 8) [000015] -A---+-N--- \--* ADD long $183
N004 ( 2, 4) [000030] -A---+----- +--* COMMA long $180
N002 ( 1, 3) [000027] DA---+----- | +--* STORE_LCL_VAR long V08 tmp6 d:1 $VN.Void
N001 ( 1, 1) [000008] -----+----- | | \--* LCL_VAR byref V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000028] -----+----- | \--* LCL_VAR long V08 tmp6 u:1 (last use) $180
N008 ( 3, 4) [000014] -----+-N--- \--* LSH long $182
N006 ( 2, 3) [000011] -----+---U- +--* CAST long <- uint $181
N005 ( 1, 1) [000010] -----+----- | \--* LCL_VAR int V01 arg1 u:1 (last use) $c0
N007 ( 1, 1) [000013] -----+----- \--* CNS_INT long 2 $1c0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (3 profiled blocks, 0 unprofiled)
*************** Starting PHASE If conversion
*************** Finishing PHASE If conversion [no changes]
*************** Starting PHASE Recognize Switch
*************** Finishing PHASE Recognize Switch [no changes]
*************** Starting PHASE Optimize pre-layout
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i IBC rare hascall gcsafe
BB04 [0003] 1 BB01 1 2 [013..022) (return) i IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize pre-layout [no changes]
*************** Starting PHASE Repair profile pre-layout
Profile is already consistent.
*************** Finishing PHASE Repair profile pre-layout [no changes]
*************** Starting PHASE Rationalize IR
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
[000031] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -----+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 ( 3, 3) [000002] J----+-N-U- t2 = * LE int
/--* t2 int
N004 ( 5, 5) [000003] -----+----- * JTRUE void $VN.Void
------------ BB03 [0002] [008..013) (throw), preds={BB01} succs={}
[000032] ----------- IL_OFFSET void INLRT @ 0x008[E-]
N001 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 $41
N002 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope $340
/--* t23 int arg0 rcx
+--* t22 long arg1 rdx
N003 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS $2c2
/--* t24 ref
N004 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 $VN.Void
N005 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
N006 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 (last use) $c0
/--* t26 ref arg0 rcx
+--* t5 int arg1 rdx
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) $VN.Void
------------ BB04 [0003] [013..022) (return), preds={BB01} succs={}
[000033] ----------- IL_OFFSET void INLRT @ 0x013[E-]
N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 (last use) $80
/--* t8 byref
N002 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 $VN.Void
N003 ( 1, 1) [000028] -----+----- t28 = LCL_VAR long V08 tmp6 u:1 (last use) $180
N005 ( 1, 1) [000010] -----+----- t10 = LCL_VAR int V01 arg1 u:1 (last use) $c0
/--* t10 int
N006 ( 2, 3) [000011] -----+---U- t11 = * CAST long <- uint $181
N007 ( 1, 1) [000013] -----+----- t13 = CNS_INT long 2 $1c0
/--* t11 long
+--* t13 long
N008 ( 3, 4) [000014] -----+-N--- t14 = * LSH long $182
/--* t28 long
+--* t14 long
N009 ( 5, 8) [000015] -A---+-N--- t15 = * ADD long $183
/--* t15 long
N010 ( 6, 6) [000016] -A-XG+----- t16 = * IND float <l:$301, c:$300>
/--* t16 float
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float $2c1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (3 profiled blocks, 0 unprofiled)
*************** Starting PHASE Lowering nodeinfo
0 parameter register to local mappings
Lowering JTRUE:
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 ( 3, 3) [000002] J----+-N-U- t2 = * LE int
/--* t2 int
N004 ( 5, 5) [000003] -----+----- * JTRUE void $VN.Void
Lowering condition:
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 ( 3, 3) [000002] J----+-N-U- t2 = * LE int
Lowering JTRUE Result:
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 ( 3, 3) [000002] -----+-N-U- * CMP void
N004 ( 5, 5) [000003] -----+----- JCC void cond=ULE
lowering call (before):
N001 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 $41
N002 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope $340
/--* t23 int arg0 rcx
+--* t22 long arg1 rdx
N003 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS $2c2
Args:
======
Late args:
======
Lowering arg:
N001 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 $41
Passed in [00..04) reg rcx
N001 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 $41
/--* t23 int
[000034] ----------- t34 = * PUTARG_REG int REG rcx
Lowering arg:
N002 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope $340
Passed in [00..08) reg rdx
N002 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope $340
/--* t22 long
[000035] ----------- t35 = * PUTARG_REG long REG rdx
results of lowering call:
N001 ( 3, 10) [000036] H---------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn
/--* t36 long
N002 ( 5, 12) [000037] n---G------ t37 = * IND long
Bumping outgoing arg space size from 0 to 32 for [000024]
lowering call (after):
N001 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 $41
/--* t23 int
[000034] ----------- t34 = * PUTARG_REG int REG rcx
N002 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope $340
/--* t22 long
[000035] ----------- t35 = * PUTARG_REG long REG rdx
N001 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn
/--* t36 long
N002 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
N003 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS $2c2
lowering store lcl var/field (before):
N001 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 $41
/--* t23 int
[000034] ----------- t34 = * PUTARG_REG int REG rcx
N002 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope $340
/--* t22 long
[000035] ----------- t35 = * PUTARG_REG long REG rdx
N001 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn
/--* t36 long
N002 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
N003 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS $2c2
/--* t24 ref
N004 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 $41
/--* t23 int
[000034] ----------- t34 = * PUTARG_REG int REG rcx
N002 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope $340
/--* t22 long
[000035] ----------- t35 = * PUTARG_REG long REG rdx
N001 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn
/--* t36 long
N002 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
N003 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS $2c2
/--* t24 ref
N004 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 $VN.Void
lowering call (before):
N005 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
N006 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 (last use) $c0
/--* t26 ref arg0 rcx
+--* t5 int arg1 rdx
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) $VN.Void
Args:
======
Late args:
======
Lowering arg:
N005 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
Passed in [00..08) reg rcx
N005 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
/--* t26 ref
[000038] ----------- t38 = * PUTARG_REG ref REG rcx
Lowering arg:
N006 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 (last use) $c0
Passed in [00..04) reg rdx
N006 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 (last use) $c0
/--* t5 int
[000039] ----------- t39 = * PUTARG_REG int REG rdx
results of lowering call:
N001 ( 3, 10) [000040] H---------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t40 long
N002 ( 5, 12) [000041] n---G------ t41 = * IND long
lowering call (after):
N005 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
/--* t26 ref
[000038] ----------- t38 = * PUTARG_REG ref REG rcx
N006 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 (last use) $c0
/--* t5 int
[000039] ----------- t39 = * PUTARG_REG int REG rdx
N001 ( 3, 10) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t40 long
N002 ( 5, 12) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 ref arg0 rcx
+--* t39 int arg1 rdx
+--* t41 long control expr
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 (last use) $80
/--* t8 byref
N002 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 (last use) $80
/--* t8 byref
N002 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 $VN.Void
Addressing mode:
Base
N003 ( 1, 1) [000028] -----+----- * LCL_VAR long V08 tmp6 u:1 (last use) $180
+ Index * 4 + 0
N006 ( 2, 3) [000011] -----+---U- * CAST long <- uint $181
Removing unused node:
N008 ( 3, 4) [000014] -----+-N--- * LSH long $182
Removing unused node:
N007 ( 1, 1) [000013] -c---+----- * CNS_INT long 2 $1c0
New addressing mode node:
N009 ( 5, 8) [000015] -----+----- * LEA(b+(i*4)+0) long
lowering return node
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float $2c1
============
Lower has completed modifying nodes.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
[000031] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 ( 3, 3) [000002] -----+-N-U- * CMP void
N004 ( 5, 5) [000003] -----+----- JCC void cond=ULE
------------ BB03 [0002] [008..013) (throw), preds={BB01} succs={}
[000032] ----------- IL_OFFSET void INLRT @ 0x008[E-]
N001 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 $41
/--* t23 int
[000034] ----------- t34 = * PUTARG_REG int REG rcx
N002 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope $340
/--* t22 long
[000035] ----------- t35 = * PUTARG_REG long REG rdx
N001 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn
/--* t36 long
N002 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
N003 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS $2c2
/--* t24 ref
N004 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 $VN.Void
N005 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
/--* t26 ref
[000038] ----------- t38 = * PUTARG_REG ref REG rcx
N006 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 (last use) $c0
/--* t5 int
[000039] ----------- t39 = * PUTARG_REG int REG rdx
N001 ( 3, 10) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t40 long
N002 ( 5, 12) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 ref arg0 rcx
+--* t39 int arg1 rdx
+--* t41 long control expr
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) $VN.Void
------------ BB04 [0003] [013..022) (return), preds={BB01} succs={}
[000033] ----------- IL_OFFSET void INLRT @ 0x013[E-]
N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 (last use) $80
/--* t8 byref
N002 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 $VN.Void
N003 ( 1, 1) [000028] -----+----- t28 = LCL_VAR long V08 tmp6 u:1 (last use) $180
N005 ( 1, 1) [000010] -----+----- t10 = LCL_VAR int V01 arg1 u:1 (last use) $c0
/--* t10 int
N006 ( 2, 3) [000011] -----+---U- t11 = * CAST long <- uint $181
/--* t28 long
+--* t11 long
N009 ( 5, 8) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long
/--* t15 long
N010 ( 6, 6) [000016] -A-XG+----- t16 = * IND float <l:$301, c:$300>
/--* t16 float
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float $2c1
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V07: refCnt = 1, refCntWtd = 0
New refCnts for V07: refCnt = 2, refCntWtd = 0
New refCnts for V01: refCnt = 2, refCntWtd = 1
New refCnts for V00: refCnt = 1, refCntWtd = 2
New refCnts for V08: refCnt = 1, refCntWtd = 2
New refCnts for V08: refCnt = 2, refCntWtd = 4
New refCnts for V01: refCnt = 3, refCntWtd = 2
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 4
New refCnts for V00: refCnt = 3, refCntWtd = 6
New refCnts for V01: refCnt = 4, refCntWtd = 3
New refCnts for V01: refCnt = 5, refCntWtd = 4
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 byref ld-addr-op single-def
; V01 arg1 int single-def
; V02 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
; V03 tmp1 float do-not-enreg[] "field V00.X (fldOffset=0x0)" P-DEP
; V04 tmp2 float do-not-enreg[] "field V00.Y (fldOffset=0x4)" P-DEP
; V05 tmp3 float do-not-enreg[] "field V00.Z (fldOffset=0x8)" P-DEP
; V06 tmp4 struct <Program.EntryPoint+Vector2, 12> do-not-enreg[S] "Promoted implicit byref" <Program.EntryPoint+Vector2>
; V07 tmp5 ref single-def "argument with side effect"
; V08 tmp6 long "Cast away GC"
In fgLocalVarLivenessInit
Local V02 should not be enregistered because: struct size does not match reg size
Local V03 should not be enregistered because: field of a dependently promoted struct
Local V04 should not be enregistered because: field of a dependently promoted struct
Local V05 should not be enregistered because: field of a dependently promoted struct
Tracked variable (4 out of 9) table:
V00 arg0 [ byref]: refCnt = 3, refCntWtd = 6
V01 arg1 [ int]: refCnt = 5, refCntWtd = 4
V08 tmp6 [ long]: refCnt = 2, refCntWtd = 4
V07 tmp5 [ ref]: refCnt = 2, refCntWtd = 0
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V01}
DEF(0)={ }
BB03 USE(1)={V01 } + ByrefExposed + GcHeap
DEF(1)={ V07} + ByrefExposed* + GcHeap*
BB04 USE(2)={V00 V01 } + ByrefExposed + GcHeap
DEF(1)={ V08}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (2)={V00 V01} + ByrefExposed + GcHeap
OUT(2)={V00 V01} + ByrefExposed + GcHeap
BB03 IN (1)={V01} + ByrefExposed + GcHeap
OUT(0)={ }
BB04 IN (2)={V00 V01} + ByrefExposed + GcHeap
OUT(0)={ }
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V07: refCnt = 1, refCntWtd = 0
New refCnts for V07: refCnt = 2, refCntWtd = 0
New refCnts for V01: refCnt = 2, refCntWtd = 1
New refCnts for V00: refCnt = 1, refCntWtd = 2
New refCnts for V08: refCnt = 1, refCntWtd = 2
New refCnts for V08: refCnt = 2, refCntWtd = 4
New refCnts for V01: refCnt = 3, refCntWtd = 2
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 4
New refCnts for V00: refCnt = 3, refCntWtd = 6
New refCnts for V01: refCnt = 4, refCntWtd = 3
New refCnts for V01: refCnt = 5, refCntWtd = 4
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
[000031] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 $c0
N002 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1
/--* t0 int
+--* t1 int
N003 ( 3, 3) [000002] -----+-N-U- * CMP void
N004 ( 5, 5) [000003] -----+----- JCC void cond=ULE
------------ BB03 [0002] [008..013) (throw), preds={BB01} succs={}
[000032] ----------- IL_OFFSET void INLRT @ 0x008[E-]
N001 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 $41
/--* t23 int
[000034] ----------- t34 = * PUTARG_REG int REG rcx
N002 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope $340
/--* t22 long
[000035] ----------- t35 = * PUTARG_REG long REG rdx
N001 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn
/--* t36 long
N002 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
N003 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS $2c2
/--* t24 ref
N004 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 $VN.Void
N005 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 (last use) $2c2
/--* t26 ref
[000038] ----------- t38 = * PUTARG_REG ref REG rcx
N006 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 (last use) $c0
/--* t5 int
[000039] ----------- t39 = * PUTARG_REG int REG rdx
N001 ( 3, 10) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn
/--* t40 long
N002 ( 5, 12) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 ref arg0 rcx
+--* t39 int arg1 rdx
+--* t41 long control expr
N007 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) $VN.Void
------------ BB04 [0003] [013..022) (return), preds={BB01} succs={}
[000033] ----------- IL_OFFSET void INLRT @ 0x013[E-]
N001 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 (last use) $80
/--* t8 byref
N002 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 $VN.Void
N003 ( 1, 1) [000028] -----+----- t28 = LCL_VAR long V08 tmp6 u:1 (last use) $180
N005 ( 1, 1) [000010] -----+----- t10 = LCL_VAR int V01 arg1 u:1 (last use) $c0
/--* t10 int
N006 ( 2, 3) [000011] -----+---U- t11 = * CAST long <- uint $181
/--* t28 long
+--* t11 long
N009 ( 5, 8) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long
/--* t15 long
N010 ( 6, 6) [000016] -A-XG+----- t16 = * IND float <l:$301, c:$300>
/--* t16 float
N011 ( 7, 7) [000017] -A-XG+----- * RETURN float $2c1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (3 profiled blocks, 0 unprofiled)
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01
use: {V01}
def: {}
in: {V00 V01}
out: {V00 V01}
BB03
use: {V01}
def: {V07}
in: {V01}
out: {}
BB04
use: {V00 V01}
def: {V08}
in: {V00 V01}
out: {}
Interval 0: byref RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 0: (V00) byref RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 1: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 1: (V01) int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 2: (V07) ref RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 3: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 3: (V08) long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 2]
01 -> BB04[2, 1]
02 -> BB03[1, 0]
Flow graph has no cycles; skipping identification of natural loops
Start LSRA Block Sequence:
Current block: BB01
Current block: BB04
Current block: BB03
Final LSRA Block Sequence:
BB01 ( 1 )
BB04 ( 1 )
BB03 ( 0 )
BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. V01(t0)
N002. CNS_INT 1
N003. CMP ; t0
N004. JCC cond=ULE
BB04 [0003] [013..022) (return), preds={BB01} succs={}
=====
N000. IL_OFFSET INLRT @ 0x013[E-]
N001. V00(t8*)
N002. V08(t27); t8*
N003. V08(t28*)
N005. V01(t10*)
N006. t11 = CAST ; t10*
N009. t15 = LEA(b+(i*4)+0); t28*,t11
N010. t16 = IND ; t15
N011. RETURN ; t16
BB03 [0002] [008..013) (throw), preds={BB01} succs={}
=====
N000. IL_OFFSET INLRT @ 0x008[E-]
N001. t23 = CNS_INT 1
N000. t34 = PUTARG_REG; t23
N002. t22 = CNS_INT(h) 0x7ff7f1188938 scope
N000. t35 = PUTARG_REG; t22
N001. CNS_INT(h) 0x7ff7f0e0d9c8 ftn
N002. IND
N003. t24 = CALL help; t34,t35
N004. V07(t25); t24
N005. V07(t26*)
N000. t38 = PUTARG_REG; t26*
N006. V01(t5*)
N000. t39 = PUTARG_REG; t5*
N001. CNS_INT(h) 0x7ff7f13342a0 ftn
N002. IND
N007. CALL ; t38,t39
buildIntervals second part ========
Arg V00 is live in reg rcx
Arg V01 is live in reg rdx
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed wt=100.00>
NEW BLOCK BB01
<RefPosition #2 @1 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N003 (???,???) [000031] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N005 ( 1, 1) [000000] -----+----- * LCL_VAR int V01 arg1 u:1 NA REG NA $c0
DefList: { }
N007 ( 1, 1) [000001] -c---+----- * CNS_INT int 1 REG NA
Contained
DefList: { }
N009 ( 3, 3) [000002] -----+-N-U- * CMP void REG NA
<RefPosition #3 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
DefList: { }
N011 ( 5, 5) [000003] -----+----- * JCC void cond=ULE REG NA
CHECKING LAST USES for BB01, liveout={V00 V01}
==============================
use: {V01}
def: {}
NEW BLOCK BB04
Setting BB01 as the predecessor for determining incoming variable registers of BB04
<RefPosition #4 @13 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N015 (???,???) [000033] ----------- * IL_OFFSET void INLRT @ 0x013[E-] REG NA
DefList: { }
N017 ( 1, 1) [000008] -----+----- * LCL_VAR byref V00 arg0 u:1 NA (last use) REG NA $80
DefList: { }
N019 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 NA REG NA $VN.Void
<RefPosition #5 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=600.00>
Assigning related <V08/L3> to <V00/L0>
<RefPosition #6 @20 RefTypeDef <Ivl:3 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=400.00>
DefList: { }
N021 ( 1, 1) [000028] -----+----- * LCL_VAR long V08 tmp6 u:1 NA (last use) REG NA $180
DefList: { }
N023 ( 1, 1) [000010] -----+----- * LCL_VAR int V01 arg1 u:1 NA (last use) REG NA $c0
DefList: { }
N025 ( 2, 3) [000011] -----+---U- * CAST long <- uint REG NA $181
<RefPosition #7 @25 RefTypeUse <Ivl:1 V01> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=400.00>
Interval 4: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #8 @26 RefTypeDef <Ivl:4> CAST BB04 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N025.t11. CAST }
N027 ( 5, 8) [000015] -c---+----- * LEA(b+(i*4)+0) long REG NA
Contained
DefList: { N025.t11. CAST }
N029 ( 6, 6) [000016] -A-XG+----- * IND float REG NA <l:$301, c:$300>
<RefPosition #9 @29 RefTypeUse <Ivl:3 V08> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #10 @29 RefTypeUse <Ivl:4> BB04 regmask=[allInt] minReg=1 last wt=100.00>
Interval 5: float RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[allMask]
<RefPosition #11 @30 RefTypeDef <Ivl:5> IND BB04 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N029.t16. IND }
N031 ( 7, 7) [000017] -A-XG+----- * RETURN float REG NA $2c1
<RefPosition #12 @31 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #13 @31 RefTypeUse <Ivl:5> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
CHECKING LAST USES for BB04, liveout={}
==============================
use: {V00 V01}
def: {V08}
NEW BLOCK BB03
Setting BB01 as the predecessor for determining incoming variable registers of BB03
<RefPosition #14 @33 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=0.00>
firstColdLoc = 35
DefList: { }
N035 (???,???) [000032] ----------- * IL_OFFSET void INLRT @ 0x008[E-] REG NA
DefList: { }
N037 ( 1, 1) [000023] -----+----- * CNS_INT int 1 REG NA $41
Interval 6: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #15 @38 RefTypeDef <Ivl:6> CNS_INT BB03 regmask=[allInt] minReg=1 wt=0.00>
DefList: { N037.t23. CNS_INT }
N039 (???,???) [000034] ----------- * PUTARG_REG int REG rcx
<RefPosition #16 @39 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #17 @39 RefTypeUse <Ivl:6> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
Interval 7: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #18 @40 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #19 @40 RefTypeDef <Ivl:7> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=0.00>
DefList: { N039.t34. PUTARG_REG }
N041 ( 3, 10) [000022] H----+----- * CNS_INT(h) long 0x7ff7f1188938 scope REG NA $340
Interval 8: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #20 @42 RefTypeDef <Ivl:8> CNS_INT BB03 regmask=[allInt] minReg=1 wt=0.00>
DefList: { N039.t34. PUTARG_REG; N041.t22. CNS_INT }
N043 (???,???) [000035] ----------- * PUTARG_REG long REG rdx
<RefPosition #21 @43 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #22 @43 RefTypeUse <Ivl:8> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
Interval 9: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #23 @44 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #24 @44 RefTypeDef <Ivl:9> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=0.00>
DefList: { N039.t34. PUTARG_REG; N043.t35. PUTARG_REG }
N045 ( 3, 10) [000036] Hc--------- * CNS_INT(h) long 0x7ff7f0e0d9c8 ftn REG NA
Contained
DefList: { N039.t34. PUTARG_REG; N043.t35. PUTARG_REG }
N047 ( 5, 12) [000037] nc--G------ * IND long REG NA
Contained
DefList: { N039.t34. PUTARG_REG; N043.t35. PUTARG_REG }
N049 ( 18, 18) [000024] --C-G+----- * CALL help ref CORINFO_HELP_STRCNS REG NA $2c2
<RefPosition #25 @49 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #26 @49 RefTypeUse <Ivl:7> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #27 @49 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #28 @49 RefTypeUse <Ivl:9> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #29 @50 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11 mm0-mm5] minReg=1>
Interval 10: ref RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #30 @50 RefTypeFixedReg <Reg:rax> BB03 regmask=[rax] minReg=1 wt=0.00>
<RefPosition #31 @50 RefTypeDef <Ivl:10> CALL BB03 regmask=[rax] minReg=1 fixed wt=0.00>
DefList: { N049.t24. CALL }
N051 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 NA REG NA $VN.Void
<RefPosition #32 @51 RefTypeUse <Ivl:10> BB03 regmask=[allInt] minReg=1 last wt=0.00>
Assigning related <V07/L2> to <I10>
<RefPosition #33 @52 RefTypeDef <Ivl:2 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=0.00>
DefList: { }
N053 ( 3, 2) [000026] -----+----- * LCL_VAR ref V07 tmp5 u:2 NA (last use) REG NA $2c2
DefList: { }
N055 (???,???) [000038] ----------- * PUTARG_REG ref REG rcx
<RefPosition #34 @55 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #35 @55 RefTypeUse <Ivl:2 V07> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
Interval 11: ref RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #36 @56 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #37 @56 RefTypeDef <Ivl:11> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=0.00>
DefList: { N055.t38. PUTARG_REG }
N057 ( 1, 1) [000005] -----+----- * LCL_VAR int V01 arg1 u:1 NA (last use) REG NA $c0
DefList: { N055.t38. PUTARG_REG }
N059 (???,???) [000039] ----------- * PUTARG_REG int REG rdx
Last use of V01 between PUTARG and CALL. Removing occupied arg regs from preferences: [rcx]
<RefPosition #38 @59 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #39 @59 RefTypeUse <Ivl:1 V01> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=400.00>
Interval 12: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #40 @60 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #41 @60 RefTypeDef <Ivl:12> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=0.00>
DefList: { N055.t38. PUTARG_REG; N059.t39. PUTARG_REG }
N061 ( 3, 10) [000040] Hc--------- * CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
Contained
DefList: { N055.t38. PUTARG_REG; N059.t39. PUTARG_REG }
N063 ( 5, 12) [000041] nc--G------ * IND long REG NA
Contained
DefList: { N055.t38. PUTARG_REG; N059.t39. PUTARG_REG }
N065 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA $VN.Void
<RefPosition #42 @65 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #43 @65 RefTypeUse <Ivl:11> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #44 @65 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #45 @65 RefTypeUse <Ivl:12> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #46 @66 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11 mm0-mm5] minReg=1>
CHECKING LAST USES for BB03, liveout={}
==============================
use: {V01}
def: {V07}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) byref RefPositions {#0@0 #5@19} physReg:rcx Preferences=[rcx] Aversions=[allMask] RelatedInterval <V08/L3>
Interval 1: (V01) int RefPositions {#1@0 #3@9 #7@25 #39@59} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Aversions=[rax rcx rdx r8-r11 mm0-mm5]
Interval 2: (V07) ref RefPositions {#33@52 #35@55} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 3: (V08) long RefPositions {#6@20 #9@29} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 4: long RefPositions {#8@26 #10@29} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 5: float RefPositions {#11@30 #13@31} physReg:NA Preferences=[mm0] Aversions=[allMask]
Interval 6: int (constant) RefPositions {#15@38 #17@39} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 7: int RefPositions {#19@40 #26@49} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 8: long (constant) RefPositions {#20@42 #22@43} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 9: long RefPositions {#24@44 #28@49} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 10: ref RefPositions {#31@50 #32@51} physReg:NA Preferences=[rax] Aversions=[allMask] RelatedInterval <V07/L2>
Interval 11: ref RefPositions {#37@56 #43@65} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 12: int RefPositions {#41@60 #45@65} physReg:NA Preferences=[rdx] Aversions=[allMask]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @1 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=400.00>
<RefPosition #4 @13 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #5 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=600.00>
<RefPosition #6 @20 RefTypeDef <Ivl:3 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #7 @25 RefTypeUse <Ivl:1 V01> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #8 @26 RefTypeDef <Ivl:4> CAST BB04 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #9 @29 RefTypeUse <Ivl:3 V08> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #10 @29 RefTypeUse <Ivl:4> BB04 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #11 @30 RefTypeDef <Ivl:5> IND BB04 regmask=[mm0] minReg=1 wt=400.00>
<RefPosition #12 @31 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #13 @31 RefTypeUse <Ivl:5> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
<RefPosition #14 @33 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=0.00>
<RefPosition #15 @38 RefTypeDef <Ivl:6> CNS_INT BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #16 @39 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #17 @39 RefTypeUse <Ivl:6> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #18 @40 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #19 @40 RefTypeDef <Ivl:7> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=0.00>
<RefPosition #20 @42 RefTypeDef <Ivl:8> CNS_INT BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #21 @43 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #22 @43 RefTypeUse <Ivl:8> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #23 @44 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #24 @44 RefTypeDef <Ivl:9> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=0.00>
<RefPosition #25 @49 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #26 @49 RefTypeUse <Ivl:7> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #27 @49 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #28 @49 RefTypeUse <Ivl:9> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #29 @50 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11 mm0-mm5] minReg=1>
<RefPosition #30 @50 RefTypeFixedReg <Reg:rax> BB03 regmask=[rax] minReg=1 wt=0.00>
<RefPosition #31 @50 RefTypeDef <Ivl:10> CALL BB03 regmask=[rax] minReg=1 fixed wt=0.00>
<RefPosition #32 @51 RefTypeUse <Ivl:10> BB03 regmask=[allInt] minReg=1 last wt=0.00>
<RefPosition #33 @52 RefTypeDef <Ivl:2 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=0.00>
<RefPosition #34 @55 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #35 @55 RefTypeUse <Ivl:2 V07> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #36 @56 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #37 @56 RefTypeDef <Ivl:11> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=0.00>
<RefPosition #38 @59 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #39 @59 RefTypeUse <Ivl:1 V01> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=400.00>
<RefPosition #40 @60 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #41 @60 RefTypeDef <Ivl:12> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=0.00>
<RefPosition #42 @65 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #43 @65 RefTypeUse <Ivl:11> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #44 @65 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #45 @65 RefTypeUse <Ivl:12> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #46 @66 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11 mm0-mm5] minReg=1>
------------
REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval)
------------
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #5 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=600.00>
-----------------
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=400.00>
<RefPosition #7 @25 RefTypeUse <Ivl:1 V01> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #39 @59 RefTypeUse <Ivl:1 V01> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=400.00>
-----------------
<RefPosition #6 @20 RefTypeDef <Ivl:3 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #9 @29 RefTypeUse <Ivl:3 V08> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=400.00>
-----------------
<RefPosition #33 @52 RefTypeDef <Ivl:2 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=0.00>
<RefPosition #35 @55 RefTypeUse <Ivl:2 V07> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00 V01
BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V01(L1)
N007. CNS_INT 1
N009. CMP
Use:<V01/L1>(#3)
N011. JCC cond=ULE
BB04 [0003] [013..022) (return), preds={BB01} succs={}
=====
N015. IL_OFFSET INLRT @ 0x013[E-]
N017. V00(L0)
N019. V08(L3)
Use:<V00/L0>(#5) *
Def:<V08/L3>(#6)
N021. V08(L3)
N023. V01(L1)
N025. CAST
Use:<V01/L1>(#7) *
Def:<I4>(#8)
N027. LEA(b+(i*4)+0)
N029. IND
Use:<V08/L3>(#9) *
Use:<I4>(#10) *
Def:<I5>(#11)
N031. RETURN
Use:<I5>(#13) Fixed:mm0(#12) *
BB03 [0002] [008..013) (throw), preds={BB01} succs={}
=====
N035. IL_OFFSET INLRT @ 0x008[E-]
N037. CNS_INT 1
Def:<I6>(#15)
N039. PUTARG_REG
Use:<I6>(#17) Fixed:rcx(#16) *
Def:<I7>(#19) rcx
N041. CNS_INT(h) 0x7ff7f1188938 scope
Def:<I8>(#20)
N043. PUTARG_REG
Use:<I8>(#22) Fixed:rdx(#21) *
Def:<I9>(#24) rdx
N045. CNS_INT(h) 0x7ff7f0e0d9c8 ftn
N047. IND
N049. CALL help
Use:<I7>(#26) Fixed:rcx(#25) *
Use:<I9>(#28) Fixed:rdx(#27) *
Kill: [rax rcx rdx r8-r11 mm0-mm5]
Def:<I10>(#31) rax Pref:<V07/L2>
N051. V07(L2)
Use:<I10>(#32) *
Def:<V07/L2>(#33)
N053. V07(L2)
N055. PUTARG_REG
Use:<V07/L2>(#35) Fixed:rcx(#34) *
Def:<I11>(#37) rcx
N057. V01(L1)
N059. PUTARG_REG
Use:<V01/L1>(#39) Fixed:rdx(#38) *
Def:<I12>(#41) rdx
N061. CNS_INT(h) 0x7ff7f13342a0 ftn
N063. IND
N065. CALL
Use:<I11>(#43) Fixed:rcx(#42) *
Use:<I12>(#45) Fixed:rdx(#44) *
Kill: [rax rcx rdx r8-r11 mm0-mm5]
Linear scan intervals after buildIntervals:
Interval 0: (V00) byref RefPositions {#0@0 #5@19} physReg:rcx Preferences=[rcx] Aversions=[allMask] RelatedInterval <V08/L3>
Interval 1: (V01) int RefPositions {#1@0 #3@9 #7@25 #39@59} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Aversions=[rax rcx rdx r8-r11 mm0-mm5]
Interval 2: (V07) ref RefPositions {#33@52 #35@55} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 3: (V08) long RefPositions {#6@20 #9@29} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 4: long RefPositions {#8@26 #10@29} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 5: float RefPositions {#11@30 #13@31} physReg:NA Preferences=[mm0] Aversions=[allMask]
Interval 6: int (constant) RefPositions {#15@38 #17@39} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 7: int RefPositions {#19@40 #26@49} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 8: long (constant) RefPositions {#20@42 #22@43} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 9: long RefPositions {#24@44 #28@49} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 10: ref RefPositions {#31@50 #32@51} physReg:NA Preferences=[rax] Aversions=[allMask] RelatedInterval <V07/L2>
Interval 11: ref RefPositions {#37@56 #43@65} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 12: int RefPositions {#41@60 #45@65} physReg:NA Preferences=[rdx] Aversions=[allMask]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) byref RefPositions {#0@0 #5@19} physReg:rcx Preferences=[rcx] Aversions=[allMask] RelatedInterval <V08/L3>
Interval 1: (V01) int RefPositions {#1@0 #3@9 #7@25 #39@59} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Aversions=[rax rcx rdx r8-r11 mm0-mm5]
Interval 2: (V07) ref RefPositions {#33@52 #35@55} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 3: (V08) long RefPositions {#6@20 #9@29} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 4: long RefPositions {#8@26 #10@29} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 5: float RefPositions {#11@30 #13@31} physReg:NA Preferences=[mm0] Aversions=[allMask]
Interval 6: int (constant) RefPositions {#15@38 #17@39} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 7: int RefPositions {#19@40 #26@49} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 8: long (constant) RefPositions {#20@42 #22@43} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 9: long RefPositions {#24@44 #28@49} physReg:NA Preferences=[rdx] Aversions=[allMask]
Interval 10: ref RefPositions {#31@50 #32@51} physReg:NA Preferences=[rax] Aversions=[allMask] RelatedInterval <V07/L2>
Interval 11: ref RefPositions {#37@56 #43@65} physReg:NA Preferences=[rcx] Aversions=[allMask]
Interval 12: int RefPositions {#41@60 #45@65} physReg:NA Preferences=[rdx] Aversions=[allMask]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @1 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=400.00>
<RefPosition #4 @13 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #5 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=600.00>
<RefPosition #6 @20 RefTypeDef <Ivl:3 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #7 @25 RefTypeUse <Ivl:1 V01> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #8 @26 RefTypeDef <Ivl:4> CAST BB04 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #9 @29 RefTypeUse <Ivl:3 V08> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #10 @29 RefTypeUse <Ivl:4> BB04 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #11 @30 RefTypeDef <Ivl:5> IND BB04 regmask=[mm0] minReg=1 wt=400.00>
<RefPosition #12 @31 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #13 @31 RefTypeUse <Ivl:5> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
<RefPosition #14 @33 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=0.00>
<RefPosition #15 @38 RefTypeDef <Ivl:6> CNS_INT BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #16 @39 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #17 @39 RefTypeUse <Ivl:6> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #18 @40 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #19 @40 RefTypeDef <Ivl:7> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=0.00>
<RefPosition #20 @42 RefTypeDef <Ivl:8> CNS_INT BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #21 @43 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #22 @43 RefTypeUse <Ivl:8> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #23 @44 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #24 @44 RefTypeDef <Ivl:9> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=0.00>
<RefPosition #25 @49 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #26 @49 RefTypeUse <Ivl:7> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #27 @49 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #28 @49 RefTypeUse <Ivl:9> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #29 @50 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11 mm0-mm5] minReg=1>
<RefPosition #30 @50 RefTypeFixedReg <Reg:rax> BB03 regmask=[rax] minReg=1 wt=0.00>
<RefPosition #31 @50 RefTypeDef <Ivl:10> CALL BB03 regmask=[rax] minReg=1 fixed wt=0.00>
<RefPosition #32 @51 RefTypeUse <Ivl:10> BB03 regmask=[allInt] minReg=1 last wt=0.00>
<RefPosition #33 @52 RefTypeDef <Ivl:2 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=0.00>
<RefPosition #34 @55 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #35 @55 RefTypeUse <Ivl:2 V07> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #36 @56 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #37 @56 RefTypeDef <Ivl:11> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=0.00>
<RefPosition #38 @59 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #39 @59 RefTypeUse <Ivl:1 V01> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=400.00>
<RefPosition #40 @60 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #41 @60 RefTypeDef <Ivl:12> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=0.00>
<RefPosition #42 @65 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #43 @65 RefTypeUse <Ivl:11> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #44 @65 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #45 @65 RefTypeUse <Ivl:12> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #46 @66 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11 mm0-mm5] minReg=1>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #5 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=600.00>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rdx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=400.00>
<RefPosition #7 @25 RefTypeUse <Ivl:1 V01> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #39 @59 RefTypeUse <Ivl:1 V01> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=400.00>
--- V02
--- V03
--- V04
--- V05
--- V06
--- V07 (Interval 2)
<RefPosition #33 @52 RefTypeDef <Ivl:2 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 wt=0.00>
<RefPosition #35 @55 RefTypeUse <Ivl:2 V07> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
--- V08 (Interval 3)
<RefPosition #6 @20 RefTypeDef <Ivl:3 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #9 @29 RefTypeUse <Ivl:3 V08> LCL_VAR BB04 regmask=[allInt] minReg=1 last wt=400.00>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| |V00a|V01a| | | | | | | | | | | |
0.#0 V00 Parm Keep rcx | |V00a|V01a| | | | | | | | | | | |
0.#1 V01 Parm ORDER(A) rbx | |V00a| |V01a| | | | | | | | | | |
1.#2 BB1 PredBB0 | |V00a| |V01a| | | | | | | | | | |
[000002] 9.#3 V01 Use Keep rbx | |V00a| |V01a| | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
13.#4 BB4 PredBB1 | |V00a| |V01a| | | | | | | | | | |
[000027] 19.#5 V00 Use * Keep rcx | |V00a| |V01a| | | | | | | | | | |
20.#6 V08 Def COVRS(A) rcx | |V08a| |V01a| | | | | | | | | | |
[000011] 25.#7 V01 Use * Keep rbx | |V08a| |V01i| | | | | | | | | | |
26.#8 I4 Def BSFIT(A) rdx | |V08a|I4 a|V01i| | | | | | | | | | |
[000016] 29.#9 V08 Use * Keep rcx | |V08a|I4 a|V01i| | | | | | | | | | |
29.#10 I4 Use * Keep rdx | |V08a|I4 a|V01i| | | | | | | | | | |
30.#11 I5 Def Alloc mm0 | | | |V01i| | | | | |I5 a| | | | |
[000017] 31.#12 mm0 Fixd Keep mm0 | | | |V01i| | | | | |I5 a| | | | |
31.#13 I5 Use * Keep mm0 | | | |V01i| | | | | |I5 a| | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
33.#14 BB3 PredBB1 | | | |V01a| | | | | | | | | | |
[000023] 38.#15 C6 Def Alloc rcx | |C6 a| |V01a| | | | | | | | | | |
[000034] 39.#16 rcx Fixd Keep rcx | |C6 a| |V01a| | | | | | | | | | |
39.#17 C6 Use * Keep rcx | |C6 a| |V01a| | | | | | | | | | |
40.#18 rcx Fixd Keep rcx | | | |V01a| | | | | | | | | | |
40.#19 I7 Def Alloc rcx | |I7 a| |V01a| | | | | | | | | | |
[000022] 42.#20 C8 Def Alloc rdx | |I7 a|C8 a|V01a| | | | | | | | | | |
[000035] 43.#21 rdx Fixd Keep rdx | |I7 a|C8 a|V01a| | | | | | | | | | |
43.#22 C8 Use * Keep rdx | |I7 a|C8 a|V01a| | | | | | | | | | |
44.#23 rdx Fixd Keep rdx | |I7 a| |V01a| | | | | | | | | | |
44.#24 I9 Def Alloc rdx | |I7 a|I9 a|V01a| | | | | | | | | | |
[000024] 49.#25 rcx Fixd Keep rcx | |I7 a|I9 a|V01a| | | | | | | | | | |
49.#26 I7 Use * Keep rcx | |I7 a|I9 a|V01a| | | | | | | | | | |
49.#27 rdx Fixd Keep rdx | |I7 a|I9 a|V01a| | | | | | | | | | |
49.#28 I9 Use * Keep rdx | |I7 a|I9 a|V01a| | | | | | | | | | |
50.#29 Kill None [rax rcx rdx r8-r11 mm0-mm5]
| | | |V01a| | | | | | | | | | |
50.#30 rax Fixd Keep rax | | | |V01a| | | | | | | | | | |
50.#31 I10 Def Alloc rax |I10a| | |V01a| | | | | | | | | | |
[000025] 51.#32 I10 Use * Keep rax |I10a| | |V01a| | | | | | | | | | |
52.#33 V07 Def BSFIT(A) rcx | |V07a| |V01a| | | | | | | | | | |
[000038] 55.#34 rcx Fixd Keep rcx | |V07a| |V01a| | | | | | | | | | |
55.#35 V07 Use * Keep rcx | |V07a| |V01a| | | | | | | | | | |
56.#36 rcx Fixd Keep rcx | | | |V01a| | | | | | | | | | |
56.#37 I11 Def Alloc rcx | |I11a| |V01a| | | | | | | | | | |
[000039] 59.#38 rdx Fixd Keep rdx | |I11a| |V01a| | | | | | | | | | |
59.#39 V01 Use * Copy rdx | |I11a|V01a|V01a| | | | | | | | | | |
60.#40 rdx Fixd Keep rdx | |I11a| | | | | | | | | | | | |
60.#41 I12 Def Alloc rdx | |I11a|I12a| | | | | | | | | | | |
[000006] 65.#42 rcx Fixd Keep rcx | |I11a|I12a| | | | | | | | | | | |
65.#43 I11 Use * Keep rcx | |I11a|I12a| | | | | | | | | | | |
65.#44 rdx Fixd Keep rdx | |I11a|I12a| | | | | | | | | | | |
65.#45 I12 Use * Keep rdx | |I11a|I12a| | | | | | | | | | | |
66.#46 Kill None [rax rcx rdx r8-r11 mm0-mm5]
| | | | | | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rbx] minReg=1 regOptional wt=100.00>
<RefPosition #2 @1 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rbx] minReg=1 regOptional wt=400.00>
<RefPosition #4 @13 RefTypeBB BB04 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #5 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[rcx] minReg=1 last wt=600.00>
<RefPosition #6 @20 RefTypeDef <Ivl:3 V08> STORE_LCL_VAR BB04 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #7 @25 RefTypeUse <Ivl:1 V01> LCL_VAR BB04 regmask=[rbx] minReg=1 last regOptional wt=400.00>
<RefPosition #8 @26 RefTypeDef <Ivl:4> CAST BB04 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #9 @29 RefTypeUse <Ivl:3 V08> LCL_VAR BB04 regmask=[rcx] minReg=1 last wt=400.00>
<RefPosition #10 @29 RefTypeUse <Ivl:4> BB04 regmask=[rdx] minReg=1 last wt=100.00>
<RefPosition #11 @30 RefTypeDef <Ivl:5> IND BB04 regmask=[mm0] minReg=1 wt=400.00>
<RefPosition #12 @31 RefTypeFixedReg <Reg:mm0> BB04 regmask=[mm0] minReg=1 wt=100.00>
<RefPosition #13 @31 RefTypeUse <Ivl:5> BB04 regmask=[mm0] minReg=1 last fixed wt=100.00>
<RefPosition #14 @33 RefTypeBB BB03 regmask=[allMask] minReg=1 wt=0.00>
<RefPosition #15 @38 RefTypeDef <Ivl:6> CNS_INT BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #16 @39 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #17 @39 RefTypeUse <Ivl:6> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #18 @40 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #19 @40 RefTypeDef <Ivl:7> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=0.00>
<RefPosition #20 @42 RefTypeDef <Ivl:8> CNS_INT BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #21 @43 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #22 @43 RefTypeUse <Ivl:8> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #23 @44 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #24 @44 RefTypeDef <Ivl:9> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=0.00>
<RefPosition #25 @49 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #26 @49 RefTypeUse <Ivl:7> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #27 @49 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #28 @49 RefTypeUse <Ivl:9> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #29 @50 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11 mm0-mm5] minReg=1>
<RefPosition #30 @50 RefTypeFixedReg <Reg:rax> BB03 regmask=[rax] minReg=1 wt=0.00>
<RefPosition #31 @50 RefTypeDef <Ivl:10> CALL BB03 regmask=[rax] minReg=1 fixed wt=0.00>
<RefPosition #32 @51 RefTypeUse <Ivl:10> BB03 regmask=[rax] minReg=1 last wt=0.00>
<RefPosition #33 @52 RefTypeDef <Ivl:2 V07> STORE_LCL_VAR BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #34 @55 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #35 @55 RefTypeUse <Ivl:2 V07> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #36 @56 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #37 @56 RefTypeDef <Ivl:11> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=0.00>
<RefPosition #38 @59 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #39 @59 RefTypeUse <Ivl:1 V01> LCL_VAR BB03 regmask=[rdx] minReg=1 last copy fixed wt=400.00>
<RefPosition #40 @60 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #41 @60 RefTypeDef <Ivl:12> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=0.00>
<RefPosition #42 @65 RefTypeFixedReg <Reg:rcx> BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #43 @65 RefTypeUse <Ivl:11> BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
<RefPosition #44 @65 RefTypeFixedReg <Reg:rdx> BB03 regmask=[rdx] minReg=1 wt=0.00>
<RefPosition #45 @65 RefTypeUse <Ivl:12> BB03 regmask=[rdx] minReg=1 last fixed wt=0.00>
<RefPosition #46 @66 RefTypeKill BB03 regmask=[rax rcx rdx r8-r11 mm0-mm5] minReg=1>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #5 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[rcx] minReg=1 last wt=600.00>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[rbx] minReg=1 regOptional wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rbx] minReg=1 regOptional wt=400.00>
<RefPosition #7 @25 RefTypeUse <Ivl:1 V01> LCL_VAR BB04 regmask=[rbx] minReg=1 last regOptional wt=400.00>
<RefPosition #39 @59 RefTypeUse <Ivl:1 V01> LCL_VAR BB03 regmask=[rdx] minReg=1 last copy fixed wt=400.00>
--- V02
--- V03
--- V04
--- V05
--- V06
--- V07 (Interval 2)
<RefPosition #33 @52 RefTypeDef <Ivl:2 V07> STORE_LCL_VAR BB03 regmask=[rcx] minReg=1 wt=0.00>
<RefPosition #35 @55 RefTypeUse <Ivl:2 V07> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed wt=0.00>
--- V08 (Interval 3)
<RefPosition #6 @20 RefTypeDef <Ivl:3 V08> STORE_LCL_VAR BB04 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #9 @29 RefTypeUse <Ivl:3 V08> LCL_VAR BB04 regmask=[rcx] minReg=1 last wt=400.00>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V01}
Has No Critical Edges
Prior to Resolution
BB01
use: {V01}
def: {}
in: {V00 V01}
out: {V00 V01}
Var=Reg beg of BB01: V00=rcx V01=rbx
Var=Reg end of BB01: V00=rcx V01=rbx
BB03
use: {V01}
def: {V07}
in: {V01}
out: {}
Var=Reg beg of BB03: V01=rbx
Var=Reg end of BB03: none
BB04
use: {V00 V01}
def: {V08}
in: {V00 V01}
out: {}
Var=Reg beg of BB04: V00=rcx V01=rbx
Var=Reg end of BB04: none
RESOLVING EDGES
Set V00 argument initial register to rcx
Set V01 argument initial register to rbx
Trees after linear scan register allocator (LSRA)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
N003 (???,???) [000031] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 rbx REG rbx $c0
N007 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
N009 ( 3, 3) [000002] -----+-N-U- * CMP void REG NA
N011 ( 5, 5) [000003] -----+----- JCC void cond=ULE REG NA
------------ BB03 [0002] [008..013) (throw), preds={BB01} succs={}
N035 (???,???) [000032] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
N037 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 REG rcx $41
/--* t23 int
N039 (???,???) [000034] ----------- t34 = * PUTARG_REG int REG rcx
N041 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope REG rdx $340
/--* t22 long
N043 (???,???) [000035] ----------- t35 = * PUTARG_REG long REG rdx
N045 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn REG NA
/--* t36 long
N047 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
N049 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS REG rax $2c2
/--* t24 ref
N051 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 rcx REG rcx $VN.Void
N053 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 rcx (last use) REG rcx $2c2
/--* t26 ref
N055 (???,???) [000038] ----------- t38 = * PUTARG_REG ref REG rcx
N057 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t5 int
N059 (???,???) [000039] ----------- t39 = * PUTARG_REG int REG rdx
N061 ( 3, 10) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t40 long
N063 ( 5, 12) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 ref arg0 rcx
+--* t39 int arg1 rdx
+--* t41 long control expr
N065 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA $VN.Void
------------ BB04 [0003] [013..022) (return), preds={BB01} succs={}
N015 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
N017 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80
/--* t8 byref
N019 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 rcx REG rcx $VN.Void
N021 ( 1, 1) [000028] -----+----- t28 = LCL_VAR long V08 tmp6 u:1 rcx (last use) REG rcx $180
N023 ( 1, 1) [000010] -----+----- t10 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t10 int
N025 ( 2, 3) [000011] -----+---U- t11 = * CAST long <- uint REG rdx $181
/--* t28 long
+--* t11 long
N027 ( 5, 8) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
N029 ( 6, 6) [000016] -A-XG+----- t16 = * IND float REG mm0 <l:$301, c:$300>
/--* t16 float
N031 ( 7, 7) [000017] -A-XG+----- * RETURN float REG NA $2c1
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0.#0 V00 Parm Alloc rcx | |V00a| | | | | | | | | | | | |
0.#1 V01 Parm Alloc rbx | |V00a| |V01a| | | | | | | | | | |
1.#2 BB1 PredBB0 | |V00a| |V01a| | | | | | | | | | |
[000002] 9.#3 V01 Use Keep rbx | |V00a| |V01a| | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
13.#4 BB4 PredBB1 | |V00a| |V01a| | | | | | | | | | |
[000027] 19.#5 V00 Use * Keep rcx | |V00i| |V01a| | | | | | | | | | |
20.#6 V08 Def Alloc rcx | |V08a| |V01a| | | | | | | | | | |
[000011] 25.#7 V01 Use * Keep rbx | |V08a| |V01i| | | | | | | | | | |
26.#8 I4 Def Alloc rdx | |V08a|I4 a| | | | | | | | | | | |
[000016] 29.#9 V08 Use * Keep rcx | |V08i|I4 a| | | | | | | | | | | |
29.#10 I4 Use * Keep rdx | | |I4 i| | | | | | | | | | | |
30.#11 I5 Def Alloc mm0 | | | | | | | | | |I5 a| | | | |
[000017] 31.#12 mm0 Fixd Keep mm0 | | | | | | | | | |I5 a| | | | |
31.#13 I5 Use * Keep mm0 | | | | | | | | | |I5 i| | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
33.#14 BB3 PredBB1 | | | |V01a| | | | | | | | | | |
[000023] 38.#15 C6 Def Alloc rcx | |C6 a| |V01a| | | | | | | | | | |
[000034] 39.#16 rcx Fixd Keep rcx | |C6 a| |V01a| | | | | | | | | | |
39.#17 C6 Use * Keep rcx | |C6 i| |V01a| | | | | | | | | | |
40.#18 rcx Fixd Keep rcx | | | |V01a| | | | | | | | | | |
40.#19 I7 Def Alloc rcx | |I7 a| |V01a| | | | | | | | | | |
[000022] 42.#20 C8 Def Alloc rdx | |I7 a|C8 a|V01a| | | | | | | | | | |
[000035] 43.#21 rdx Fixd Keep rdx | |I7 a|C8 a|V01a| | | | | | | | | | |
43.#22 C8 Use * Keep rdx | |I7 a|C8 i|V01a| | | | | | | | | | |
44.#23 rdx Fixd Keep rdx | |I7 a| |V01a| | | | | | | | | | |
44.#24 I9 Def Alloc rdx | |I7 a|I9 a|V01a| | | | | | | | | | |
[000024] 49.#25 rcx Fixd Keep rcx | |I7 a|I9 a|V01a| | | | | | | | | | |
49.#26 I7 Use * Keep rcx | |I7 i|I9 a|V01a| | | | | | | | | | |
49.#27 rdx Fixd Keep rdx | | |I9 a|V01a| | | | | | | | | | |
49.#28 I9 Use * Keep rdx | | |I9 i|V01a| | | | | | | | | | |
50.#29 Kill None [rax rcx rdx r8-r11 mm0-mm5]
| | | |V01a| | | | | | | | | | |
50.#30 rax Fixd Keep rax | | | |V01a| | | | | | | | | | |
50.#31 I10 Def Alloc rax |I10a| | |V01a| | | | | | | | | | |
[000025] 51.#32 I10 Use * Keep rax |I10i| | |V01a| | | | | | | | | | |
52.#33 V07 Def Alloc rcx | |V07a| |V01a| | | | | | | | | | |
[000038] 55.#34 rcx Fixd Keep rcx | |V07a| |V01a| | | | | | | | | | |
55.#35 V07 Use * Keep rcx | |V07i| |V01a| | | | | | | | | | |
56.#36 rcx Fixd Keep rcx | | | |V01a| | | | | | | | | | |
56.#37 I11 Def Alloc rcx | |I11a| |V01a| | | | | | | | | | |
[000039] 59.#38 rdx Fixd Keep rdx | |I11a| |V01a| | | | | | | | | | |
59.#39 V01 Use * Copy rdx | |I11a|V01i|V01i| | | | | | | | | | |
60.#40 rdx Fixd Keep rdx | |I11a| | | | | | | | | | | | |
60.#41 I12 Def Alloc rdx | |I11a|I12a| | | | | | | | | | | |
[000006] 65.#42 rcx Fixd Keep rcx | |I11a|I12a| | | | | | | | | | | |
65.#43 I11 Use * Keep rcx | |I11i|I12a| | | | | | | | | | | |
65.#44 rdx Fixd Keep rdx | | |I12a| | | | | | | | | | | |
65.#45 I12 Use * Keep rdx | | |I12i| | | | | | | | | | | |
66.#46 Kill None [rax rcx rdx r8-r11 mm0-mm5]
| | | | | | | | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars: 4
Total Reg Cand Vars: 4
Total number of Intervals: 12
Total number of RefPositions: 46
Total Number of spill temps created: 0
..........
BB00 [ 100.00]: REG_ORDER = 1
BB03 [ 0.00]: BEST_FIT = 1
BB04 [ 2.00]: COVERS = 1, BEST_FIT = 1
..........
Total SpillCount : 0 Weighted: 0.000000
Total CopyReg : 0 Weighted: 0.000000
Total ResolutionMovs : 0 Weighted: 0.000000
Total SplitEdges : 0 Weighted: 0.000000
..........
Total COVERS [# 4] : 1 Weighted: 2.000000
Total BEST_FIT [#11] : 2 Weighted: 2.000000
Total REG_ORDER [#13] : 1 Weighted: 100.000000
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(rcx) V01(rdx=>rbx)
BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V01(rbx)
N007. CNS_INT 1
N009. CMP ; rbx
N011. JCC cond=ULE
Var=Reg end of BB01: V00=rcx V01=rbx
BB04 [0003] [013..022) (return), preds={BB01} succs={}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB04: V00=rcx V01=rbx
N015. IL_OFFSET INLRT @ 0x013[E-]
N017. V00(rcx*)
* N019. V08(rcx); rcx*
N021. V08(rcx*)
N023. V01(rbx*)
N025. rdx = CAST ; rbx*
N027. STK = LEA(b+(i*4)+0); rcx*,rdx
N029. mm0 = IND ; STK
N031. RETURN ; mm0
Var=Reg end of BB04: none
BB03 [0002] [008..013) (throw), preds={BB01} succs={}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB03: V01=rbx
N035. IL_OFFSET INLRT @ 0x008[E-]
N037. rcx = CNS_INT 1
N039. rcx = PUTARG_REG; rcx
N041. rdx = CNS_INT(h) 0x7ff7f1188938 scope
N043. rdx = PUTARG_REG; rdx
N045. CNS_INT(h) 0x7ff7f0e0d9c8 ftn
N047. IND
N049. rax = CALL help; rcx,rdx
* N051. V07(rcx); rax
N053. V07(rcx*)
N055. rcx = PUTARG_REG; rcx*
N057. V01(rbx*)
N059. rdx = PUTARG_REG; rbx*
N061. CNS_INT(h) 0x7ff7f13342a0 ftn
N063. IND
N065. CALL ; rcx,rdx
Var=Reg end of BB03: none
*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
N003 (???,???) [000031] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 rbx REG rbx $c0
N007 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
N009 ( 3, 3) [000002] -----+-N-U- * CMP void REG NA
N011 ( 5, 5) [000003] -----+----- JCC void cond=ULE REG NA
------------ BB03 [0002] [008..013) (throw), preds={BB01} succs={}
N035 (???,???) [000032] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
N037 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 REG rcx $41
/--* t23 int
N039 (???,???) [000034] ----------- t34 = * PUTARG_REG int REG rcx
N041 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope REG rdx $340
/--* t22 long
N043 (???,???) [000035] ----------- t35 = * PUTARG_REG long REG rdx
N045 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn REG NA
/--* t36 long
N047 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
N049 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS REG rax $2c2
/--* t24 ref
N051 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 rcx REG rcx $VN.Void
N053 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 rcx (last use) REG rcx $2c2
/--* t26 ref
N055 (???,???) [000038] ----------- t38 = * PUTARG_REG ref REG rcx
N057 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t5 int
N059 (???,???) [000039] ----------- t39 = * PUTARG_REG int REG rdx
N061 ( 3, 10) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t40 long
N063 ( 5, 12) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 ref arg0 rcx
+--* t39 int arg1 rdx
+--* t41 long control expr
N065 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA $VN.Void
------------ BB04 [0003] [013..022) (return), preds={BB01} succs={}
N015 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
N017 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80
/--* t8 byref
N019 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 rcx REG rcx $VN.Void
N021 ( 1, 1) [000028] -----+----- t28 = LCL_VAR long V08 tmp6 u:1 rcx (last use) REG rcx $180
N023 ( 1, 1) [000010] -----+----- t10 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t10 int
N025 ( 2, 3) [000011] -----+---U- t11 = * CAST long <- uint REG rdx $181
/--* t28 long
+--* t11 long
N027 ( 5, 8) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
N029 ( 6, 6) [000016] -A-XG+----- t16 = * IND float REG mm0 <l:$301, c:$300>
/--* t16 float
N031 ( 7, 7) [000017] -A-XG+----- * RETURN float REG NA $2c1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (3 profiled blocks, 0 unprofiled)
*************** Starting PHASE Optimize layout
*************** In fgSearchImprovedLayout()
Initial BasicBlocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Not enough blocks to partition anything. Skipping reordering.
Reordering block list
*************** Finishing PHASE Optimize layout
Trees after Optimize layout
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB04(1),BB03(0) ( cond ) i LIR IBC
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB04(1),BB03(0) (cond), preds={} succs={BB03,BB04}
N003 (???,???) [000031] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 rbx REG rbx $c0
N007 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
N009 ( 3, 3) [000002] -----+-N-U- * CMP void REG NA
N011 ( 5, 5) [000003] -----+----- JCC void cond=ULE REG NA
------------ BB04 [0003] [013..022) (return), preds={BB01} succs={}
N015 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
N017 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80
/--* t8 byref
N019 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 rcx REG rcx $VN.Void
N021 ( 1, 1) [000028] -----+----- t28 = LCL_VAR long V08 tmp6 u:1 rcx (last use) REG rcx $180
N023 ( 1, 1) [000010] -----+----- t10 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t10 int
N025 ( 2, 3) [000011] -----+---U- t11 = * CAST long <- uint REG rdx $181
/--* t28 long
+--* t11 long
N027 ( 5, 8) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
N029 ( 6, 6) [000016] -A-XG+----- t16 = * IND float REG mm0 <l:$301, c:$300>
/--* t16 float
N031 ( 7, 7) [000017] -A-XG+----- * RETURN float REG NA $2c1
------------ BB03 [0002] [008..013) (throw), preds={BB01} succs={}
N035 (???,???) [000032] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
N037 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 REG rcx $41
/--* t23 int
N039 (???,???) [000034] ----------- t34 = * PUTARG_REG int REG rcx
N041 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope REG rdx $340
/--* t22 long
N043 (???,???) [000035] ----------- t35 = * PUTARG_REG long REG rdx
N045 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn REG NA
/--* t36 long
N047 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
N049 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS REG rax $2c2
/--* t24 ref
N051 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 rcx REG rcx $VN.Void
N053 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 rcx (last use) REG rcx $2c2
/--* t26 ref
N055 (???,???) [000038] ----------- t38 = * PUTARG_REG ref REG rcx
N057 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t5 int
N059 (???,???) [000039] ----------- t39 = * PUTARG_REG int REG rdx
N061 ( 3, 10) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t40 long
N063 ( 5, 12) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 ref arg0 rcx
+--* t39 int arg1 rdx
+--* t41 long control expr
N065 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (3 profiled blocks, 0 unprofiled)
*************** Starting PHASE Optimize post-layout
*************** Finishing PHASE Optimize post-layout
Trees after Optimize post-layout
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB04(1) ( cond ) i LIR IBC
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..004) -> BB03(0),BB04(1) (cond), preds={} succs={BB04,BB03}
N003 (???,???) [000031] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 rbx REG rbx $c0
N007 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
N009 ( 3, 3) [000002] -----+-N-U- * CMP void REG NA
N011 ( 5, 5) [000003] -----+----- JCC void cond=UGT REG NA
------------ BB04 [0003] [013..022) (return), preds={BB01} succs={}
N015 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
N017 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80
/--* t8 byref
N019 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 rcx REG rcx $VN.Void
N021 ( 1, 1) [000028] -----+----- t28 = LCL_VAR long V08 tmp6 u:1 rcx (last use) REG rcx $180
N023 ( 1, 1) [000010] -----+----- t10 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t10 int
N025 ( 2, 3) [000011] -----+---U- t11 = * CAST long <- uint REG rdx $181
/--* t28 long
+--* t11 long
N027 ( 5, 8) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
N029 ( 6, 6) [000016] -A-XG+----- t16 = * IND float REG mm0 <l:$301, c:$300>
/--* t16 float
N031 ( 7, 7) [000017] -A-XG+----- * RETURN float REG NA $2c1
------------ BB03 [0002] [008..013) (throw), preds={BB01} succs={}
N035 (???,???) [000032] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
N037 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 REG rcx $41
/--* t23 int
N039 (???,???) [000034] ----------- t34 = * PUTARG_REG int REG rcx
N041 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope REG rdx $340
/--* t22 long
N043 (???,???) [000035] ----------- t35 = * PUTARG_REG long REG rdx
N045 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn REG NA
/--* t36 long
N047 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
N049 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS REG rax $2c2
/--* t24 ref
N051 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 rcx REG rcx $VN.Void
N053 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 rcx (last use) REG rcx $2c2
/--* t26 ref
N055 (???,???) [000038] ----------- t38 = * PUTARG_REG ref REG rcx
N057 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t5 int
N059 (???,???) [000039] ----------- t39 = * PUTARG_REG int REG rdx
N061 ( 3, 10) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t40 long
N063 ( 5, 12) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 ref arg0 rcx
+--* t39 int arg1 rdx
+--* t41 long control expr
N065 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Checking Profile Weights (flags:0x1c)
Profile is self-consistent (3 profiled blocks, 0 unprofiled)
*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block [no changes]
*************** Starting PHASE Place 'align' instructions
*************** In placeLoopAlignInstructions()
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 2]
01 -> BB03[2, 1]
02 -> BB04[1, 0]
Flow graph has no cycles; skipping identification of natural loops
Not checking for any loops as fgMightHaveNaturalLoops is false
*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB04(1) ( cond ) i LIR IBC
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare hascall gcsafe
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(rcx) V01(rbx)
Modified regs: [rax rcx rdx rbx r8-r11 mm0-mm5]
Callee-saved registers pushed: 1 [rbx]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Set V00 to offset 0
Set V01 to offset 8
Assign V02 OutArgs, size=32, stkOffs=-0x30
--- delta bump 8 for RA
--- delta bump 40 for RSP frame
--- virtual stack offset to actual stack offset delta is 48
-- V00 was 0, now 48
-- V01 was 8, now 56
-- V02 was -48, now 0
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 3, 6 ) byref -> rcx ld-addr-op single-def
; V01 arg1 [V01,T01] ( 5, 4 ) int -> rbx single-def
; V02 OutArgs [V02 ] ( 1, 1 ) struct (32) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <UNNAMED>
;* V03 tmp1 [V03 ] ( 0, 0 ) float -> zero-ref do-not-enreg[] "field V00.X (fldOffset=0x0)" P-DEP
;* V04 tmp2 [V04 ] ( 0, 0 ) float -> zero-ref do-not-enreg[] "field V00.Y (fldOffset=0x4)" P-DEP
;* V05 tmp3 [V05 ] ( 0, 0 ) float -> zero-ref do-not-enreg[] "field V00.Z (fldOffset=0x8)" P-DEP
;* V06 tmp4 [V06 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[S] "Promoted implicit byref" <Program.EntryPoint+Vector2>
; V07 tmp5 [V07,T03] ( 2, 0 ) ref -> rcx single-def "argument with side effect"
; V08 tmp6 [V08,T02] ( 2, 4 ) long -> rcx "Cast away GC"
;
; Lcl frame size = 32
Created:
G_M62292_IG02: ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
BB01 : first block
BB03 : branch target
*************** After genMarkLabelsForCodegen()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight IBC [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 2 [000..004)-> BB03(0),BB04(1) ( cond ) i LIR IBC label
BB04 [0003] 1 BB01 1 2 [013..022) (return) i LIR IBC
BB03 [0002] 1 BB01 0 0 [008..013) (throw ) i LIR IBC rare label hascall gcsafe
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
=============== Generating BB01 [0000] [000..004) -> BB03(0),BB04(1) (cond), preds={} succs={BB04,BB03} flags=0x00000000.00801011: i LIR IBC label
BB01 IN (2)={V00 V01} + ByrefExposed + GcHeap
OUT(2)={V00 V01} + ByrefExposed + GcHeap
Recording Var Locations at start of BB01
V00(rcx) V01(rbx)
Change life 0000000000000000 {} -> 0000000000000003 {V00 V01}
V00 in reg rcx is becoming live [------]
Live regs: 0000000000000000 {} + {rcx} => 0000000000000002 {rcx}
Debug: New V00 debug range: first
V01 in reg rbx is becoming live [------]
Live regs: 0000000000000002 {rcx} + {rbx} => 000000000000000A {rcx rbx}
Debug: New V01 debug range: first
Live regs: (unchanged) 000000000000000A {rcx rbx}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0002 {rcx}
L_M62292_BB01:
Label: G_M62292_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}
Scope info: begin block BB01, IL range [000..004)
Added IP mapping: 0x0000 STACK_EMPTY (G_M62292_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000031] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V01 arg1 u:1 rbx REG rbx $c0
Generating: N007 ( 1, 1) [000001] -c---+----- t1 = CNS_INT int 1 REG NA
/--* t0 int
+--* t1 int
Generating: N009 ( 3, 3) [000002] -----+-N-U- * CMP void REG NA
Mapped BB01 to G_M62292_IG02
IN0001: cmp ebx, 1
Generating: N011 ( 5, 5) [000003] -----+----- JCC void cond=UGT REG NA
IN0002: ja L_M62292_BB03
Variable Live Range History Dump for BB01
V00 arg0: rcx [(G_M62292_IG02,ins#0,ofs#0), ...]
V01 arg1: rbx [(G_M62292_IG02,ins#0,ofs#0), ...]
=============== Generating BB04 [0003] [013..022) (return), preds={BB01} succs={} flags=0x00000000.00800011: i LIR IBC
BB04 IN (2)={V00 V01} + ByrefExposed + GcHeap
OUT(0)={ }
Recording Var Locations at start of BB04
V00(rcx) V01(rbx)
Liveness not changing: 0000000000000003 {V00 V01}
Live regs: 0000000000000000 {} + {rcx rbx} => 000000000000000A {rcx rbx}
GC regs: (unchanged) 0000 {}
Byref regs: 0000 {} => 0002 {rcx}
L_M62292_BB04:
Scope info: begin block BB04, IL range [013..022)
Added IP mapping: 0x0013 STACK_EMPTY (G_M62292_IG02,ins#2,ofs#9) label
Generating: N015 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x013[E-] REG NA
Generating: N017 ( 1, 1) [000008] -----+----- t8 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80
/--* t8 byref
Generating: N019 ( 1, 3) [000027] DA---+----- * STORE_LCL_VAR long V08 tmp6 d:1 rcx REG rcx $VN.Void
V00 in reg rcx is becoming dead [000008]
Live regs: 000000000000000A {rcx rbx} - {rcx} => 0000000000000008 {rbx}
Debug: Closing V00 debug range.
Live vars after [000008]: {V00 V01} -{V00} => {V01}
Byref regs: 0002 {rcx} => 0000 {}
V08 in reg rcx is becoming live [000027]
Live regs: 0000000000000008 {rbx} + {rcx} => 000000000000000A {rcx rbx}
Live vars after [000027]: {V01} +{V08} => {V01 V08}
Generating: N021 ( 1, 1) [000028] -----+----- t28 = LCL_VAR long V08 tmp6 u:1 rcx (last use) REG rcx $180
Generating: N023 ( 1, 1) [000010] -----+----- t10 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t10 int
Generating: N025 ( 2, 3) [000011] -----+---U- t11 = * CAST long <- uint REG rdx $181
V01 in reg rbx is becoming dead [000010]
Live regs: 000000000000000A {rcx rbx} - {rbx} => 0000000000000002 {rcx}
Debug: Closing V01 debug range.
Live vars after [000010]: {V01 V08} -{V01} => {V08}
Mapped BB04 to G_M62292_IG02
IN0003: mov edx, ebx
/--* t28 long
+--* t11 long
Generating: N027 ( 5, 8) [000015] -c---+----- t15 = * LEA(b+(i*4)+0) long REG NA
/--* t15 long
Generating: N029 ( 6, 6) [000016] -A-XG+----- t16 = * IND float REG mm0 <l:$301, c:$300>
V08 in reg rcx is becoming dead [000028]
Live regs: 0000000000000002 {rcx} - {rcx} => 0000000000000000 {}
Live vars after [000028]: {V08} -{V08} => {}
IN0004: vmovss xmm0, dword ptr [rcx+4*rdx]
/--* t16 float
Generating: N031 ( 7, 7) [000017] -A-XG+----- * RETURN float REG NA $2c1
Added IP mapping: EPILOG (G_M62292_IG02,ins#4,ofs#16) label
Reserving epilog IG for block BB04
Saved:
G_M62292_IG02: ; offs=0x000000, size=0x0010, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], BB04 [0003], byref
Created:
G_M62292_IG03: ; offs=0x000010, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Created:
G_M62292_IG04: ; offs=0x000110, size=0x0000, bbWeight=1, gcrefRegs=0000 {}, epilog
*************** After placeholder IG creation
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62292_IG02: ; offs=0x000000, size=0x0010, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], BB04 [0003], byref
G_M62292_IG03: ; epilog placeholder, next placeholder=<END>, BB04 [0003], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0002 {rcx}
G_M62292_IG04: ; offs=0x000110, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Current IG
Variable Live Range History Dump for BB04
V00 arg0: rcx [(G_M62292_IG02,ins#0,ofs#0), (G_M62292_IG02,ins#2,ofs#9)]
V01 arg1: rbx [(G_M62292_IG02,ins#0,ofs#0), (G_M62292_IG02,ins#2,ofs#9)]
=============== Generating BB03 [0002] [008..013) (throw), preds={BB01} succs={} flags=0x00000000.02811811: i LIR IBC rare label hascall gcsafe
BB03 IN (1)={V01} + ByrefExposed + GcHeap
OUT(0)={ }
Recording Var Locations at start of BB03
V01(rbx)
Change life 0000000000000000 {} -> 0000000000000002 {V01}
V01 in reg rbx is becoming live [------]
Live regs: 0000000000000000 {} + {rbx} => 0000000000000008 {rbx}
Debug: New V01 debug range: new var or location
Live regs: (unchanged) 0000000000000008 {rbx}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M62292_BB03:
Label: G_M62292_IG04, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB03, IL range [008..013)
Added IP mapping: 0x0008 STACK_EMPTY (G_M62292_IG04,ins#0,ofs#0) label
Generating: N035 (???,???) [000032] ----------- IL_OFFSET void INLRT @ 0x008[E-] REG NA
Generating: N037 ( 1, 1) [000023] -----+----- t23 = CNS_INT int 1 REG rcx $41
Mapped BB03 to G_M62292_IG04
IN0005: mov ecx, 1
/--* t23 int
Generating: N039 (???,???) [000034] ----------- t34 = * PUTARG_REG int REG rcx
Generating: N041 ( 3, 10) [000022] H----+----- t22 = CNS_INT(h) long 0x7ff7f1188938 scope REG rdx $340
IN0006: mov rdx, 0x7FF7F1188938
/--* t22 long
Generating: N043 (???,???) [000035] ----------- t35 = * PUTARG_REG long REG rdx
Generating: N045 ( 3, 10) [000036] Hc--------- t36 = CNS_INT(h) long 0x7ff7f0e0d9c8 ftn REG NA
/--* t36 long
Generating: N047 ( 5, 12) [000037] nc--G------ t37 = * IND long REG NA
/--* t34 int arg0 rcx
+--* t35 long arg1 rdx
+--* t37 long control expr
Generating: N049 ( 18, 18) [000024] --C-G+----- t24 = * CALL help ref CORINFO_HELP_STRCNS REG rax $2c2
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0007: call [CORINFO_HELP_STRCNS]
GC regs: 0000 {} => 0001 {rax}
/--* t24 ref
Generating: N051 ( 22, 21) [000025] DAC-G+----- * STORE_LCL_VAR ref V07 tmp5 d:2 rcx REG rcx $VN.Void
GC regs: 0001 {rax} => 0000 {}
IN0008: mov rcx, rax
V07 in reg rcx is becoming live [000025]
Live regs: 0000000000000008 {rbx} + {rcx} => 000000000000000A {rcx rbx}
Live vars after [000025]: {V01} +{V07} => {V01 V07}
GC regs: 0000 {} => 0002 {rcx}
Generating: N053 ( 3, 2) [000026] -----+----- t26 = LCL_VAR ref V07 tmp5 u:2 rcx (last use) REG rcx $2c2
/--* t26 ref
Generating: N055 (???,???) [000038] ----------- t38 = * PUTARG_REG ref REG rcx
V07 in reg rcx is becoming dead [000026]
Live regs: 000000000000000A {rcx rbx} - {rcx} => 0000000000000008 {rbx}
Live vars after [000026]: {V01 V07} -{V07} => {V01}
GC regs: 0002 {rcx} => 0000 {}
GC regs: 0000 {} => 0002 {rcx}
Generating: N057 ( 1, 1) [000005] -----+----- t5 = LCL_VAR int V01 arg1 u:1 rbx (last use) REG rbx $c0
/--* t5 int
Generating: N059 (???,???) [000039] ----------- t39 = * PUTARG_REG int REG rdx
V01 in reg rbx is becoming dead [000005]
Live regs: 0000000000000008 {rbx} - {rbx} => 0000000000000000 {}
Debug: Closing V01 debug range.
Live vars after [000005]: {V01} -{V01} => {}
IN0009: mov edx, ebx
Generating: N061 ( 3, 10) [000040] Hc--------- t40 = CNS_INT(h) long 0x7ff7f13342a0 ftn REG NA
/--* t40 long
Generating: N063 ( 5, 12) [000041] nc--G------ t41 = * IND long REG NA
/--* t38 ref arg0 rcx
+--* t39 int arg1 rdx
+--* t41 long control expr
Generating: N065 ( 43, 31) [000006] -ACXG+----- * CALL void Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int) REG NA $VN.Void
GC regs: 0002 {rcx} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN000a: call [Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)]
IN000b: int3
Variable Live Range History Dump for BB03
V01 arg1: rbx [(G_M62292_IG04,ins#0,ofs#0), (G_M62292_IG04,ins#4,ofs#24)]
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 55, compSizeEstimate = 43 Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 3, 6 ) byref -> rcx ld-addr-op single-def
; V01 arg1 [V01,T01] ( 5, 4 ) int -> rbx single-def
; V02 OutArgs [V02 ] ( 1, 1 ) struct (32) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <UNNAMED>
;* V03 tmp1 [V03 ] ( 0, 0 ) float -> zero-ref do-not-enreg[] "field V00.X (fldOffset=0x0)" P-DEP
;* V04 tmp2 [V04 ] ( 0, 0 ) float -> zero-ref do-not-enreg[] "field V00.Y (fldOffset=0x4)" P-DEP
;* V05 tmp3 [V05 ] ( 0, 0 ) float -> zero-ref do-not-enreg[] "field V00.Z (fldOffset=0x8)" P-DEP
;* V06 tmp4 [V06 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[S] "Promoted implicit byref" <Program.EntryPoint+Vector2>
; V07 tmp5 [V07,T03] ( 2, 0 ) ref -> rcx single-def "argument with side effect"
; V08 tmp6 [V08,T02] ( 2, 4 ) long -> rcx "Cast away GC"
;
; Lcl frame size = 32
*************** Before prolog / epilog generation
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M62292_IG02: ; offs=0x000000, size=0x0010, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], BB04 [0003], byref
G_M62292_IG03: ; epilog placeholder, next placeholder=<END>, BB04 [0003], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0002 {rcx}
G_M62292_IG04: ; offs=0x000110, size=0x0000, bbWeight=0, gcrefRegs=0000 {}, BB03 [0002] <-- Current IG
Recording Var Locations at start of BB01
V00(rcx) V01(rbx)
Saved:
G_M62292_IG04: ; offs=0x000110, size=0x0021, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], gcvars, byref
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M62292_IG01,ins#0,ofs#0) label
__prolog:
Debug: New V00 debug range: first
Debug: New V01 debug range: first
IN000c: push rbx
IN000d: sub rsp, 32
*************** In genHomeRegisterParams()
3 registers in register parameter interference graph
rcx
rdx
rbx
<- rdx
IN000e: mov ebx, edx
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Saved:
G_M62292_IG01: ; offs=0x000000, size=0x0007, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0002 {rcx}
IN000f: add rsp, 32
IN0010: pop rbx
IN0011: ret
Saved:
G_M62292_IG03: ; offs=0x000010, size=0x0006, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0007, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M62292_IG02: ; offs=0x000007, size=0x0010, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], BB04 [0003], byref
G_M62292_IG03: ; offs=0x000017, size=0x0006, bbWeight=1, epilog, nogc, extend
G_M62292_IG04: ; offs=0x00001D, size=0x0021, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], gcvars, byref
*************** In emitJumpDistBind()
Emitter Jump List:
IG02 IN0002 ja[6] -> IG04
total jump count: 1
Binding: IN0002: 000000 ja L_M62292_BB03
Binding L_M62292_BB03 to G_M62292_IG04
Estimate of fwd jump [61E675B4/002]: 000A -> 001D = 0011
Shrinking jump [61E675B4/002]
Adjusted offset of BB03 from 0017 to 0013
Adjusted offset of BB04 from 001D to 0019
Total shrinkage = 4, min extra jump size = 4294967295
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x3A bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x8)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M62292_IG01: ; offs=0x000000, size=0x0007, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN000c: 000000 push rbx
IN000d: 000001 sub rsp, 32
IN000e: 000005 mov ebx, edx
;; size=7 bbWeight=1 PerfScore 1.50
G_M62292_IG02: ; offs=0x000007, size=0x000C, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], BB04 [0003], byref, isz
; byrRegs +[rcx]
IN0001: 000007 cmp ebx, 1
IN0002: 00000A ja SHORT G_M62292_IG04
IN0003: 00000C mov edx, ebx
IN0004: 00000E vmovss xmm0, dword ptr [rcx+4*rdx]
;; size=12 bbWeight=1 PerfScore 5.50
G_M62292_IG03: ; offs=0x000013, size=0x0006, bbWeight=1, epilog, nogc, extend
IN000f: 000013 add rsp, 32
IN0010: 000017 pop rbx
IN0011: 000018 ret
;; size=6 bbWeight=1 PerfScore 1.75
G_M62292_IG04: ; offs=0x000019, size=0x0021, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], gcvars, byref
; byrRegs -[rcx]
IN0005: 000019 mov ecx, 1
IN0006: 00001E mov rdx, 0x7FF7F1188938
recordRelocation: 00007FF7F08ED7FA (rw: 00000230620A9C72) => 00007FF7F0E0D9C8, type 16 (IMAGE_REL_BASED_DISP32), delta 0
IN0007: 000028 call [CORINFO_HELP_STRCNS]
; gcrRegs +[rax]
; gcr arg pop 0
IN0008: 00002E mov rcx, rax
; gcrRegs +[rcx]
IN0009: 000031 mov edx, ebx
recordRelocation: 00007FF7F08ED805 (rw: 00000230620A9C7D) => 00007FF7F13342A0, type 16 (IMAGE_REL_BASED_DISP32), delta 0
IN000a: 000033 call [Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)]
; gcrRegs -[rax rcx]
; gcr arg pop 0
IN000b: 000039 int3
;; size=33 bbWeight=0 PerfScore 0.00
Allocated method code size = 58 , actual size = 58, unused size = 0
; Total bytes of code 58, prolog size 5, PerfScore 8.75, instruction count 17, allocated bytes for code 58 (MethodHash=2b4c0cab) for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float (Tier1)
; ============================================================
*************** After end code gen, before unwindEmit()
G_M62292_IG01: ; func=00, offs=0x000000, size=0x0007, bbWeight=1, PerfScore 1.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN000c: 000000 push rbx
IN000d: 000001 sub rsp, 32
IN000e: 000005 mov ebx, edx
G_M62292_IG02: ; offs=0x000007, size=0x000C, bbWeight=1, PerfScore 5.50, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], BB04 [0003], byref, isz
IN0001: 000007 cmp ebx, 1
IN0002: 00000A ja SHORT G_M62292_IG04
IN0003: 00000C mov edx, ebx
IN0004: 00000E vmovss xmm0, dword ptr [rcx+4*rdx]
G_M62292_IG03: ; offs=0x000013, size=0x0006, bbWeight=1, PerfScore 1.75, epilog, nogc, extend
IN000f: 000013 add rsp, 32
IN0010: 000017 pop rbx
IN0011: 000018 ret
G_M62292_IG04: ; offs=0x000019, size=0x0021, bbWeight=0, PerfScore 0.00, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0002], gcvars, byref
IN0005: 000019 mov ecx, 1
IN0006: 00001E mov rdx, 0x7FF7F1188938
IN0007: 000028 call [CORINFO_HELP_STRCNS]
IN0008: 00002E mov rcx, rax
IN0009: 000031 mov edx, ebx
IN000a: 000033 call [Program.EntryPoint:ThrowOutOfRangeException[int](System.String,int)]
IN000b: 000039 int3
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x00003a (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x05
CountOfUnwindCodes: 2
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 3 * 8 + 8 = 32 = 0x20
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3)
allocUnwindInfo(pHotCode=0x00007FF7F08ED7D0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x3a, unwindSize=0x8, pUnwindBlock=0x0000023062036D58, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 5
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000007 ( STACK_EMPTY )
IL offs 0x0013 : 0x0000000C ( STACK_EMPTY )
IL offs EPILOG : 0x00000013 ( STACK_EMPTY )
IL offs 0x0008 : 0x00000019 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 5
; Variable debug info: 4 live ranges, 2 vars for method Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
(V00 arg0) : From 00000000h to 0000000Ch, in rcx
(V01 arg1) : From 00000000h to 00000007h, in rdx
(V01 arg1) : From 00000007h to 0000000Ch, in rbx
(V01 arg1) : From 00000019h to 00000031h, in rbx
*************** In gcInfoBlockHdrSave()
Set code length to 58.
Set Outgoing stack arg area size to 32.
Register slot id for reg rax = 0.
Set state of slot 0 at instr offset 0x28 to Live.
Set state of slot 0 at instr offset 0x2e to Dead.
Defining 2 call sites:
Offset 0x28, size 6.
Offset 0x33, size 6.
*************** Finishing PHASE Emit GC+EH tables
Method code size: 58
Allocations for Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float (MethodHash=2b4c0cab)
count: 843, size: 92025, max = 7576
allocateMemory: 131072, nraUsed: 100320
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
ABI | 152 | 0.17%
AssertionProp | 6620 | 7.19%
ASTNode | 6208 | 6.75%
InstDesc | 3372 | 3.66%
ImpStack | 384 | 0.42%
BasicBlock | 1744 | 1.90%
CallArgs | 320 | 0.35%
FlowEdge | 240 | 0.26%
DepthFirstSearch | 424 | 0.46%
Loops | 272 | 0.30%
TreeStatementList | 0 | 0.00%
SiScope | 0 | 0.00%
DominatorMemory | 328 | 0.36%
LSRA | 9548 | 10.38%
LSRA_Interval | 1248 | 1.36%
LSRA_RefPosition | 3760 | 4.09%
Reachability | 16 | 0.02%
SSA | 672 | 0.73%
ValueNumber | 12408 | 13.48%
LvaTable | 1644 | 1.79%
UnwindInfo | 0 | 0.00%
hashBv | 40 | 0.04%
bitset | 32 | 0.03%
FixedBitVect | 40 | 0.04%
Generic | 1056 | 1.15%
LocalAddressVisitor | 112 | 0.12%
FieldSeqStore | 0 | 0.00%
MemorySsaMap | 40 | 0.04%
MemoryPhiArg | 0 | 0.00%
CSE | 1280 | 1.39%
GC | 2542 | 2.76%
CorTailCallInfo | 0 | 0.00%
Inlining | 1800 | 1.96%
ArrayStack | 0 | 0.00%
DebugInfo | 320 | 0.35%
DebugOnly | 29537 | 32.10%
Codegen | 2848 | 3.09%
LoopOpt | 0 | 0.00%
LoopClone | 0 | 0.00%
LoopUnroll | 0 | 0.00%
LoopHoist | 0 | 0.00%
LoopIVOpts | 0 | 0.00%
Unknown | 194 | 0.21%
RangeCheck | 0 | 0.00%
CopyProp | 776 | 0.84%
Promotion | 240 | 0.26%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 720 | 0.78%
ClassLayout | 200 | 0.22%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 88 | 0.10%
Pgo | 800 | 0.87%
MaskConversionOpt | 0 | 0.00%
TryRegionClone | 0 | 0.00%
Async | 0 | 0.00%
RangeCheckCloning | 0 | 0.00%
Final metrics:
ActualCodeBytes : 58
AllocatedHotCodeBytes : 58
AllocatedColdCodeBytes : 0
ReadOnlyDataBytes : 0
GCInfoBytes : 5
EHClauseCount : 0
PhysicallyPromotedFields : 0
LoopsFoundDuringOpts : 0
LoopsInverted : 0
LoopsCloned : 0
LoopsUnrolled : 0
LoopAlignmentCandidates : 0
LoopsAligned : 0
LoopsIVWidened : 0
WidenedIVs : 0
UnusedIVsRemoved : 0
LoopsMadeDownwardsCounted : 0
LoopsStrengthReduced : 0
VarsInSsa : 4
HoistedExpressions : 0
RedundantBranchesEliminated : 0
JumpThreadingsPerformed : 0
CseCount : 0
BasicBlocksAtCodegen : 3
PerfScore : 8.750000
BytesAllocated : 100320
ImporterBranchFold : 0
ImporterSwitchFold : 0
DevirtualizedCall : 0
DevirtualizedCallUnboxedEntry : 0
DevirtualizedCallRemovedBox : 0
GDV : 0
ClassGDV : 0
MethodGDV : 0
MultiGuessGDV : 0
ChainedGDV : 0
EnumeratorGDV : 0
InlinerBranchFold : 0
InlineAttempt : 0
InlineCount : 0
ProfileConsistentBeforeInline : 1
ProfileConsistentAfterInline : 1
ProfileConsistentBeforeMorph : 1
ProfileConsistentAfterMorph : 1
ProfileSynthesizedBlendedOrRepaired : 1
ProfileInconsistentInitially : 0
ProfileInconsistentResetLeave : 0
ProfileInconsistentImporterBranchFold : 0
ProfileInconsistentImporterSwitchFold : 0
ProfileInconsistentChainedGDV : 0
ProfileInconsistentScratchBB : 0
ProfileInconsistentInlinerBranchFold : 0
ProfileInconsistentInlineeScale : 0
ProfileInconsistentInlinee : 0
ProfileInconsistentNoReturnInlinee : 0
ProfileInconsistentMayThrowInlinee : 0
NewRefClassHelperCalls : 0
StackAllocatedRefClasses : 0
NewBoxedValueClassHelperCalls : 0
StackAllocatedBoxedValueClasses : 0
NewArrayHelperCalls : 0
StackAllocatedArrays : 0
LocalAssertionCount : 0
LocalAssertionOverflow : 0
MorphTrackedLocals : 1
MorphLocals : 9
EnumeratorGDVProvisionalNoEscape : 0
EnumeratorGDVCanCloneToEnsureNoEscape : 0
****** DONE compiling Program.EntryPoint:GetTest(Program.EntryPoint+Vector2,int):float
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