Contains notes about using the Versal™ Devices Integrated 100G Multirate Ethernet MAC Subsystem IP.
Differences between Designing with UltraScale+ CMAC and Versal MRMAC has some useful links.
Contains notes about using the Versal™ Devices Integrated 100G Multirate Ethernet MAC Subsystem IP.
Differences between Designing with UltraScale+ CMAC and Versal MRMAC has some useful links.
This contains notes about the AMD QDMA Subsystem for PCI Express, based upon trying to write a VFIO based poll-mode driver for QDMA.
Have UltraScale+ and Versal AI Edge devices to try with QDMA, which support the soft QDMA. Don't have devices with the CPM4 nor CPM4 hard QDMA.
Descibes notes about installing AlmaLinux 10.1 on a Dell Optiplex XE4 - see Notes about Milestone Husky IVO 350T Rev 3 reuse for notes about the PC which had been re-badged.
The processor is a 12th Gen Intel(R) Core(TM) i3-12100 CPU.
The initial state of the Dell Optiplex XE4 was:
The following sequence is repeatible:
AlmaLinux-10.0-x86_64_v2-Live-GNOME.iso to a Micro SD card as per AlmaLinux 10 initial look. That is using a USB to Micro SD adapter which doesn't provide write protection, even when Micro SD -> Micro SD to SD adapter with the switch set to the lock position -> USB to SD adpater.This contains notes about re-use of a second hand Milestone Husky IVO 350T Rev 3 PC.
This is a re-badged Dell PC, from a video technology software company.
Husky IVO Dell models and driver links links to the Dell Optiplex XE4 (rev. 3) https://www.dell.com/support/home/da-dk/product-support/product/optiplex-xe4/drivers, for the Husky IVO 350T.
The Milestone Husky IVO™ 350T Rev. 3 Getting started and maintenance guide links to the Dell Installation and service manual for the OptiPlex XE4 Tower.
Contains notes about the ALINX VD100 Dev Board & Kit with AMD Versal AI Edge XCVE2302
Noticed the product page linked above contains V2.0 at the start which suggests different hardware revisions may have been shipped. Looking at the history of the product page:
V2.0V2.0Have been using AXI Interconnect and SmartConnect in Vivado block designs to map multiple different peripherals to access via PCIe, without previously finding issues.
For the U200_100G_ether_simplex_tx went to add a second CMAC block.
The AXI SmartConnect assignments in the /xdma_0/M_AXI_LITE address space were:
| Master Segment Name | Slave Segment | Offset | Range |
|---|---|---|---|
| SEG_cmac_usplus_0_Reg | /cmac_usplus_0/s_axi/Reg | 0x0000 | 8K |
| SEG_axi_gpio_0_Reg | /axi_gpio_0/S_AXI/Reg | 0x2000 | 8K |
| SEG_system_management_wiz_0_Reg | /system_management_wiz_0/S_AXI_LITE/Reg | 0x4000 | 8K |
Notes about 100G Ethernet switches for a home lab, looking for either:
Found on Reddit "Cheap" 100G switches, pros and cons of each option? for initial suggestions.
Contains notes about using the open-nic project on an Alveo U200.
Using SmartGit cloned https://github.com/Xilinx/open-nic into ~/U200_open-nic/open-nic.
xilinx_7_series_bitstream.c was originally written for Xilinx 7 series devices, before subsequently adding support for Xilinx UltraScale and UltraScale+ devices.
The 7K160T doesn't use SSI.
Convert the bit to bin file, to remove the header so the contents of the file is word aligned: