STM32 TAMP Register for Tamper And Backup Registers - a hardware security and data-retention block

STM32-TAMP-Register-README.md

STM32 (STM32H5) TAMP Register

The STM32H5 TAMP (Tamper and Backup Registers) peripheral is a hardware security and data-retention block. It is designed to detect physical or electronic intrusions and automatically erase sensitive device secrets to prevent attacks, while also managing backup registers that survive power loss.

Key TAMP Features

• Tamper Detection: Supports multiple internal and external tamper sources (like active/passive detection) to catch intrusions.
• Backup Registers: 32 32-bit registers (TAMP_BKP0R to TAMP_BKP31R) designed to retain critical data when the main $V_{DD}$ supply is off.
• Boot Hardware Keys: The first 8 backup registers (TAMP_BKP0R – TAMP_BKP7R) can store secure AES boot hardware keys.
• Secrets Erasure: Capable of triggering immediate hardware erasure of device secrets, backup SRAM, and backup registers.

Core TAMP Registers

The TAMP peripheral is highly configurable. The primary registers controlling this behavior include:

Register	Name / Description	Function
TAMP_CR1	Control Register 1	Enables/disables individual external and internal tamper detection circuits.
TAMP_CR2	Control Register 2	Configures tamper edge/level triggers, filtering options, and "No Erase" rules for external pins.
TAMP_CR3	Control Register 3	Configures "No Erase" options and blocking mechanisms for internal tamper events.
TAMP_FLTCR	Filter Control Register	Sets tamper sampling frequencies and internal pull-up/precharge configurations for pins.
TAMP_SR	Status Register	Indicates whether an active tamper event has been detected on a specific pin/source.
TAMP_IER	Interrupt Enable Register	Masks or enables specific tamper event interrupts.
TAMP_MISR	Masked Interrupt Status Register	Displays flags identifying which unmasked tamper event triggered the interrupt.
TAMP_SMCR	Secure Mode Configuration	Sets protection, secure/non-secure read-write zones, and privilege levels for the backup registers.
TAMP_BKPxR	Backup Data Registers (i.e. TAMP_BKP0R)	32 registers used to preserve data across power cycles or during standby.

Reference and Documentation

For detailed register bit mappings, memory offsets, and instructions on how to use secure zones, consult the STM32H5 Reference Manual (RM0481). To implement secure anti-tamper functionality in your C code, you can use the Hardware Abstraction Layer API documented in the STM32CubeH5 TAMP HAL Documentation.

• https://wiki.st.com/stm32mpu/wiki/TAMP_internal_peripheral
• https://dev.st.com/stm32cube-docs/stm32u5-hal2/2.0.0-beta.1.1/docs/drivers/hal_drivers/tamp/hal_tamp_how_to_use.html
• https://wiki.st.com/stm32mpu/wiki/TAMP_internal_peripheral
• https://dev.st.com/stm32cube-docs/stm32u5-hal2/2.0.0-beta.1.1/docs/drivers/hal_drivers/tamp/hal_tamp_how_to_use.html
• https://www.st.com/content/ccc/resource/training/technical/product_training/group1/8f/b1/0d/28/a7/1f/42/cb/STM32L5-System-Tamper_and_backup_registers_TAMP/files/STM32L5-System-Tamper_and_backup_registers_TAMP.pdf/_jcr_content/translations/en.STM32L5-System-Tamper_and_backup_registers_TAMP.pdf
• https://www.st.com/content/ccc/resource/training/technical/product_training/group1/71/16/23/60/e4/f9/49/0a/STM32U5-Security-Enhanced-anti-tamper_ANTITAMP/files/STM32U5-Security-Enhanced-anti-tamper_ANTITAMP.pdf/_jcr_content/translations/en.STM32U5-Security-Enhanced-anti-tamper_ANTITAMP.pdf
• https://www.st.com/content/ccc/resource/training/technical/product_training/group1/8f/b1/0d/28/a7/1f/42/cb/STM32L5-System-Tamper_and_backup_registers_TAMP/files/STM32L5-System-Tamper_and_backup_registers_TAMP.pdf/_jcr_content/translations/en.STM32L5-System-Tamper_and_backup_registers_TAMP.pdf
• https://www.st.com/content/ccc/resource/training/technical/product_training/group1/71/16/23/60/e4/f9/49/0a/STM32U5-Security-Enhanced-anti-tamper_ANTITAMP/files/STM32U5-Security-Enhanced-anti-tamper_ANTITAMP.pdf/_jcr_content/translations/en.STM32U5-Security-Enhanced-anti-tamper_ANTITAMP.pdf
• https://www.st.com/content/ccc/resource/training/technical/product_training/group1/9c/6f/28/78/64/52/44/3e/stm32u0-system-tamper-and-backup-registers-tamp/files/stm32u0-system-tamper-and-backup-registers-tamp.pdf/jcr:content/translations/en.stm32u0-system-tamper-and-backup-registers-tamp.pdf
• https://docs.rs/stm32h5/latest/stm32h5/stm32h533/tamp/smisr/index.html
• https://docs.embassy.dev/stm32-metapac/git/stm32u595ai/tamp/struct.Tamp.html

STM32-TAMP-Register-Tamper-And-Backup-Registers.c

#include "stm32h5xx_hal_flash.h"

#define EDATA_PROVISION_COOKIE (0xDE4DB33FUL)

bool CustomInit();

static void EDataBackupCookieInit(void);
static bool EDataIsProvisionCookieSet(void);
static void EDataSetProvisionCookie(void);
static void EDataClearProvisionCookie(void);

bool CustomInit()
{
  if (!IsConfigurationValidated())  // Your custom function
  {
    EDataSetProvisionCookie();
    
    // ... Do custom data provisioning here ...
    // return false; // Return early if failure during process
    
    EDataClearProvisionCookie();
    return false
  }
  
  // 2nd-pass provisioning
  if (EDataIsProvisionCookieSet())
  {
    status = CustomDataProvisioning(); // S
    if (status == HAL_OK)
      EDataClearProvisionCookie();
  }
  
  // Load data as normal
  // ...
}

static void EDataBackupCookieInit(void)
{
  HAL_PWR_EnableBkUpAccess();
  __HAL_RCC_RTC_CLK_ENABLE();
}

static bool EDataIsProvisionCookieSet(void)
{
  EDataBackupCookieInit();
  return (TAMP->BKP0R == EDATA_PROVISION_COOKIE);
}

static void EDataSetProvisionCookie(void)
{
  EDataBackupCookieInit();
  TAMP->BKP0R = EDATA_PROVISION_COOKIE;
}

static void EDataClearProvisionCookie(void)
{
  EDataBackupCookieInit();
  TAMP->BKP0R = 0U;
}