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Daniel-Svensson/mulx-DecDivMod1E9-jitdump.txt

Created June 14, 2025 16:43
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mulx-DecDivMod1E9-jitdump.txt
****** START compiling Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint (MethodHash=5d76c1ec)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: optimizer should use profile data
IL to import:
IL_0000 02 ldarg.0
IL_0001 7b 67 00 00 04 ldfld 0x4000067
IL_0006 6e conv.u8
IL_0007 1f 20 ldc.i4.s 0x20
IL_0009 62 shl
IL_000a 02 ldarg.0
IL_000b 7b 69 00 00 04 ldfld 0x4000069
IL_0010 6e conv.u8
IL_0011 58 add
IL_0012 25 dup
IL_0013 20 00 ca 9a 3b ldc.i4 0x3B9ACA00
IL_0018 6a conv.i8
IL_0019 5c div.un
IL_001a 0a stloc.0
IL_001b 02 ldarg.0
IL_001c 06 ldloc.0
IL_001d 1f 20 ldc.i4.s 0x20
IL_001f 64 shr.un
IL_0020 6d conv.u4
IL_0021 7d 67 00 00 04 stfld 0x4000067
IL_0026 02 ldarg.0
IL_0027 06 ldloc.0
IL_0028 6d conv.u4
IL_0029 7d 69 00 00 04 stfld 0x4000069
IL_002e 06 ldloc.0
IL_002f 6d conv.u4
IL_0030 20 00 ca 9a 3b ldc.i4 0x3B9ACA00
IL_0035 5a mul
IL_0036 6e conv.u8
IL_0037 59 sub
IL_0038 1f 20 ldc.i4.s 0x20
IL_003a 62 shl
IL_003b 02 ldarg.0
IL_003c 7b 68 00 00 04 ldfld 0x4000068
IL_0041 6e conv.u8
IL_0042 58 add
IL_0043 25 dup
IL_0044 20 00 ca 9a 3b ldc.i4 0x3B9ACA00
IL_0049 6a conv.i8
IL_004a 5c div.un
IL_004b 6d conv.u4
IL_004c 0b stloc.1
IL_004d 02 ldarg.0
IL_004e 07 ldloc.1
IL_004f 7d 68 00 00 04 stfld 0x4000068
IL_0054 6d conv.u4
IL_0055 07 ldloc.1
IL_0056 20 00 ca 9a 3b ldc.i4 0x3B9ACA00
IL_005b 5a mul
IL_005c 59 sub
IL_005d 2a ret
1 return registers for return type int
[00..04) reg rax
Parameter V00 ABI info: [00..08) reg rcx
lvaGrabTemp returning 3 (V03 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
Local V03 should not be enregistered because: it is address exposed
; Initial local variable assignments
;
; V00 arg0 byref
; V01 loc0 long
; V02 loc1 int
; V03 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
*************** In compInitDebuggingInfo() for Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 3
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 05Eh
1: 01h 01h V01 loc0 000h 05Eh
2: 02h 02h V02 loc1 000h 05Eh
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint
Marked V01 as a single def local
Marked V02 as a single def local
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [0000] [000..05E)
IL Code Size,Instr 94, 51, Basic Block count 1, Local Variable Num,Ref count 4, 13 for method Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint
OPTIONS: opts.MinOpts() == false
Basic block list for 'Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint'
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
Trees after Pre-import
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)
*************** Finishing PHASE Profile incorporation [no changes]
*************** Starting PHASE Canonicalize entry
*************** Finishing PHASE Canonicalize entry [no changes]
*************** Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldfld 04000067
[ 1] 6 (0x006) conv.u8
[ 1] 7 (0x007) ldc.i4.s 32
[ 2] 9 (0x009) shl
[ 1] 10 (0x00a) ldarg.0
[ 2] 11 (0x00b) ldfld 04000069
[ 2] 16 (0x010) conv.u8
[ 2] 17 (0x011) add
[ 1] 18 (0x012) dup
lvaGrabTemp returning 4 (V04 tmp1) called for dup spill.
STMT00000 ( 0x000[E-] ... ??? )
[000011] DA-XG------ * STORE_LCL_VAR long V04 tmp1
[000010] ---XG------ \--* ADD long
[000005] ---XG------ +--* LSH long
[000003] ---XG----U- | +--* CAST long <- ulong <- uint
[000002] n--XG------ | | \--* IND int
[000001] ---X------- | | \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000000] ----------- | | \--* LCL_VAR byref V00 arg0
[000004] ----------- | \--* CNS_INT int 32
[000009] ---XG----U- \--* CAST long <- ulong <- uint
[000008] n--XG------ \--* IND int
[000007] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000006] ----------- \--* LCL_VAR byref V00 arg0
Marked V04 as a single def local
[ 2] 19 (0x013) ldc.i4 1000000000
[ 3] 24 (0x018) conv.i8
Folding long operator with constant nodes into a constant:
[000015] ----------- * CAST long <- int
[000014] ----------- \--* CNS_INT int 0x3B9ACA00
Bashed to long constant:
[000015] ----------- * CNS_INT long 0x3B9ACA00
[ 3] 25 (0x019) div.un
[ 2] 26 (0x01a) stloc.0
STMT00001 ( ??? ... ??? )
[000017] DA--------- * STORE_LCL_VAR long V01 loc0
[000016] ----------- \--* UDIV long
[000013] ----------- +--* LCL_VAR long V04 tmp1
[000015] ----------- \--* CNS_INT long 0x3B9ACA00
[ 1] 27 (0x01b) ldarg.0
[ 2] 28 (0x01c) ldloc.0
[ 3] 29 (0x01d) ldc.i4.s 32
[ 4] 31 (0x01f) shr.un
[ 3] 32 (0x020) conv.u4
[ 3] 33 (0x021) stfld 04000067
STMT00002 ( ??? ... ??? )
[000024] nA-XG------ * STOREIND int
[000023] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000018] ----------- | \--* LCL_VAR byref V00 arg0
[000022] ----------- \--* CAST int <- uint <- long
[000021] ----------- \--* RSZ long
[000019] ----------- +--* LCL_VAR long V01 loc0
[000020] ----------- \--* CNS_INT int 32
[ 1] 38 (0x026) ldarg.0
[ 2] 39 (0x027) ldloc.0
[ 3] 40 (0x028) conv.u4
[ 3] 41 (0x029) stfld 04000069
STMT00003 ( ??? ... ??? )
[000029] nA-XG------ * STOREIND int
[000028] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000025] ----------- | \--* LCL_VAR byref V00 arg0
[000027] ----------- \--* CAST int <- uint <- long
[000026] ----------- \--* LCL_VAR long V01 loc0
[ 1] 46 (0x02e) ldloc.0
[ 2] 47 (0x02f) conv.u4
[ 2] 48 (0x030) ldc.i4 1000000000
[ 3] 53 (0x035) mul
[ 2] 54 (0x036) conv.u8
[ 2] 55 (0x037) sub
[ 1] 56 (0x038) ldc.i4.s 32
[ 2] 58 (0x03a) shl
[ 1] 59 (0x03b) ldarg.0
[ 2] 60 (0x03c) ldfld 04000068
[ 2] 65 (0x041) conv.u8
[ 2] 66 (0x042) add
[ 1] 67 (0x043) dup
lvaGrabTemp returning 5 (V05 tmp2) called for dup spill.
STMT00004 ( ??? ... ??? )
[000043] DA-XG------ * STORE_LCL_VAR long V05 tmp2
[000042] ---XG------ \--* ADD long
[000037] ----------- +--* LSH long
[000035] ----------- | +--* SUB long
[000012] ----------- | | +--* LCL_VAR long V04 tmp1
[000034] ---------U- | | \--* CAST long <- ulong <- uint
[000033] ----------- | | \--* MUL int
[000031] ----------- | | +--* CAST int <- uint <- long
[000030] ----------- | | | \--* LCL_VAR long V01 loc0
[000032] ----------- | | \--* CNS_INT int 0x3B9ACA00
[000036] ----------- | \--* CNS_INT int 32
[000041] ---XG----U- \--* CAST long <- ulong <- uint
[000040] n--XG------ \--* IND int
[000039] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000038] ----------- \--* LCL_VAR byref V00 arg0
Marked V05 as a single def local
[ 2] 68 (0x044) ldc.i4 1000000000
[ 3] 73 (0x049) conv.i8
Folding long operator with constant nodes into a constant:
[000047] ----------- * CAST long <- int
[000046] ----------- \--* CNS_INT int 0x3B9ACA00
Bashed to long constant:
[000047] ----------- * CNS_INT long 0x3B9ACA00
[ 3] 74 (0x04a) div.un
[ 2] 75 (0x04b) conv.u4
[ 2] 76 (0x04c) stloc.1
STMT00005 ( ??? ... ??? )
[000050] DA--------- * STORE_LCL_VAR int V02 loc1
[000049] ----------- \--* CAST int <- uint <- long
[000048] ----------- \--* UDIV long
[000045] ----------- +--* LCL_VAR long V05 tmp2
[000047] ----------- \--* CNS_INT long 0x3B9ACA00
[ 1] 77 (0x04d) ldarg.0
[ 2] 78 (0x04e) ldloc.1
[ 3] 79 (0x04f) stfld 04000068
STMT00006 ( ??? ... ??? )
[000054] nA-XG------ * STOREIND int
[000053] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000051] ----------- | \--* LCL_VAR byref V00 arg0
[000052] ----------- \--* LCL_VAR int V02 loc1
[ 1] 84 (0x054) conv.u4
[ 1] 85 (0x055) ldloc.1
[ 2] 86 (0x056) ldc.i4 1000000000
[ 3] 91 (0x05b) mul
[ 2] 92 (0x05c) sub
[ 1] 93 (0x05d) ret
STMT00007 ( ??? ... ??? )
[000060] ----------- * RETURN int
[000059] ----------- \--* SUB int
[000055] ----------- +--* CAST int <- uint <- long
[000044] ----------- | \--* LCL_VAR long V05 tmp2
[000058] ----------- \--* MUL int
[000056] ----------- +--* LCL_VAR int V02 loc1
[000057] ----------- \--* CNS_INT int 0x3B9ACA00
*************** Finishing PHASE Importation
Trees after Importation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG------ * STORE_LCL_VAR long V04 tmp1
[000010] ---XG------ \--* ADD long
[000005] ---XG------ +--* LSH long
[000003] ---XG----U- | +--* CAST long <- ulong <- uint
[000002] n--XG------ | | \--* IND int
[000001] ---X------- | | \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000000] ----------- | | \--* LCL_VAR byref V00 arg0
[000004] ----------- | \--* CNS_INT int 32
[000009] ---XG----U- \--* CAST long <- ulong <- uint
[000008] n--XG------ \--* IND int
[000007] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000006] ----------- \--* LCL_VAR byref V00 arg0
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
[000017] DA--------- * STORE_LCL_VAR long V01 loc0
[000016] ----------- \--* UDIV long
[000013] ----------- +--* LCL_VAR long V04 tmp1
[000015] ----------- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
[000024] nA-XG------ * STOREIND int
[000023] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000018] ----------- | \--* LCL_VAR byref V00 arg0
[000022] ----------- \--* CAST int <- uint <- long
[000021] ----------- \--* RSZ long
[000019] ----------- +--* LCL_VAR long V01 loc0
[000020] ----------- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
[000029] nA-XG------ * STOREIND int
[000028] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000025] ----------- | \--* LCL_VAR byref V00 arg0
[000027] ----------- \--* CAST int <- uint <- long
[000026] ----------- \--* LCL_VAR long V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
[000043] DA-XG------ * STORE_LCL_VAR long V05 tmp2
[000042] ---XG------ \--* ADD long
[000037] ----------- +--* LSH long
[000035] ----------- | +--* SUB long
[000012] ----------- | | +--* LCL_VAR long V04 tmp1
[000034] ---------U- | | \--* CAST long <- ulong <- uint
[000033] ----------- | | \--* MUL int
[000031] ----------- | | +--* CAST int <- uint <- long
[000030] ----------- | | | \--* LCL_VAR long V01 loc0
[000032] ----------- | | \--* CNS_INT int 0x3B9ACA00
[000036] ----------- | \--* CNS_INT int 32
[000041] ---XG----U- \--* CAST long <- ulong <- uint
[000040] n--XG------ \--* IND int
[000039] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000038] ----------- \--* LCL_VAR byref V00 arg0
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
[000050] DA--------- * STORE_LCL_VAR int V02 loc1
[000049] ----------- \--* CAST int <- uint <- long
[000048] ----------- \--* UDIV long
[000045] ----------- +--* LCL_VAR long V05 tmp2
[000047] ----------- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
[000054] nA-XG------ * STOREIND int
[000053] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000051] ----------- | \--* LCL_VAR byref V00 arg0
[000052] ----------- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
[000060] ----------- * RETURN int
[000059] ----------- \--* SUB int
[000055] ----------- +--* CAST int <- uint <- long
[000044] ----------- | \--* LCL_VAR long V05 tmp2
[000058] ----------- \--* MUL int
[000056] ----------- +--* LCL_VAR int V02 loc1
[000057] ----------- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import [no changes]
*************** Starting PHASE Morph - Init
*************** Finishing PHASE Morph - Init [no changes]
*************** Starting PHASE Morph - Inlining
INLINER: no pgo data
**************** Inline Tree
Inlines into 060001C0 [via ExtendedDefaultPolicy] Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint:
Budget: initialTime=342, finalTime=342, initialBudget=6840, currentBudget=6840
Budget: initialSize=2274, finalSize=2274
*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG------ * STORE_LCL_VAR long V04 tmp1
[000010] ---XG------ \--* ADD long
[000005] ---XG------ +--* LSH long
[000003] ---XG----U- | +--* CAST long <- ulong <- uint
[000002] n--XG------ | | \--* IND int
[000001] ---X------- | | \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000000] ----------- | | \--* LCL_VAR byref V00 arg0
[000004] ----------- | \--* CNS_INT int 32
[000009] ---XG----U- \--* CAST long <- ulong <- uint
[000008] n--XG------ \--* IND int
[000007] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000006] ----------- \--* LCL_VAR byref V00 arg0
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
[000017] DA--------- * STORE_LCL_VAR long V01 loc0
[000016] ----------- \--* UDIV long
[000013] ----------- +--* LCL_VAR long V04 tmp1
[000015] ----------- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
[000024] nA-XG------ * STOREIND int
[000023] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000018] ----------- | \--* LCL_VAR byref V00 arg0
[000022] ----------- \--* CAST int <- uint <- long
[000021] ----------- \--* RSZ long
[000019] ----------- +--* LCL_VAR long V01 loc0
[000020] ----------- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
[000029] nA-XG------ * STOREIND int
[000028] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000025] ----------- | \--* LCL_VAR byref V00 arg0
[000027] ----------- \--* CAST int <- uint <- long
[000026] ----------- \--* LCL_VAR long V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
[000043] DA-XG------ * STORE_LCL_VAR long V05 tmp2
[000042] ---XG------ \--* ADD long
[000037] ----------- +--* LSH long
[000035] ----------- | +--* SUB long
[000012] ----------- | | +--* LCL_VAR long V04 tmp1
[000034] ---------U- | | \--* CAST long <- ulong <- uint
[000033] ----------- | | \--* MUL int
[000031] ----------- | | +--* CAST int <- uint <- long
[000030] ----------- | | | \--* LCL_VAR long V01 loc0
[000032] ----------- | | \--* CNS_INT int 0x3B9ACA00
[000036] ----------- | \--* CNS_INT int 32
[000041] ---XG----U- \--* CAST long <- ulong <- uint
[000040] n--XG------ \--* IND int
[000039] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000038] ----------- \--* LCL_VAR byref V00 arg0
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
[000050] DA--------- * STORE_LCL_VAR int V02 loc1
[000049] ----------- \--* CAST int <- uint <- long
[000048] ----------- \--* UDIV long
[000045] ----------- +--* LCL_VAR long V05 tmp2
[000047] ----------- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
[000054] nA-XG------ * STOREIND int
[000053] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000051] ----------- | \--* LCL_VAR byref V00 arg0
[000052] ----------- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
[000060] ----------- * RETURN int
[000059] ----------- \--* SUB int
[000055] ----------- +--* CAST int <- uint <- long
[000044] ----------- | \--* LCL_VAR long V05 tmp2
[000058] ----------- \--* MUL int
[000056] ----------- +--* LCL_VAR int V02 loc1
[000057] ----------- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE DFS blocks and remove dead code 1
*************** Finishing PHASE DFS blocks and remove dead code 1 [no changes]
*************** Starting PHASE Allocate Objects
no newobjs or newarr in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks [no changes]
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty try/catch/fault
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try/catch/fault [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Head and tail merge
*************** Finishing PHASE Head and tail merge
Trees after Head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG------ * STORE_LCL_VAR long V04 tmp1
[000010] ---XG------ \--* ADD long
[000005] ---XG------ +--* LSH long
[000003] ---XG----U- | +--* CAST long <- ulong <- uint
[000002] n--XG------ | | \--* IND int
[000001] ---X------- | | \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000000] ----------- | | \--* LCL_VAR byref V00 arg0
[000004] ----------- | \--* CNS_INT int 32
[000009] ---XG----U- \--* CAST long <- ulong <- uint
[000008] n--XG------ \--* IND int
[000007] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000006] ----------- \--* LCL_VAR byref V00 arg0
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
[000017] DA--------- * STORE_LCL_VAR long V01 loc0
[000016] ----------- \--* UDIV long
[000013] ----------- +--* LCL_VAR long V04 tmp1
[000015] ----------- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
[000024] nA-XG------ * STOREIND int
[000023] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000018] ----------- | \--* LCL_VAR byref V00 arg0
[000022] ----------- \--* CAST int <- uint <- long
[000021] ----------- \--* RSZ long
[000019] ----------- +--* LCL_VAR long V01 loc0
[000020] ----------- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
[000029] nA-XG------ * STOREIND int
[000028] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000025] ----------- | \--* LCL_VAR byref V00 arg0
[000027] ----------- \--* CAST int <- uint <- long
[000026] ----------- \--* LCL_VAR long V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
[000043] DA-XG------ * STORE_LCL_VAR long V05 tmp2
[000042] ---XG------ \--* ADD long
[000037] ----------- +--* LSH long
[000035] ----------- | +--* SUB long
[000012] ----------- | | +--* LCL_VAR long V04 tmp1
[000034] ---------U- | | \--* CAST long <- ulong <- uint
[000033] ----------- | | \--* MUL int
[000031] ----------- | | +--* CAST int <- uint <- long
[000030] ----------- | | | \--* LCL_VAR long V01 loc0
[000032] ----------- | | \--* CNS_INT int 0x3B9ACA00
[000036] ----------- | \--* CNS_INT int 32
[000041] ---XG----U- \--* CAST long <- ulong <- uint
[000040] n--XG------ \--* IND int
[000039] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000038] ----------- \--* LCL_VAR byref V00 arg0
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
[000050] DA--------- * STORE_LCL_VAR int V02 loc1
[000049] ----------- \--* CAST int <- uint <- long
[000048] ----------- \--* UDIV long
[000045] ----------- +--* LCL_VAR long V05 tmp2
[000047] ----------- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
[000054] nA-XG------ * STOREIND int
[000053] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000051] ----------- | \--* LCL_VAR byref V00 arg0
[000052] ----------- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
[000060] ----------- * RETURN int
[000059] ----------- \--* SUB int
[000055] ----------- +--* CAST int <- uint <- long
[000044] ----------- | \--* LCL_VAR long V05 tmp2
[000058] ----------- \--* MUL int
[000056] ----------- +--* LCL_VAR int V02 loc1
[000057] ----------- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks [no changes]
*************** Starting PHASE Update flow graph early pass
*************** Finishing PHASE Update flow graph early pass [no changes]
*************** Starting PHASE Morph - Promote Structs
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 byref
; V01 loc0 long
; V02 loc1 int
; V03 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
; V04 tmp1 long "dup spill"
; V05 tmp2 long "dup spill"
struct promotion of V03 is disabled because it has already been marked DNER
*************** Finishing PHASE Morph - Promote Structs [no changes]
*************** Starting PHASE DFS blocks and remove dead code 2
*************** Finishing PHASE DFS blocks and remove dead code 2 [no changes]
*************** Starting PHASE Morph - Structs/AddrExp
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG------ * STORE_LCL_VAR long V04 tmp1
[000010] ---XG------ \--* ADD long
[000005] ---XG------ +--* LSH long
[000003] ---XG----U- | +--* CAST long <- ulong <- uint
[000002] n--XG------ | | \--* IND int
[000001] ---X------- | | \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000000] ----------- | | \--* LCL_VAR byref V00 arg0
[000004] ----------- | \--* CNS_INT int 32
[000009] ---XG----U- \--* CAST long <- ulong <- uint
[000008] n--XG------ \--* IND int
[000007] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000006] ----------- \--* LCL_VAR byref V00 arg0
LocalAddressVisitor visiting statement:
STMT00001 ( ??? ... ??? )
[000017] DA--------- * STORE_LCL_VAR long V01 loc0
[000016] ----------- \--* UDIV long
[000013] ----------- +--* LCL_VAR long V04 tmp1
[000015] ----------- \--* CNS_INT long 0x3B9ACA00
LocalAddressVisitor visiting statement:
STMT00002 ( ??? ... 0x021 )
[000024] nA-XG------ * STOREIND int
[000023] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000018] ----------- | \--* LCL_VAR byref V00 arg0
[000022] ----------- \--* CAST int <- uint <- long
[000021] ----------- \--* RSZ long
[000019] ----------- +--* LCL_VAR long V01 loc0
[000020] ----------- \--* CNS_INT int 32
LocalAddressVisitor visiting statement:
STMT00003 ( ??? ... 0x029 )
[000029] nA-XG------ * STOREIND int
[000028] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000025] ----------- | \--* LCL_VAR byref V00 arg0
[000027] ----------- \--* CAST int <- uint <- long
[000026] ----------- \--* LCL_VAR long V01 loc0
LocalAddressVisitor visiting statement:
STMT00004 ( ??? ... 0x04C )
[000043] DA-XG------ * STORE_LCL_VAR long V05 tmp2
[000042] ---XG------ \--* ADD long
[000037] ----------- +--* LSH long
[000035] ----------- | +--* SUB long
[000012] ----------- | | +--* LCL_VAR long V04 tmp1
[000034] ---------U- | | \--* CAST long <- ulong <- uint
[000033] ----------- | | \--* MUL int
[000031] ----------- | | +--* CAST int <- uint <- long
[000030] ----------- | | | \--* LCL_VAR long V01 loc0
[000032] ----------- | | \--* CNS_INT int 0x3B9ACA00
[000036] ----------- | \--* CNS_INT int 32
[000041] ---XG----U- \--* CAST long <- ulong <- uint
[000040] n--XG------ \--* IND int
[000039] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000038] ----------- \--* LCL_VAR byref V00 arg0
LocalAddressVisitor visiting statement:
STMT00005 ( ??? ... ??? )
[000050] DA--------- * STORE_LCL_VAR int V02 loc1
[000049] ----------- \--* CAST int <- uint <- long
[000048] ----------- \--* UDIV long
[000045] ----------- +--* LCL_VAR long V05 tmp2
[000047] ----------- \--* CNS_INT long 0x3B9ACA00
LocalAddressVisitor visiting statement:
STMT00006 ( ??? ... 0x04F )
[000054] nA-XG------ * STOREIND int
[000053] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000051] ----------- | \--* LCL_VAR byref V00 arg0
[000052] ----------- \--* LCL_VAR int V02 loc1
LocalAddressVisitor visiting statement:
STMT00007 ( ??? ... 0x05D )
[000060] ----------- * RETURN int
[000059] ----------- \--* SUB int
[000055] ----------- +--* CAST int <- uint <- long
[000044] ----------- | \--* LCL_VAR long V05 tmp2
[000058] ----------- \--* MUL int
[000056] ----------- +--* LCL_VAR int V02 loc1
[000057] ----------- \--* CNS_INT int 0x3B9ACA00
*************** Finishing PHASE Morph - Structs/AddrExp [no changes]
*************** Starting PHASE Optimize mask conversions
Skipping. There are no converts of locals
*************** Finishing PHASE Optimize mask conversions [no changes]
*************** Starting PHASE Early liveness
Local V03 should not be enregistered because: struct size does not match reg size
Tracked variable (5 out of 6) table:
V00 arg0 [ byref]: refCnt = 6, refCntWtd = 0
V01 loc0 [ long]: refCnt = 4, refCntWtd = 0
V02 loc1 [ int]: refCnt = 3, refCntWtd = 0
V04 tmp1 [ long]: refCnt = 3, refCntWtd = 0
V05 tmp2 [ long]: refCnt = 3, refCntWtd = 0
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 }
DEF(4)={ V01 V02 V04 V05}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00}
OUT(0)={ }
*************** Finishing PHASE Early liveness
Trees after Early liveness
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG------ * STORE_LCL_VAR long V04 tmp1
[000010] ---XG------ \--* ADD long
[000005] ---XG------ +--* LSH long
[000003] ---XG----U- | +--* CAST long <- ulong <- uint
[000002] n--XG------ | | \--* IND int
[000001] ---X------- | | \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000000] ----------- | | \--* LCL_VAR byref V00 arg0
[000004] ----------- | \--* CNS_INT int 32
[000009] ---XG----U- \--* CAST long <- ulong <- uint
[000008] n--XG------ \--* IND int
[000007] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000006] ----------- \--* LCL_VAR byref V00 arg0
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
[000017] DA--------- * STORE_LCL_VAR long V01 loc0
[000016] ----------- \--* UDIV long
[000013] ----------- +--* LCL_VAR long V04 tmp1
[000015] ----------- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
[000024] nA-XG------ * STOREIND int
[000023] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000018] ----------- | \--* LCL_VAR byref V00 arg0
[000022] ----------- \--* CAST int <- uint <- long
[000021] ----------- \--* RSZ long
[000019] ----------- +--* LCL_VAR long V01 loc0
[000020] ----------- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
[000029] nA-XG------ * STOREIND int
[000028] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000025] ----------- | \--* LCL_VAR byref V00 arg0
[000027] ----------- \--* CAST int <- uint <- long
[000026] ----------- \--* LCL_VAR long V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
[000043] DA-XG------ * STORE_LCL_VAR long V05 tmp2
[000042] ---XG------ \--* ADD long
[000037] ----------- +--* LSH long
[000035] ----------- | +--* SUB long
[000012] ----------- | | +--* LCL_VAR long V04 tmp1 (last use)
[000034] ---------U- | | \--* CAST long <- ulong <- uint
[000033] ----------- | | \--* MUL int
[000031] ----------- | | +--* CAST int <- uint <- long
[000030] ----------- | | | \--* LCL_VAR long V01 loc0 (last use)
[000032] ----------- | | \--* CNS_INT int 0x3B9ACA00
[000036] ----------- | \--* CNS_INT int 32
[000041] ---XG----U- \--* CAST long <- ulong <- uint
[000040] n--XG------ \--* IND int
[000039] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000038] ----------- \--* LCL_VAR byref V00 arg0
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
[000050] DA--------- * STORE_LCL_VAR int V02 loc1
[000049] ----------- \--* CAST int <- uint <- long
[000048] ----------- \--* UDIV long
[000045] ----------- +--* LCL_VAR long V05 tmp2
[000047] ----------- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
[000054] nA-XG------ * STOREIND int
[000053] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000051] ----------- | \--* LCL_VAR byref V00 arg0 (last use)
[000052] ----------- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
[000060] ----------- * RETURN int
[000059] ----------- \--* SUB int
[000055] ----------- +--* CAST int <- uint <- long
[000044] ----------- | \--* LCL_VAR long V05 tmp2 (last use)
[000058] ----------- \--* MUL int
[000056] ----------- +--* LCL_VAR int V02 loc1 (last use)
[000057] ----------- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Forward Substitution
===> BB01
[000011]: next stmt has non-last use
[000017]: next stmt has non-last use
[000043]: next stmt has non-last use
[000050]: next stmt has non-last use
*************** Finishing PHASE Forward Substitution [no changes]
*************** Starting PHASE Physical promotion
*************** Finishing PHASE Physical promotion [no changes]
*************** Starting PHASE Identify candidates for implicit byref copy omission
*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]
*************** Starting PHASE Morph - ByRefs
*************** Finishing PHASE Morph - ByRefs [no changes]
*************** Starting PHASE Morph - Global
Cross-block table size 64 (for 5 tracked locals)
Morphing BB01
BB01 ineligible for cross-block
Assertions in: #NA
fgMorphTree BB01, STMT00000 (before)
[000011] DA-XG------ * STORE_LCL_VAR long V04 tmp1
[000010] ---XG------ \--* ADD long
[000005] ---XG------ +--* LSH long
[000003] ---XG----U- | +--* CAST long <- ulong <- uint
[000002] n--XG------ | | \--* IND int
[000001] ---X------- | | \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000000] ----------- | | \--* LCL_VAR byref V00 arg0
[000004] ----------- | \--* CNS_INT int 32
[000009] ---XG----U- \--* CAST long <- ulong <- uint
[000008] n--XG------ \--* IND int
[000007] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000006] ----------- \--* LCL_VAR byref V00 arg0
Final value of Compiler::fgMorphFieldAddr after morphing:
[000062] -----+----- * ADD byref
[000000] -----+----- +--* LCL_VAR byref V00 arg0
[000061] -----+----- \--* CNS_INT long 4
GenTreeNode creates assertion:
[000002] ---XG+----- * IND int
In BB01 New Local Constant Assertion: V00 != 0, index = #01
Final value of Compiler::fgMorphFieldAddr after morphing:
[000064] -----+----- * ADD byref
[000006] -----+----- +--* LCL_VAR byref V00 arg0
[000063] -----+----- \--* CNS_INT long 12
fgMorphTree BB01, STMT00000 (after)
[000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1
[000010] ---XG+----- \--* ADD long
[000005] ---XG+----- +--* LSH long
[000003] ---XG+---U- | +--* CAST long <- ulong <- uint
[000002] ---XG+----- | | \--* IND int
[000062] -----+----- | | \--* ADD byref
[000000] -----+----- | | +--* LCL_VAR byref V00 arg0
[000061] -----+----- | | \--* CNS_INT long 4
[000004] -----+----- | \--* CNS_INT int 32
[000009] ---XG+---U- \--* CAST long <- ulong <- uint
[000008] ---XG+----- \--* IND int
[000064] -----+----- \--* ADD byref
[000006] -----+----- +--* LCL_VAR byref V00 arg0
[000063] -----+----- \--* CNS_INT long 12
fgMorphTree BB01, STMT00001 (before)
[000017] DA--------- * STORE_LCL_VAR long V01 loc0
[000016] ----------- \--* UDIV long
[000013] ----------- +--* LCL_VAR long V04 tmp1
[000015] ----------- \--* CNS_INT long 0x3B9ACA00
fgMorphTree BB01, STMT00002 (before)
[000024] nA-XG------ * STOREIND int
[000023] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:uhi
[000018] ----------- | \--* LCL_VAR byref V00 arg0
[000022] ----------- \--* CAST int <- uint <- long
[000021] ----------- \--* RSZ long
[000019] ----------- +--* LCL_VAR long V01 loc0
[000020] ----------- \--* CNS_INT int 32
Final value of Compiler::fgMorphFieldAddr after morphing:
[000066] -----+----- * ADD byref
[000018] -----+----- +--* LCL_VAR byref V00 arg0
[000065] -----+----- \--* CNS_INT long 4
Non-null assertion prop for indirection [000024] in BB01:
fgMorphTree BB01, STMT00002 (after)
[000024] nA--G+----- * STOREIND int
[000066] -----+----- +--* ADD byref
[000018] -----+----- | +--* LCL_VAR byref V00 arg0
[000065] -----+----- | \--* CNS_INT long 4
[000022] -----+----- \--* CAST int <- uint <- long
[000021] -----+----- \--* RSZ long
[000019] -----+----- +--* LCL_VAR long V01 loc0
[000020] -----+----- \--* CNS_INT int 32
fgMorphTree BB01, STMT00003 (before)
[000029] nA-XG------ * STOREIND int
[000028] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:umid
[000025] ----------- | \--* LCL_VAR byref V00 arg0
[000027] ----------- \--* CAST int <- uint <- long
[000026] ----------- \--* LCL_VAR long V01 loc0
Final value of Compiler::fgMorphFieldAddr after morphing:
[000068] -----+----- * ADD byref
[000025] -----+----- +--* LCL_VAR byref V00 arg0
[000067] -----+----- \--* CNS_INT long 12
Non-null assertion prop for indirection [000029] in BB01:
fgMorphTree BB01, STMT00003 (after)
[000029] nA--G+----- * STOREIND int
[000068] -----+----- +--* ADD byref
[000025] -----+----- | +--* LCL_VAR byref V00 arg0
[000067] -----+----- | \--* CNS_INT long 12
[000026] -----+----- \--* LCL_VAR int V01 loc0
fgMorphTree BB01, STMT00004 (before)
[000043] DA-XG------ * STORE_LCL_VAR long V05 tmp2
[000042] ---XG------ \--* ADD long
[000037] ----------- +--* LSH long
[000035] ----------- | +--* SUB long
[000012] ----------- | | +--* LCL_VAR long V04 tmp1 (last use)
[000034] ---------U- | | \--* CAST long <- ulong <- uint
[000033] ----------- | | \--* MUL int
[000031] ----------- | | +--* CAST int <- uint <- long
[000030] ----------- | | | \--* LCL_VAR long V01 loc0 (last use)
[000032] ----------- | | \--* CNS_INT int 0x3B9ACA00
[000036] ----------- | \--* CNS_INT int 32
[000041] ---XG----U- \--* CAST long <- ulong <- uint
[000040] n--XG------ \--* IND int
[000039] ---X------- \--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000038] ----------- \--* LCL_VAR byref V00 arg0
Final value of Compiler::fgMorphFieldAddr after morphing:
[000070] -----+----- * ADD byref
[000038] -----+----- +--* LCL_VAR byref V00 arg0
[000069] -----+----- \--* CNS_INT long 8
Non-null assertion prop for indirection [000040] in BB01:
fgMorphTree BB01, STMT00004 (after)
[000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2
[000042] ----G+----- \--* ADD long
[000037] -----+----- +--* LSH long
[000035] -----+----- | +--* SUB long
[000012] -----+----- | | +--* LCL_VAR long V04 tmp1 (last use)
[000034] -----+---U- | | \--* CAST long <- ulong <- uint
[000033] -----+----- | | \--* MUL int
[000030] -----+----- | | +--* LCL_VAR int V01 loc0 (last use)
[000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
[000036] -----+----- | \--* CNS_INT int 32
[000041] ----G+---U- \--* CAST long <- ulong <- uint
[000040] n---G+----- \--* IND int
[000070] -----+----- \--* ADD byref
[000038] -----+----- +--* LCL_VAR byref V00 arg0
[000069] -----+----- \--* CNS_INT long 8
fgMorphTree BB01, STMT00005 (before)
[000050] DA--------- * STORE_LCL_VAR int V02 loc1
[000049] ----------- \--* CAST int <- uint <- long
[000048] ----------- \--* UDIV long
[000045] ----------- +--* LCL_VAR long V05 tmp2
[000047] ----------- \--* CNS_INT long 0x3B9ACA00
fgMorphTree BB01, STMT00006 (before)
[000054] nA-XG------ * STOREIND int
[000053] ---X------- +--* FIELD_ADDR byref Managed.New.Decimal+DecCalc:ulo
[000051] ----------- | \--* LCL_VAR byref V00 arg0 (last use)
[000052] ----------- \--* LCL_VAR int V02 loc1
Final value of Compiler::fgMorphFieldAddr after morphing:
[000072] -----+----- * ADD byref
[000051] -----+----- +--* LCL_VAR byref V00 arg0 (last use)
[000071] -----+----- \--* CNS_INT long 8
Non-null assertion prop for indirection [000054] in BB01:
fgMorphTree BB01, STMT00006 (after)
[000054] nA--G+----- * STOREIND int
[000072] -----+----- +--* ADD byref
[000051] -----+----- | +--* LCL_VAR byref V00 arg0 (last use)
[000071] -----+----- | \--* CNS_INT long 8
[000052] -----+----- \--* LCL_VAR int V02 loc1
fgMorphTree BB01, STMT00007 (before)
[000060] ----------- * RETURN int
[000059] ----------- \--* SUB int
[000055] ----------- +--* CAST int <- uint <- long
[000044] ----------- | \--* LCL_VAR long V05 tmp2 (last use)
[000058] ----------- \--* MUL int
[000056] ----------- +--* LCL_VAR int V02 loc1 (last use)
[000057] ----------- \--* CNS_INT int 0x3B9ACA00
fgMorphTree BB01, STMT00007 (after)
[000060] -----+----- * RETURN int
[000059] -----+----- \--* SUB int
[000044] -----+----- +--* LCL_VAR int V05 tmp2 (last use)
[000058] -----+----- \--* MUL int
[000056] -----+----- +--* LCL_VAR int V02 loc1 (last use)
[000057] -----+----- \--* CNS_INT int 0x3B9ACA00
morph assertion stats: 64 table size, 1 assertions, 0 dropped
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1
[000010] ---XG+----- \--* ADD long
[000005] ---XG+----- +--* LSH long
[000003] ---XG+---U- | +--* CAST long <- ulong <- uint
[000002] ---XG+----- | | \--* IND int
[000062] -----+----- | | \--* ADD byref
[000000] -----+----- | | +--* LCL_VAR byref V00 arg0
[000061] -----+----- | | \--* CNS_INT long 4
[000004] -----+----- | \--* CNS_INT int 32
[000009] ---XG+---U- \--* CAST long <- ulong <- uint
[000008] ---XG+----- \--* IND int
[000064] -----+----- \--* ADD byref
[000006] -----+----- +--* LCL_VAR byref V00 arg0
[000063] -----+----- \--* CNS_INT long 12
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
[000017] DA---+----- * STORE_LCL_VAR long V01 loc0
[000016] -----+----- \--* UDIV long
[000013] -----+----- +--* LCL_VAR long V04 tmp1
[000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
[000024] nA--G+----- * STOREIND int
[000066] -----+----- +--* ADD byref
[000018] -----+----- | +--* LCL_VAR byref V00 arg0
[000065] -----+----- | \--* CNS_INT long 4
[000022] -----+----- \--* CAST int <- uint <- long
[000021] -----+----- \--* RSZ long
[000019] -----+----- +--* LCL_VAR long V01 loc0
[000020] -----+----- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
[000029] nA--G+----- * STOREIND int
[000068] -----+----- +--* ADD byref
[000025] -----+----- | +--* LCL_VAR byref V00 arg0
[000067] -----+----- | \--* CNS_INT long 12
[000026] -----+----- \--* LCL_VAR int V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
[000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2
[000042] ----G+----- \--* ADD long
[000037] -----+----- +--* LSH long
[000035] -----+----- | +--* SUB long
[000012] -----+----- | | +--* LCL_VAR long V04 tmp1 (last use)
[000034] -----+---U- | | \--* CAST long <- ulong <- uint
[000033] -----+----- | | \--* MUL int
[000030] -----+----- | | +--* LCL_VAR int V01 loc0 (last use)
[000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
[000036] -----+----- | \--* CNS_INT int 32
[000041] ----G+---U- \--* CAST long <- ulong <- uint
[000040] n---G+----- \--* IND int
[000070] -----+----- \--* ADD byref
[000038] -----+----- +--* LCL_VAR byref V00 arg0
[000069] -----+----- \--* CNS_INT long 8
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
[000050] DA---+----- * STORE_LCL_VAR int V02 loc1
[000049] -----+----- \--* CAST int <- uint <- long
[000048] -----+----- \--* UDIV long
[000045] -----+----- +--* LCL_VAR long V05 tmp2
[000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
[000054] nA--G+----- * STOREIND int
[000072] -----+----- +--* ADD byref
[000051] -----+----- | +--* LCL_VAR byref V00 arg0 (last use)
[000071] -----+----- | \--* CNS_INT long 8
[000052] -----+----- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
[000060] -----+----- * RETURN int
[000059] -----+----- \--* SUB int
[000044] -----+----- +--* LCL_VAR int V05 tmp2 (last use)
[000058] -----+----- \--* MUL int
[000056] -----+----- +--* LCL_VAR int V02 loc1 (last use)
[000057] -----+----- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Post-Morph
*************** In fgMarkDemotedImplicitByRefArgs()
*************** Finishing PHASE Post-Morph
Trees after Post-Morph
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1
[000010] ---XG+----- \--* ADD long
[000005] ---XG+----- +--* LSH long
[000003] ---XG+---U- | +--* CAST long <- ulong <- uint
[000002] ---XG+----- | | \--* IND int
[000062] -----+----- | | \--* ADD byref
[000000] -----+----- | | +--* LCL_VAR byref V00 arg0
[000061] -----+----- | | \--* CNS_INT long 4
[000004] -----+----- | \--* CNS_INT int 32
[000009] ---XG+---U- \--* CAST long <- ulong <- uint
[000008] ---XG+----- \--* IND int
[000064] -----+----- \--* ADD byref
[000006] -----+----- +--* LCL_VAR byref V00 arg0
[000063] -----+----- \--* CNS_INT long 12
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
[000017] DA---+----- * STORE_LCL_VAR long V01 loc0
[000016] -----+----- \--* UDIV long
[000013] -----+----- +--* LCL_VAR long V04 tmp1
[000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
[000024] nA--G+----- * STOREIND int
[000066] -----+----- +--* ADD byref
[000018] -----+----- | +--* LCL_VAR byref V00 arg0
[000065] -----+----- | \--* CNS_INT long 4
[000022] -----+----- \--* CAST int <- uint <- long
[000021] -----+----- \--* RSZ long
[000019] -----+----- +--* LCL_VAR long V01 loc0
[000020] -----+----- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
[000029] nA--G+----- * STOREIND int
[000068] -----+----- +--* ADD byref
[000025] -----+----- | +--* LCL_VAR byref V00 arg0
[000067] -----+----- | \--* CNS_INT long 12
[000026] -----+----- \--* LCL_VAR int V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
[000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2
[000042] ----G+----- \--* ADD long
[000037] -----+----- +--* LSH long
[000035] -----+----- | +--* SUB long
[000012] -----+----- | | +--* LCL_VAR long V04 tmp1
[000034] -----+---U- | | \--* CAST long <- ulong <- uint
[000033] -----+----- | | \--* MUL int
[000030] -----+----- | | +--* LCL_VAR int V01 loc0
[000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
[000036] -----+----- | \--* CNS_INT int 32
[000041] ----G+---U- \--* CAST long <- ulong <- uint
[000040] n---G+----- \--* IND int
[000070] -----+----- \--* ADD byref
[000038] -----+----- +--* LCL_VAR byref V00 arg0
[000069] -----+----- \--* CNS_INT long 8
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
[000050] DA---+----- * STORE_LCL_VAR int V02 loc1
[000049] -----+----- \--* CAST int <- uint <- long
[000048] -----+----- \--* UDIV long
[000045] -----+----- +--* LCL_VAR long V05 tmp2
[000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
[000054] nA--G+----- * STOREIND int
[000072] -----+----- +--* ADD byref
[000051] -----+----- | +--* LCL_VAR byref V00 arg0
[000071] -----+----- | \--* CNS_INT long 8
[000052] -----+----- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
[000060] -----+----- * RETURN int
[000059] -----+----- \--* SUB int
[000044] -----+----- +--* LCL_VAR int V05 tmp2
[000058] -----+----- \--* MUL int
[000056] -----+----- +--* LCL_VAR int V02 loc1
[000057] -----+----- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie [no changes]
*************** Starting PHASE Compute block weights
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute block weights [no changes]
*************** Starting PHASE Remove empty finally 2
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 2 [no changes]
*************** Starting PHASE Remove empty try 2
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 2 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 2
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 2 [no changes]
*************** Starting PHASE Invert loops
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
*************** Finishing PHASE Invert loops
Trees after Invert loops
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1
[000010] ---XG+----- \--* ADD long
[000005] ---XG+----- +--* LSH long
[000003] ---XG+---U- | +--* CAST long <- ulong <- uint
[000002] ---XG+----- | | \--* IND int
[000062] -----+----- | | \--* ADD byref
[000000] -----+----- | | +--* LCL_VAR byref V00 arg0
[000061] -----+----- | | \--* CNS_INT long 4
[000004] -----+----- | \--* CNS_INT int 32
[000009] ---XG+---U- \--* CAST long <- ulong <- uint
[000008] ---XG+----- \--* IND int
[000064] -----+----- \--* ADD byref
[000006] -----+----- +--* LCL_VAR byref V00 arg0
[000063] -----+----- \--* CNS_INT long 12
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
[000017] DA---+----- * STORE_LCL_VAR long V01 loc0
[000016] -----+----- \--* UDIV long
[000013] -----+----- +--* LCL_VAR long V04 tmp1
[000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
[000024] nA--G+----- * STOREIND int
[000066] -----+----- +--* ADD byref
[000018] -----+----- | +--* LCL_VAR byref V00 arg0
[000065] -----+----- | \--* CNS_INT long 4
[000022] -----+----- \--* CAST int <- uint <- long
[000021] -----+----- \--* RSZ long
[000019] -----+----- +--* LCL_VAR long V01 loc0
[000020] -----+----- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
[000029] nA--G+----- * STOREIND int
[000068] -----+----- +--* ADD byref
[000025] -----+----- | +--* LCL_VAR byref V00 arg0
[000067] -----+----- | \--* CNS_INT long 12
[000026] -----+----- \--* LCL_VAR int V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
[000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2
[000042] ----G+----- \--* ADD long
[000037] -----+----- +--* LSH long
[000035] -----+----- | +--* SUB long
[000012] -----+----- | | +--* LCL_VAR long V04 tmp1
[000034] -----+---U- | | \--* CAST long <- ulong <- uint
[000033] -----+----- | | \--* MUL int
[000030] -----+----- | | +--* LCL_VAR int V01 loc0
[000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
[000036] -----+----- | \--* CNS_INT int 32
[000041] ----G+---U- \--* CAST long <- ulong <- uint
[000040] n---G+----- \--* IND int
[000070] -----+----- \--* ADD byref
[000038] -----+----- +--* LCL_VAR byref V00 arg0
[000069] -----+----- \--* CNS_INT long 8
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
[000050] DA---+----- * STORE_LCL_VAR int V02 loc1
[000049] -----+----- \--* CAST int <- uint <- long
[000048] -----+----- \--* UDIV long
[000045] -----+----- +--* LCL_VAR long V05 tmp2
[000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
[000054] nA--G+----- * STOREIND int
[000072] -----+----- +--* ADD byref
[000051] -----+----- | +--* LCL_VAR byref V00 arg0
[000071] -----+----- | \--* CNS_INT long 8
[000052] -----+----- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
[000060] -----+----- * RETURN int
[000059] -----+----- \--* SUB int
[000044] -----+----- +--* LCL_VAR int V05 tmp2
[000058] -----+----- \--* MUL int
[000056] -----+----- +--* LCL_VAR int V02 loc1
[000057] -----+----- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Optimize control flow
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** Finishing PHASE Optimize control flow [no changes]
*************** Starting PHASE Post-morph head and tail merge
*************** Finishing PHASE Post-morph head and tail merge
Trees after Post-morph head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1
[000010] ---XG+----- \--* ADD long
[000005] ---XG+----- +--* LSH long
[000003] ---XG+---U- | +--* CAST long <- ulong <- uint
[000002] ---XG+----- | | \--* IND int
[000062] -----+----- | | \--* ADD byref
[000000] -----+----- | | +--* LCL_VAR byref V00 arg0
[000061] -----+----- | | \--* CNS_INT long 4
[000004] -----+----- | \--* CNS_INT int 32
[000009] ---XG+---U- \--* CAST long <- ulong <- uint
[000008] ---XG+----- \--* IND int
[000064] -----+----- \--* ADD byref
[000006] -----+----- +--* LCL_VAR byref V00 arg0
[000063] -----+----- \--* CNS_INT long 12
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
[000017] DA---+----- * STORE_LCL_VAR long V01 loc0
[000016] -----+----- \--* UDIV long
[000013] -----+----- +--* LCL_VAR long V04 tmp1
[000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
[000024] nA--G+----- * STOREIND int
[000066] -----+----- +--* ADD byref
[000018] -----+----- | +--* LCL_VAR byref V00 arg0
[000065] -----+----- | \--* CNS_INT long 4
[000022] -----+----- \--* CAST int <- uint <- long
[000021] -----+----- \--* RSZ long
[000019] -----+----- +--* LCL_VAR long V01 loc0
[000020] -----+----- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
[000029] nA--G+----- * STOREIND int
[000068] -----+----- +--* ADD byref
[000025] -----+----- | +--* LCL_VAR byref V00 arg0
[000067] -----+----- | \--* CNS_INT long 12
[000026] -----+----- \--* LCL_VAR int V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
[000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2
[000042] ----G+----- \--* ADD long
[000037] -----+----- +--* LSH long
[000035] -----+----- | +--* SUB long
[000012] -----+----- | | +--* LCL_VAR long V04 tmp1
[000034] -----+---U- | | \--* CAST long <- ulong <- uint
[000033] -----+----- | | \--* MUL int
[000030] -----+----- | | +--* LCL_VAR int V01 loc0
[000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
[000036] -----+----- | \--* CNS_INT int 32
[000041] ----G+---U- \--* CAST long <- ulong <- uint
[000040] n---G+----- \--* IND int
[000070] -----+----- \--* ADD byref
[000038] -----+----- +--* LCL_VAR byref V00 arg0
[000069] -----+----- \--* CNS_INT long 8
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
[000050] DA---+----- * STORE_LCL_VAR int V02 loc1
[000049] -----+----- \--* CAST int <- uint <- long
[000048] -----+----- \--* UDIV long
[000045] -----+----- +--* LCL_VAR long V05 tmp2
[000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
[000054] nA--G+----- * STOREIND int
[000072] -----+----- +--* ADD byref
[000051] -----+----- | +--* LCL_VAR byref V00 arg0
[000071] -----+----- | \--* CNS_INT long 8
[000052] -----+----- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
[000060] -----+----- * RETURN int
[000059] -----+----- \--* SUB int
[000044] -----+----- +--* LCL_VAR int V05 tmp2
[000058] -----+----- \--* MUL int
[000056] -----+----- +--* LCL_VAR int V02 loc1
[000057] -----+----- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE DFS blocks and remove dead code 3
*************** Finishing PHASE DFS blocks and remove dead code 3 [no changes]
*************** Starting PHASE Find loops
*************** In optFindLoopsPhase()
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
*************** Finishing PHASE Find loops
Trees after Find loops
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1
[000010] ---XG+----- \--* ADD long
[000005] ---XG+----- +--* LSH long
[000003] ---XG+---U- | +--* CAST long <- ulong <- uint
[000002] ---XG+----- | | \--* IND int
[000062] -----+----- | | \--* ADD byref
[000000] -----+----- | | +--* LCL_VAR byref V00 arg0
[000061] -----+----- | | \--* CNS_INT long 4
[000004] -----+----- | \--* CNS_INT int 32
[000009] ---XG+---U- \--* CAST long <- ulong <- uint
[000008] ---XG+----- \--* IND int
[000064] -----+----- \--* ADD byref
[000006] -----+----- +--* LCL_VAR byref V00 arg0
[000063] -----+----- \--* CNS_INT long 12
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
[000017] DA---+----- * STORE_LCL_VAR long V01 loc0
[000016] -----+----- \--* UDIV long
[000013] -----+----- +--* LCL_VAR long V04 tmp1
[000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
[000024] nA--G+----- * STOREIND int
[000066] -----+----- +--* ADD byref
[000018] -----+----- | +--* LCL_VAR byref V00 arg0
[000065] -----+----- | \--* CNS_INT long 4
[000022] -----+----- \--* CAST int <- uint <- long
[000021] -----+----- \--* RSZ long
[000019] -----+----- +--* LCL_VAR long V01 loc0
[000020] -----+----- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
[000029] nA--G+----- * STOREIND int
[000068] -----+----- +--* ADD byref
[000025] -----+----- | +--* LCL_VAR byref V00 arg0
[000067] -----+----- | \--* CNS_INT long 12
[000026] -----+----- \--* LCL_VAR int V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
[000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2
[000042] ----G+----- \--* ADD long
[000037] -----+----- +--* LSH long
[000035] -----+----- | +--* SUB long
[000012] -----+----- | | +--* LCL_VAR long V04 tmp1
[000034] -----+---U- | | \--* CAST long <- ulong <- uint
[000033] -----+----- | | \--* MUL int
[000030] -----+----- | | +--* LCL_VAR int V01 loc0
[000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
[000036] -----+----- | \--* CNS_INT int 32
[000041] ----G+---U- \--* CAST long <- ulong <- uint
[000040] n---G+----- \--* IND int
[000070] -----+----- \--* ADD byref
[000038] -----+----- +--* LCL_VAR byref V00 arg0
[000069] -----+----- \--* CNS_INT long 8
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
[000050] DA---+----- * STORE_LCL_VAR int V02 loc1
[000049] -----+----- \--* CAST int <- uint <- long
[000048] -----+----- \--* UDIV long
[000045] -----+----- +--* LCL_VAR long V05 tmp2
[000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
[000054] nA--G+----- * STOREIND int
[000072] -----+----- +--* ADD byref
[000051] -----+----- | +--* LCL_VAR byref V00 arg0
[000071] -----+----- | \--* CNS_INT long 8
[000052] -----+----- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
[000060] -----+----- * RETURN int
[000059] -----+----- \--* SUB int
[000044] -----+----- +--* LCL_VAR int V05 tmp2
[000058] -----+----- \--* MUL int
[000056] -----+----- +--* LCL_VAR int V02 loc1
[000057] -----+----- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Repair profile post-morph
No PGO data. Skipping profile repair.
*************** Finishing PHASE Repair profile post-morph [no changes]
*************** Starting PHASE Set block weights
After computing the dominance tree:
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
Return blocks: BB01
*************** Finishing PHASE Set block weights [no changes]
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
No loops to clone
*************** Finishing PHASE Clone loops [no changes]
*************** Starting PHASE Unroll loops
*************** Finishing PHASE Unroll loops [no changes]
*************** Starting PHASE Compute dominators
*************** Finishing PHASE Compute dominators [no changes]
*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function
*************** Finishing PHASE Morph array ops [no changes]
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1)
STMT00000 ( 0x000[E-] ... 0x01A )
[000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1
[000010] ---XG+----- \--* ADD long
[000005] ---XG+----- +--* LSH long
[000003] ---XG+---U- | +--* CAST long <- ulong <- uint
[000002] ---XG+----- | | \--* IND int
[000062] -----+----- | | \--* ADD byref
[000000] -----+----- | | +--* LCL_VAR byref V00 arg0
[000061] -----+----- | | \--* CNS_INT long 4
[000004] -----+----- | \--* CNS_INT int 32
[000009] ---XG+---U- \--* CAST long <- ulong <- uint
[000008] ---XG+----- \--* IND int
[000064] -----+----- \--* ADD byref
[000006] -----+----- +--* LCL_VAR byref V00 arg0
[000063] -----+----- \--* CNS_INT long 12
New refCnts for V04: refCnt = 1, refCntWtd = 2
V04 needs explicit zero init. Disqualified as a single-def register candidate.
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
STMT00001 ( ??? ... ??? )
[000017] DA---+----- * STORE_LCL_VAR long V01 loc0
[000016] -----+----- \--* UDIV long
[000013] -----+----- +--* LCL_VAR long V04 tmp1
[000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
New refCnts for V01: refCnt = 1, refCntWtd = 1
V01 needs explicit zero init. Disqualified as a single-def register candidate.
New refCnts for V04: refCnt = 2, refCntWtd = 4
STMT00002 ( ??? ... 0x021 )
[000024] nA--G+----- * STOREIND int
[000066] -----+----- +--* ADD byref
[000018] -----+----- | +--* LCL_VAR byref V00 arg0
[000065] -----+----- | \--* CNS_INT long 4
[000022] -----+----- \--* CAST int <- uint <- long
[000021] -----+----- \--* RSZ long
[000019] -----+----- +--* LCL_VAR long V01 loc0
[000020] -----+----- \--* CNS_INT int 32
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 2, refCntWtd = 2
STMT00003 ( ??? ... 0x029 )
[000029] nA--G+----- * STOREIND int
[000068] -----+----- +--* ADD byref
[000025] -----+----- | +--* LCL_VAR byref V00 arg0
[000067] -----+----- | \--* CNS_INT long 12
[000026] -----+----- \--* LCL_VAR int V01 loc0
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 3, refCntWtd = 3
STMT00004 ( ??? ... 0x04C )
[000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2
[000042] ----G+----- \--* ADD long
[000037] -----+----- +--* LSH long
[000035] -----+----- | +--* SUB long
[000012] -----+----- | | +--* LCL_VAR long V04 tmp1
[000034] -----+---U- | | \--* CAST long <- ulong <- uint
[000033] -----+----- | | \--* MUL int
[000030] -----+----- | | +--* LCL_VAR int V01 loc0
[000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
[000036] -----+----- | \--* CNS_INT int 32
[000041] ----G+---U- \--* CAST long <- ulong <- uint
[000040] n---G+----- \--* IND int
[000070] -----+----- \--* ADD byref
[000038] -----+----- +--* LCL_VAR byref V00 arg0
[000069] -----+----- \--* CNS_INT long 8
New refCnts for V05: refCnt = 1, refCntWtd = 2
V05 needs explicit zero init. Disqualified as a single-def register candidate.
New refCnts for V04: refCnt = 3, refCntWtd = 6
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V00: refCnt = 5, refCntWtd = 5
STMT00005 ( ??? ... ??? )
[000050] DA---+----- * STORE_LCL_VAR int V02 loc1
[000049] -----+----- \--* CAST int <- uint <- long
[000048] -----+----- \--* UDIV long
[000045] -----+----- +--* LCL_VAR long V05 tmp2
[000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
New refCnts for V02: refCnt = 1, refCntWtd = 1
V02 needs explicit zero init. Disqualified as a single-def register candidate.
New refCnts for V05: refCnt = 2, refCntWtd = 4
STMT00006 ( ??? ... 0x04F )
[000054] nA--G+----- * STOREIND int
[000072] -----+----- +--* ADD byref
[000051] -----+----- | +--* LCL_VAR byref V00 arg0
[000071] -----+----- | \--* CNS_INT long 8
[000052] -----+----- \--* LCL_VAR int V02 loc1
New refCnts for V00: refCnt = 6, refCntWtd = 6
New refCnts for V02: refCnt = 2, refCntWtd = 2
STMT00007 ( ??? ... 0x05D )
[000060] -----+----- * RETURN int
[000059] -----+----- \--* SUB int
[000044] -----+----- +--* LCL_VAR int V05 tmp2
[000058] -----+----- \--* MUL int
[000056] -----+----- +--* LCL_VAR int V02 loc1
[000057] -----+----- \--* CNS_INT int 0x3B9ACA00
New refCnts for V05: refCnt = 3, refCntWtd = 6
New refCnts for V02: refCnt = 3, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 7, refCntWtd = 7
New refCnts for V00: refCnt = 8, refCntWtd = 8
*************** Finishing PHASE Mark local vars [no changes]
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
Trees after Find oper order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
( 13, 15) [000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1
( 13, 15) [000010] ---XG+----- \--* ADD long
( 7, 8) [000005] ---XG+----- +--* LSH long
( 5, 6) [000003] ---XG+---U- | +--* CAST long <- ulong <- uint
( 4, 4) [000002] ---XG+----- | | \--* IND int
( 2, 2) [000062] -----+-N--- | | \--* ADD byref
( 1, 1) [000000] -----+----- | | +--* LCL_VAR byref V00 arg0
( 1, 1) [000061] -----+----- | | \--* CNS_INT long 4
( 1, 1) [000004] -----+----- | \--* CNS_INT int 32
( 5, 6) [000009] ---XG+---U- \--* CAST long <- ulong <- uint
( 4, 4) [000008] ---XG+----- \--* IND int
( 2, 2) [000064] -----+-N--- \--* ADD byref
( 1, 1) [000006] -----+----- +--* LCL_VAR byref V00 arg0
( 1, 1) [000063] -----+----- \--* CNS_INT long 12
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
( 22, 8) [000017] DA---+----- * STORE_LCL_VAR long V01 loc0
( 22, 8) [000016] -----+----- \--* UDIV long
( 1, 1) [000013] -----+----- +--* LCL_VAR long V04 tmp1
( 1, 4) [000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
( 9, 10) [000024] nA--G+--R-- * STOREIND int
( 2, 2) [000066] -----+-N--- +--* ADD byref
( 1, 1) [000018] -----+----- | +--* LCL_VAR byref V00 arg0
( 1, 1) [000065] -----+----- | \--* CNS_INT long 4
( 4, 5) [000022] -----+----- \--* CAST int <- uint <- long
( 3, 3) [000021] -----+----- \--* RSZ long
( 1, 1) [000019] -----+----- +--* LCL_VAR long V01 loc0
( 1, 1) [000020] -----+----- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
( 6, 6) [000029] nA--G+----- * STOREIND int
( 2, 2) [000068] -----+-N--- +--* ADD byref
( 1, 1) [000025] -----+----- | +--* LCL_VAR byref V00 arg0
( 1, 1) [000067] -----+----- | \--* CNS_INT long 12
( 1, 1) [000026] -----+----- \--* LCL_VAR int V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2
( 17, 21) [000042] ----G+----- \--* ADD long
( 11, 14) [000037] -----+----- +--* LSH long
( 9, 12) [000035] -----+----- | +--* SUB long
( 1, 1) [000012] -----+----- | | +--* LCL_VAR long V04 tmp1
( 7, 10) [000034] -----+---U- | | \--* CAST long <- ulong <- uint
( 6, 8) [000033] -----+----- | | \--* MUL int
( 1, 1) [000030] -----+----- | | +--* LCL_VAR int V01 loc0
( 1, 4) [000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
( 1, 1) [000036] -----+----- | \--* CNS_INT int 32
( 5, 6) [000041] ----G+---U- \--* CAST long <- ulong <- uint
( 4, 4) [000040] n---G+----- \--* IND int
( 2, 2) [000070] -----+-N--- \--* ADD byref
( 1, 1) [000038] -----+----- +--* LCL_VAR byref V00 arg0
( 1, 1) [000069] -----+----- \--* CNS_INT long 8
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
( 23, 10) [000050] DA---+----- * STORE_LCL_VAR int V02 loc1
( 23, 10) [000049] -----+----- \--* CAST int <- uint <- long
( 22, 8) [000048] -----+----- \--* UDIV long
( 1, 1) [000045] -----+----- +--* LCL_VAR long V05 tmp2
( 1, 4) [000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
( 6, 6) [000054] nA--G+----- * STOREIND int
( 2, 2) [000072] -----+-N--- +--* ADD byref
( 1, 1) [000051] -----+----- | +--* LCL_VAR byref V00 arg0
( 1, 1) [000071] -----+----- | \--* CNS_INT long 8
( 1, 1) [000052] -----+----- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
( 9, 11) [000060] -----+----- * RETURN int
( 8, 10) [000059] -----+----- \--* SUB int
( 1, 1) [000044] -----+----- +--* LCL_VAR int V05 tmp2
( 6, 8) [000058] -----+----- \--* MUL int
( 1, 1) [000056] -----+----- +--* LCL_VAR int V02 loc1
( 1, 4) [000057] -----+----- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 15 tree nodes
*************** Finishing PHASE Set block order
Trees after Set block order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
N014 ( 13, 15) [000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1
N013 ( 13, 15) [000010] ---XG+----- \--* ADD long
N007 ( 7, 8) [000005] ---XG+----- +--* LSH long
N005 ( 5, 6) [000003] ---XG+---U- | +--* CAST long <- ulong <- uint
N004 ( 4, 4) [000002] ---XG+----- | | \--* IND int
N003 ( 2, 2) [000062] -----+-N--- | | \--* ADD byref
N001 ( 1, 1) [000000] -----+----- | | +--* LCL_VAR byref V00 arg0
N002 ( 1, 1) [000061] -----+----- | | \--* CNS_INT long 4
N006 ( 1, 1) [000004] -----+----- | \--* CNS_INT int 32
N012 ( 5, 6) [000009] ---XG+---U- \--* CAST long <- ulong <- uint
N011 ( 4, 4) [000008] ---XG+----- \--* IND int
N010 ( 2, 2) [000064] -----+-N--- \--* ADD byref
N008 ( 1, 1) [000006] -----+----- +--* LCL_VAR byref V00 arg0
N009 ( 1, 1) [000063] -----+----- \--* CNS_INT long 12
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
N004 ( 22, 8) [000017] DA---+----- * STORE_LCL_VAR long V01 loc0
N003 ( 22, 8) [000016] -----+----- \--* UDIV long
N001 ( 1, 1) [000013] -----+----- +--* LCL_VAR long V04 tmp1
N002 ( 1, 4) [000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
N008 ( 9, 10) [000024] nA--G+--R-- * STOREIND int
N007 ( 2, 2) [000066] -----+-N--- +--* ADD byref
N005 ( 1, 1) [000018] -----+----- | +--* LCL_VAR byref V00 arg0
N006 ( 1, 1) [000065] -----+----- | \--* CNS_INT long 4
N004 ( 4, 5) [000022] -----+----- \--* CAST int <- uint <- long
N003 ( 3, 3) [000021] -----+----- \--* RSZ long
N001 ( 1, 1) [000019] -----+----- +--* LCL_VAR long V01 loc0
N002 ( 1, 1) [000020] -----+----- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int
N003 ( 2, 2) [000068] -----+-N--- +--* ADD byref
N001 ( 1, 1) [000025] -----+----- | +--* LCL_VAR byref V00 arg0
N002 ( 1, 1) [000067] -----+----- | \--* CNS_INT long 12
N004 ( 1, 1) [000026] -----+----- \--* LCL_VAR int V01 loc0
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2
N014 ( 17, 21) [000042] ----G+----- \--* ADD long
N008 ( 11, 14) [000037] -----+----- +--* LSH long
N006 ( 9, 12) [000035] -----+----- | +--* SUB long
N001 ( 1, 1) [000012] -----+----- | | +--* LCL_VAR long V04 tmp1
N005 ( 7, 10) [000034] -----+---U- | | \--* CAST long <- ulong <- uint
N004 ( 6, 8) [000033] -----+----- | | \--* MUL int
N002 ( 1, 1) [000030] -----+----- | | +--* LCL_VAR int V01 loc0
N003 ( 1, 4) [000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
N007 ( 1, 1) [000036] -----+----- | \--* CNS_INT int 32
N013 ( 5, 6) [000041] ----G+---U- \--* CAST long <- ulong <- uint
N012 ( 4, 4) [000040] n---G+----- \--* IND int
N011 ( 2, 2) [000070] -----+-N--- \--* ADD byref
N009 ( 1, 1) [000038] -----+----- +--* LCL_VAR byref V00 arg0
N010 ( 1, 1) [000069] -----+----- \--* CNS_INT long 8
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
N005 ( 23, 10) [000050] DA---+----- * STORE_LCL_VAR int V02 loc1
N004 ( 23, 10) [000049] -----+----- \--* CAST int <- uint <- long
N003 ( 22, 8) [000048] -----+----- \--* UDIV long
N001 ( 1, 1) [000045] -----+----- +--* LCL_VAR long V05 tmp2
N002 ( 1, 4) [000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int
N003 ( 2, 2) [000072] -----+-N--- +--* ADD byref
N001 ( 1, 1) [000051] -----+----- | +--* LCL_VAR byref V00 arg0
N002 ( 1, 1) [000071] -----+----- | \--* CNS_INT long 8
N004 ( 1, 1) [000052] -----+----- \--* LCL_VAR int V02 loc1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
N006 ( 9, 11) [000060] -----+----- * RETURN int
N005 ( 8, 10) [000059] -----+----- \--* SUB int
N001 ( 1, 1) [000044] -----+----- +--* LCL_VAR int V05 tmp2
N004 ( 6, 8) [000058] -----+----- \--* MUL int
N002 ( 1, 1) [000056] -----+----- +--* LCL_VAR int V02 loc1
N003 ( 1, 4) [000057] -----+----- \--* CNS_INT int 0x3B9ACA00
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Local V03 should not be enregistered because: struct size does not match reg size
Tracked variable (5 out of 6) table:
V00 arg0 [ byref]: refCnt = 8, refCntWtd = 8
V04 tmp1 [ long]: refCnt = 3, refCntWtd = 6
V05 tmp2 [ long]: refCnt = 3, refCntWtd = 6
V01 loc0 [ long]: refCnt = 4, refCntWtd = 4
V02 loc1 [ int]: refCnt = 3, refCntWtd = 3
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(4)={ V04 V05 V01 V02} + ByrefExposed + GcHeap
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
*************** In optRemoveRedundantZeroInits()
Analyzing BB01
Marking V04 as having an explicit init
Marking V01 as having an explicit init
Marking V05 as having an explicit init
Marking V02 as having an explicit init
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
V00.1: defined in BB00 6 uses (global)
V01.1: defined in BB01 3 uses (local)
V02.1: defined in BB01 2 uses (local)
V04.1: defined in BB01 2 uses (local)
V05.1: defined in BB01 2 uses (local)
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
N014 ( 13, 15) [000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1 d:1
N013 ( 13, 15) [000010] ---XG+----- \--* ADD long
N007 ( 7, 8) [000005] ---XG+----- +--* LSH long
N005 ( 5, 6) [000003] ---XG+---U- | +--* CAST long <- ulong <- uint
N004 ( 4, 4) [000002] ---XG+----- | | \--* IND int
N003 ( 2, 2) [000062] -----+-N--- | | \--* ADD byref
N001 ( 1, 1) [000000] -----+----- | | +--* LCL_VAR byref V00 arg0 u:1
N002 ( 1, 1) [000061] -----+----- | | \--* CNS_INT long 4
N006 ( 1, 1) [000004] -----+----- | \--* CNS_INT int 32
N012 ( 5, 6) [000009] ---XG+---U- \--* CAST long <- ulong <- uint
N011 ( 4, 4) [000008] ---XG+----- \--* IND int
N010 ( 2, 2) [000064] -----+-N--- \--* ADD byref
N008 ( 1, 1) [000006] -----+----- +--* LCL_VAR byref V00 arg0 u:1
N009 ( 1, 1) [000063] -----+----- \--* CNS_INT long 12
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
N004 ( 22, 8) [000017] DA---+----- * STORE_LCL_VAR long V01 loc0 d:1
N003 ( 22, 8) [000016] -----+----- \--* UDIV long
N001 ( 1, 1) [000013] -----+----- +--* LCL_VAR long V04 tmp1 u:1
N002 ( 1, 4) [000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
N008 ( 9, 10) [000024] nA--G+--R-- * STOREIND int
N007 ( 2, 2) [000066] -----+-N--- +--* ADD byref
N005 ( 1, 1) [000018] -----+----- | +--* LCL_VAR byref V00 arg0 u:1
N006 ( 1, 1) [000065] -----+----- | \--* CNS_INT long 4
N004 ( 4, 5) [000022] -----+----- \--* CAST int <- uint <- long
N003 ( 3, 3) [000021] -----+----- \--* RSZ long
N001 ( 1, 1) [000019] -----+----- +--* LCL_VAR long V01 loc0 u:1
N002 ( 1, 1) [000020] -----+----- \--* CNS_INT int 32
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int
N003 ( 2, 2) [000068] -----+-N--- +--* ADD byref
N001 ( 1, 1) [000025] -----+----- | +--* LCL_VAR byref V00 arg0 u:1
N002 ( 1, 1) [000067] -----+----- | \--* CNS_INT long 12
N004 ( 1, 1) [000026] -----+----- \--* LCL_VAR int V01 loc0 u:1
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1
N014 ( 17, 21) [000042] ----G+----- \--* ADD long
N008 ( 11, 14) [000037] -----+----- +--* LSH long
N006 ( 9, 12) [000035] -----+----- | +--* SUB long
N001 ( 1, 1) [000012] -----+----- | | +--* LCL_VAR long V04 tmp1 u:1 (last use)
N005 ( 7, 10) [000034] -----+---U- | | \--* CAST long <- ulong <- uint
N004 ( 6, 8) [000033] -----+----- | | \--* MUL int
N002 ( 1, 1) [000030] -----+----- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N003 ( 1, 4) [000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
N007 ( 1, 1) [000036] -----+----- | \--* CNS_INT int 32
N013 ( 5, 6) [000041] ----G+---U- \--* CAST long <- ulong <- uint
N012 ( 4, 4) [000040] n---G+----- \--* IND int
N011 ( 2, 2) [000070] -----+-N--- \--* ADD byref
N009 ( 1, 1) [000038] -----+----- +--* LCL_VAR byref V00 arg0 u:1
N010 ( 1, 1) [000069] -----+----- \--* CNS_INT long 8
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
N005 ( 23, 10) [000050] DA---+----- * STORE_LCL_VAR int V02 loc1 d:1
N004 ( 23, 10) [000049] -----+----- \--* CAST int <- uint <- long
N003 ( 22, 8) [000048] -----+----- \--* UDIV long
N001 ( 1, 1) [000045] -----+----- +--* LCL_VAR long V05 tmp2 u:1
N002 ( 1, 4) [000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int
N003 ( 2, 2) [000072] -----+-N--- +--* ADD byref
N001 ( 1, 1) [000051] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 (last use)
N002 ( 1, 1) [000071] -----+----- | \--* CNS_INT long 8
N004 ( 1, 1) [000052] -----+----- \--* LCL_VAR int V02 loc1 u:1
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
N006 ( 9, 11) [000060] -----+----- * RETURN int
N005 ( 8, 10) [000059] -----+----- \--* SUB int
N001 ( 1, 1) [000044] -----+----- +--* LCL_VAR int V05 tmp2 u:1 (last use)
N004 ( 6, 8) [000058] -----+----- \--* MUL int
N002 ( 1, 1) [000056] -----+----- +--* LCL_VAR int V02 loc1 u:1 (last use)
N003 ( 1, 4) [000057] -----+----- \--* CNS_INT int 0x3B9ACA00
SSA MEM: ByrefExposed, GcHeap = m:2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
SSA checks completed successfully
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method
*************** Finishing PHASE Early Value Propagation [no changes]
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
Visiting BB01
The SSA definition for ByrefExposed (#1) at start of BB01 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB01 is $c0 {InitVal($41)}
***** BB01, STMT00000(before)
N014 ( 13, 15) [000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1 d:1
N013 ( 13, 15) [000010] ---XG+----- \--* ADD long
N007 ( 7, 8) [000005] ---XG+----- +--* LSH long
N005 ( 5, 6) [000003] ---XG+---U- | +--* CAST long <- ulong <- uint
N004 ( 4, 4) [000002] ---XG+----- | | \--* IND int
N003 ( 2, 2) [000062] -----+-N--- | | \--* ADD byref
N001 ( 1, 1) [000000] -----+----- | | +--* LCL_VAR byref V00 arg0 u:1
N002 ( 1, 1) [000061] -----+----- | | \--* CNS_INT long 4
N006 ( 1, 1) [000004] -----+----- | \--* CNS_INT int 32
N012 ( 5, 6) [000009] ---XG+---U- \--* CAST long <- ulong <- uint
N011 ( 4, 4) [000008] ---XG+----- \--* IND int
N010 ( 2, 2) [000064] -----+-N--- \--* ADD byref
N008 ( 1, 1) [000006] -----+----- +--* LCL_VAR byref V00 arg0 u:1
N009 ( 1, 1) [000063] -----+----- \--* CNS_INT long 12
N001 [000000] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N002 [000061] CNS_INT 4 => $100 {LngCns 4}
N003 [000062] ADD => $140 {ADD($80, $100)}
N004 [000002] IND => <l:$281 {norm=$180 {ByrefExposedLoad($42, $140, $c0)}, exc=$240 {NullPtrExc($80)}}, c:$280 {norm=$1c0 {MemOpaque:NotInLoop}, exc=$240 {NullPtrExc($80)}}>
N005 [000003] CAST => <l:$2c1 {norm=$2c0 {$180, long <- ulong <- uint}, exc=$240 {NullPtrExc($80)}}, c:$2c3 {norm=$2c2 {$1c0, long <- ulong <- uint}, exc=$240 {NullPtrExc($80)}}>
N006 [000004] CNS_INT 32 => $44 {IntCns 32}
N007 [000005] LSH => <l:$2c7 {norm=$2c4 {LSH($2c0, $44)}, exc=$240 {NullPtrExc($80)}}, c:$2c6 {norm=$2c5 {LSH($2c2, $44)}, exc=$240 {NullPtrExc($80)}}>
N008 [000006] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N009 [000063] CNS_INT 12 => $102 {LngCns 12}
N010 [000064] ADD => $141 {ADD($80, $102)}
N011 [000008] IND => <l:$283 {norm=$181 {ByrefExposedLoad($42, $141, $c0)}, exc=$240 {NullPtrExc($80)}}, c:$282 {norm=$1c1 {MemOpaque:NotInLoop}, exc=$240 {NullPtrExc($80)}}>
N012 [000009] CAST => <l:$2c9 {norm=$2c8 {$181, long <- ulong <- uint}, exc=$240 {NullPtrExc($80)}}, c:$2cb {norm=$2ca {$1c1, long <- ulong <- uint}, exc=$240 {NullPtrExc($80)}}>
N013 [000010] ADD => <l:$2cf {norm=$2cc {ADD($2c4, $2c8)}, exc=$240 {NullPtrExc($80)}}, c:$2ce {norm=$2cd {ADD($2c5, $2ca)}, exc=$240 {NullPtrExc($80)}}>
Tree [000011] assigned VN to local var V04/1: <l:$2cc {ADD($2c4, $2c8)}, c:$2cd {ADD($2c5, $2ca)}>
N014 [000011] STORE_LCL_VAR V04 tmp1 d:1 => $241 {norm=$VN.Void, exc=$240 {NullPtrExc($80)}}
***** BB01, STMT00000(after)
N014 ( 13, 15) [000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
N013 ( 13, 15) [000010] ---XG+----- \--* ADD long <l:$2cf, c:$2ce>
N007 ( 7, 8) [000005] ---XG+----- +--* LSH long <l:$2c7, c:$2c6>
N005 ( 5, 6) [000003] ---XG+---U- | +--* CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N004 ( 4, 4) [000002] ---XG+----- | | \--* IND int <l:$281, c:$280>
N003 ( 2, 2) [000062] -----+-N--- | | \--* ADD byref $140
N001 ( 1, 1) [000000] -----+----- | | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000061] -----+----- | | \--* CNS_INT long 4 $100
N006 ( 1, 1) [000004] -----+----- | \--* CNS_INT int 32 $44
N012 ( 5, 6) [000009] ---XG+---U- \--* CAST long <- ulong <- uint <l:$2c9, c:$2cb>
N011 ( 4, 4) [000008] ---XG+----- \--* IND int <l:$283, c:$282>
N010 ( 2, 2) [000064] -----+-N--- \--* ADD byref $141
N008 ( 1, 1) [000006] -----+----- +--* LCL_VAR byref V00 arg0 u:1 $80
N009 ( 1, 1) [000063] -----+----- \--* CNS_INT long 12 $102
---------
***** BB01, STMT00001(before)
N004 ( 22, 8) [000017] DA---+----- * STORE_LCL_VAR long V01 loc0 d:1
N003 ( 22, 8) [000016] -----+----- \--* UDIV long
N001 ( 1, 1) [000013] -----+----- +--* LCL_VAR long V04 tmp1 u:1
N002 ( 1, 4) [000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00
N001 [000013] LCL_VAR V04 tmp1 u:1 => <l:$2cc {ADD($2c4, $2c8)}, c:$2cd {ADD($2c5, $2ca)}>
N002 [000015] CNS_INT 0x3B9ACA00 => $103 {LngCns 0x3B9ACA00}
N003 [000016] UDIV => <l:$2d0 {UDIV($2cc, $103)}, c:$2d1 {UDIV($2cd, $103)}>
Tree [000017] assigned VN to local var V01/1: <l:$2d0 {UDIV($2cc, $103)}, c:$2d1 {UDIV($2cd, $103)}>
N004 [000017] STORE_LCL_VAR V01 loc0 d:1 => $VN.Void
***** BB01, STMT00001(after)
N004 ( 22, 8) [000017] DA---+----- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
N003 ( 22, 8) [000016] -----+----- \--* UDIV long <l:$2d0, c:$2d1>
N001 ( 1, 1) [000013] -----+----- +--* LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00 $103
---------
***** BB01, STMT00002(before)
N008 ( 9, 10) [000024] nA--G+--R-- * STOREIND int
N007 ( 2, 2) [000066] -----+-N--- +--* ADD byref
N005 ( 1, 1) [000018] -----+----- | +--* LCL_VAR byref V00 arg0 u:1
N006 ( 1, 1) [000065] -----+----- | \--* CNS_INT long 4
N004 ( 4, 5) [000022] -----+----- \--* CAST int <- uint <- long
N003 ( 3, 3) [000021] -----+----- \--* RSZ long
N001 ( 1, 1) [000019] -----+----- +--* LCL_VAR long V01 loc0 u:1
N002 ( 1, 1) [000020] -----+----- \--* CNS_INT int 32
N001 [000019] LCL_VAR V01 loc0 u:1 => <l:$2d0 {UDIV($2cc, $103)}, c:$2d1 {UDIV($2cd, $103)}>
N002 [000020] CNS_INT 32 => $44 {IntCns 32}
N003 [000021] RSZ => <l:$2d2 {RSZ($2d0, $44)}, c:$2d3 {RSZ($2d1, $44)}>
N004 [000022] CAST => <l:$284 {$2d2, int <- uint <- long}, c:$285 {$2d3, int <- uint <- long}>
N005 [000018] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N006 [000065] CNS_INT 4 => $100 {LngCns 4}
N007 [000066] ADD => $140 {ADD($80, $100)}
fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000024] to VN: $c1.
N008 [000024] STOREIND => $VN.Void
***** BB01, STMT00002(after)
N008 ( 9, 10) [000024] nA--G+--R-- * STOREIND int $VN.Void
N007 ( 2, 2) [000066] -----+-N--- +--* ADD byref $140
N005 ( 1, 1) [000018] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 $80
N006 ( 1, 1) [000065] -----+----- | \--* CNS_INT long 4 $100
N004 ( 4, 5) [000022] -----+----- \--* CAST int <- uint <- long <l:$284, c:$285>
N003 ( 3, 3) [000021] -----+----- \--* RSZ long <l:$2d2, c:$2d3>
N001 ( 1, 1) [000019] -----+----- +--* LCL_VAR long V01 loc0 u:1 <l:$2d0, c:$2d1>
N002 ( 1, 1) [000020] -----+----- \--* CNS_INT int 32 $44
---------
***** BB01, STMT00003(before)
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int
N003 ( 2, 2) [000068] -----+-N--- +--* ADD byref
N001 ( 1, 1) [000025] -----+----- | +--* LCL_VAR byref V00 arg0 u:1
N002 ( 1, 1) [000067] -----+----- | \--* CNS_INT long 12
N004 ( 1, 1) [000026] -----+----- \--* LCL_VAR int V01 loc0 u:1
N001 [000025] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N002 [000067] CNS_INT 12 => $102 {LngCns 12}
N003 [000068] ADD => $141 {ADD($80, $102)}
N004 [000026] LCL_VAR V01 loc0 u:1 => <l:$286 {$2d0, int <- long}, c:$287 {$2d1, int <- long}>
fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000029] to VN: $c2.
N005 [000029] STOREIND => $VN.Void
***** BB01, STMT00003(after)
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int $VN.Void
N003 ( 2, 2) [000068] -----+-N--- +--* ADD byref $141
N001 ( 1, 1) [000025] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000067] -----+----- | \--* CNS_INT long 12 $102
N004 ( 1, 1) [000026] -----+----- \--* LCL_VAR int V01 loc0 u:1 <l:$286, c:$287>
---------
***** BB01, STMT00004(before)
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1
N014 ( 17, 21) [000042] ----G+----- \--* ADD long
N008 ( 11, 14) [000037] -----+----- +--* LSH long
N006 ( 9, 12) [000035] -----+----- | +--* SUB long
N001 ( 1, 1) [000012] -----+----- | | +--* LCL_VAR long V04 tmp1 u:1 (last use)
N005 ( 7, 10) [000034] -----+---U- | | \--* CAST long <- ulong <- uint
N004 ( 6, 8) [000033] -----+----- | | \--* MUL int
N002 ( 1, 1) [000030] -----+----- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N003 ( 1, 4) [000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00
N007 ( 1, 1) [000036] -----+----- | \--* CNS_INT int 32
N013 ( 5, 6) [000041] ----G+---U- \--* CAST long <- ulong <- uint
N012 ( 4, 4) [000040] n---G+----- \--* IND int
N011 ( 2, 2) [000070] -----+-N--- \--* ADD byref
N009 ( 1, 1) [000038] -----+----- +--* LCL_VAR byref V00 arg0 u:1
N010 ( 1, 1) [000069] -----+----- \--* CNS_INT long 8
N001 [000012] LCL_VAR V04 tmp1 u:1 (last use) => <l:$2cc {ADD($2c4, $2c8)}, c:$2cd {ADD($2c5, $2ca)}>
N002 [000030] LCL_VAR V01 loc0 u:1 (last use) => <l:$286 {$2d0, int <- long}, c:$287 {$2d1, int <- long}>
N003 [000032] CNS_INT 0x3B9ACA00 => $47 {IntCns 0x3B9ACA00}
N004 [000033] MUL => <l:$288 {MUL($47, $286)}, c:$289 {MUL($47, $287)}>
N005 [000034] CAST => <l:$2d4 {$288, long <- ulong <- uint}, c:$2d5 {$289, long <- ulong <- uint}>
N006 [000035] SUB => <l:$2d6 {SUB($2cc, $2d4)}, c:$2d7 {SUB($2cd, $2d5)}>
N007 [000036] CNS_INT 32 => $44 {IntCns 32}
N008 [000037] LSH => <l:$2d8 {LSH($2d6, $44)}, c:$2d9 {LSH($2d7, $44)}>
N009 [000038] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)}
N010 [000069] CNS_INT 8 => $105 {LngCns 8}
N011 [000070] ADD => $142 {ADD($80, $105)}
N012 [000040] IND => <l:$182 {ByrefExposedLoad($42, $142, $c2)}, c:$1c2 {MemOpaque:NotInLoop}>
N013 [000041] CAST => <l:$2da {$182, long <- ulong <- uint}, c:$2db {$1c2, long <- ulong <- uint}>
N014 [000042] ADD => <l:$2dc {ADD($2d8, $2da)}, c:$2dd {ADD($2d9, $2db)}>
Tree [000043] assigned VN to local var V05/1: <l:$2dc {ADD($2d8, $2da)}, c:$2dd {ADD($2d9, $2db)}>
N015 [000043] STORE_LCL_VAR V05 tmp2 d:1 => $VN.Void
***** BB01, STMT00004(after)
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 $VN.Void
N014 ( 17, 21) [000042] ----G+----- \--* ADD long <l:$2dc, c:$2dd>
N008 ( 11, 14) [000037] -----+----- +--* LSH long <l:$2d8, c:$2d9>
N006 ( 9, 12) [000035] -----+----- | +--* SUB long <l:$2d6, c:$2d7>
N001 ( 1, 1) [000012] -----+----- | | +--* LCL_VAR long V04 tmp1 u:1 (last use) <l:$2cc, c:$2cd>
N005 ( 7, 10) [000034] -----+---U- | | \--* CAST long <- ulong <- uint <l:$2d4, c:$2d5>
N004 ( 6, 8) [000033] -----+----- | | \--* MUL int <l:$288, c:$289>
N002 ( 1, 1) [000030] -----+----- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$286, c:$287>
N003 ( 1, 4) [000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00 $47
N007 ( 1, 1) [000036] -----+----- | \--* CNS_INT int 32 $44
N013 ( 5, 6) [000041] ----G+---U- \--* CAST long <- ulong <- uint <l:$2da, c:$2db>
N012 ( 4, 4) [000040] n---G+----- \--* IND int <l:$182, c:$1c2>
N011 ( 2, 2) [000070] -----+-N--- \--* ADD byref $142
N009 ( 1, 1) [000038] -----+----- +--* LCL_VAR byref V00 arg0 u:1 $80
N010 ( 1, 1) [000069] -----+----- \--* CNS_INT long 8 $105
---------
***** BB01, STMT00005(before)
N005 ( 23, 10) [000050] DA---+----- * STORE_LCL_VAR int V02 loc1 d:1
N004 ( 23, 10) [000049] -----+----- \--* CAST int <- uint <- long
N003 ( 22, 8) [000048] -----+----- \--* UDIV long
N001 ( 1, 1) [000045] -----+----- +--* LCL_VAR long V05 tmp2 u:1
N002 ( 1, 4) [000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00
N001 [000045] LCL_VAR V05 tmp2 u:1 => <l:$2dc {ADD($2d8, $2da)}, c:$2dd {ADD($2d9, $2db)}>
N002 [000047] CNS_INT 0x3B9ACA00 => $103 {LngCns 0x3B9ACA00}
N003 [000048] UDIV => <l:$2de {UDIV($2dc, $103)}, c:$2df {UDIV($2dd, $103)}>
N004 [000049] CAST => <l:$28a {$2de, int <- uint <- long}, c:$28b {$2df, int <- uint <- long}>
Tree [000050] assigned VN to local var V02/1: <l:$28a {$2de, int <- uint <- long}, c:$28b {$2df, int <- uint <- long}>
N005 [000050] STORE_LCL_VAR V02 loc1 d:1 => $VN.Void
***** BB01, STMT00005(after)
N005 ( 23, 10) [000050] DA---+----- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
N004 ( 23, 10) [000049] -----+----- \--* CAST int <- uint <- long <l:$28a, c:$28b>
N003 ( 22, 8) [000048] -----+----- \--* UDIV long <l:$2de, c:$2df>
N001 ( 1, 1) [000045] -----+----- +--* LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00 $103
---------
***** BB01, STMT00006(before)
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int
N003 ( 2, 2) [000072] -----+-N--- +--* ADD byref
N001 ( 1, 1) [000051] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 (last use)
N002 ( 1, 1) [000071] -----+----- | \--* CNS_INT long 8
N004 ( 1, 1) [000052] -----+----- \--* LCL_VAR int V02 loc1 u:1
N001 [000051] LCL_VAR V00 arg0 u:1 (last use) => $80 {InitVal($40)}
N002 [000071] CNS_INT 8 => $105 {LngCns 8}
N003 [000072] ADD => $142 {ADD($80, $105)}
N004 [000052] LCL_VAR V02 loc1 u:1 => <l:$28a {$2de, int <- uint <- long}, c:$28b {$2df, int <- uint <- long}>
fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000054] to VN: $c3.
N005 [000054] STOREIND => $VN.Void
***** BB01, STMT00006(after)
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int $VN.Void
N003 ( 2, 2) [000072] -----+-N--- +--* ADD byref $142
N001 ( 1, 1) [000051] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $80
N002 ( 1, 1) [000071] -----+----- | \--* CNS_INT long 8 $105
N004 ( 1, 1) [000052] -----+----- \--* LCL_VAR int V02 loc1 u:1 <l:$28a, c:$28b>
---------
***** BB01, STMT00007(before)
N006 ( 9, 11) [000060] -----+----- * RETURN int
N005 ( 8, 10) [000059] -----+----- \--* SUB int
N001 ( 1, 1) [000044] -----+----- +--* LCL_VAR int V05 tmp2 u:1 (last use)
N004 ( 6, 8) [000058] -----+----- \--* MUL int
N002 ( 1, 1) [000056] -----+----- +--* LCL_VAR int V02 loc1 u:1 (last use)
N003 ( 1, 4) [000057] -----+----- \--* CNS_INT int 0x3B9ACA00
N001 [000044] LCL_VAR V05 tmp2 u:1 (last use) => <l:$28c {$2dc, int <- long}, c:$28d {$2dd, int <- long}>
N002 [000056] LCL_VAR V02 loc1 u:1 (last use) => <l:$28a {$2de, int <- uint <- long}, c:$28b {$2df, int <- uint <- long}>
N003 [000057] CNS_INT 0x3B9ACA00 => $47 {IntCns 0x3B9ACA00}
N004 [000058] MUL => <l:$28e {MUL($47, $28a)}, c:$28f {MUL($47, $28b)}>
N005 [000059] SUB => <l:$290 {SUB($28c, $28e)}, c:$291 {SUB($28d, $28f)}>
N006 [000060] RETURN => $VN.Void
***** BB01, STMT00007(after)
N006 ( 9, 11) [000060] -----+----- * RETURN int $VN.Void
N005 ( 8, 10) [000059] -----+----- \--* SUB int <l:$290, c:$291>
N001 ( 1, 1) [000044] -----+----- +--* LCL_VAR int V05 tmp2 u:1 (last use) <l:$28c, c:$28d>
N004 ( 6, 8) [000058] -----+----- \--* MUL int <l:$28e, c:$28f>
N002 ( 1, 1) [000056] -----+----- +--* LCL_VAR int V02 loc1 u:1 (last use) <l:$28a, c:$28b>
N003 ( 1, 4) [000057] -----+----- \--* CNS_INT int 0x3B9ACA00 $47
*************** Finishing PHASE Do value numbering
Trees after Do value numbering
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
N014 ( 13, 15) [000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
N013 ( 13, 15) [000010] ---XG+----- \--* ADD long <l:$2cf, c:$2ce>
N007 ( 7, 8) [000005] ---XG+----- +--* LSH long <l:$2c7, c:$2c6>
N005 ( 5, 6) [000003] ---XG+---U- | +--* CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N004 ( 4, 4) [000002] ---XG+----- | | \--* IND int <l:$281, c:$280>
N003 ( 2, 2) [000062] -----+-N--- | | \--* ADD byref $140
N001 ( 1, 1) [000000] -----+----- | | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000061] -----+----- | | \--* CNS_INT long 4 $100
N006 ( 1, 1) [000004] -----+----- | \--* CNS_INT int 32 $44
N012 ( 5, 6) [000009] ---XG+---U- \--* CAST long <- ulong <- uint <l:$2c9, c:$2cb>
N011 ( 4, 4) [000008] ---XG+----- \--* IND int <l:$283, c:$282>
N010 ( 2, 2) [000064] -----+-N--- \--* ADD byref $141
N008 ( 1, 1) [000006] -----+----- +--* LCL_VAR byref V00 arg0 u:1 $80
N009 ( 1, 1) [000063] -----+----- \--* CNS_INT long 12 $102
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
N004 ( 22, 8) [000017] DA---+----- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
N003 ( 22, 8) [000016] -----+----- \--* UDIV long <l:$2d0, c:$2d1>
N001 ( 1, 1) [000013] -----+----- +--* LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00 $103
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
N008 ( 9, 10) [000024] nA--G+--R-- * STOREIND int $VN.Void
N007 ( 2, 2) [000066] -----+-N--- +--* ADD byref $140
N005 ( 1, 1) [000018] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 $80
N006 ( 1, 1) [000065] -----+----- | \--* CNS_INT long 4 $100
N004 ( 4, 5) [000022] -----+----- \--* CAST int <- uint <- long <l:$284, c:$285>
N003 ( 3, 3) [000021] -----+----- \--* RSZ long <l:$2d2, c:$2d3>
N001 ( 1, 1) [000019] -----+----- +--* LCL_VAR long V01 loc0 u:1 <l:$2d0, c:$2d1>
N002 ( 1, 1) [000020] -----+----- \--* CNS_INT int 32 $44
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int $VN.Void
N003 ( 2, 2) [000068] -----+-N--- +--* ADD byref $141
N001 ( 1, 1) [000025] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000067] -----+----- | \--* CNS_INT long 12 $102
N004 ( 1, 1) [000026] -----+----- \--* LCL_VAR int V01 loc0 u:1 <l:$286, c:$287>
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 $VN.Void
N014 ( 17, 21) [000042] ----G+----- \--* ADD long <l:$2dc, c:$2dd>
N008 ( 11, 14) [000037] -----+----- +--* LSH long <l:$2d8, c:$2d9>
N006 ( 9, 12) [000035] -----+----- | +--* SUB long <l:$2d6, c:$2d7>
N001 ( 1, 1) [000012] -----+----- | | +--* LCL_VAR long V04 tmp1 u:1 (last use) <l:$2cc, c:$2cd>
N005 ( 7, 10) [000034] -----+---U- | | \--* CAST long <- ulong <- uint <l:$2d4, c:$2d5>
N004 ( 6, 8) [000033] -----+----- | | \--* MUL int <l:$288, c:$289>
N002 ( 1, 1) [000030] -----+----- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$286, c:$287>
N003 ( 1, 4) [000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00 $47
N007 ( 1, 1) [000036] -----+----- | \--* CNS_INT int 32 $44
N013 ( 5, 6) [000041] ----G+---U- \--* CAST long <- ulong <- uint <l:$2da, c:$2db>
N012 ( 4, 4) [000040] n---G+----- \--* IND int <l:$182, c:$1c2>
N011 ( 2, 2) [000070] -----+-N--- \--* ADD byref $142
N009 ( 1, 1) [000038] -----+----- +--* LCL_VAR byref V00 arg0 u:1 $80
N010 ( 1, 1) [000069] -----+----- \--* CNS_INT long 8 $105
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
N005 ( 23, 10) [000050] DA---+----- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
N004 ( 23, 10) [000049] -----+----- \--* CAST int <- uint <- long <l:$28a, c:$28b>
N003 ( 22, 8) [000048] -----+----- \--* UDIV long <l:$2de, c:$2df>
N001 ( 1, 1) [000045] -----+----- +--* LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00 $103
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int $VN.Void
N003 ( 2, 2) [000072] -----+-N--- +--* ADD byref $142
N001 ( 1, 1) [000051] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $80
N002 ( 1, 1) [000071] -----+----- | \--* CNS_INT long 8 $105
N004 ( 1, 1) [000052] -----+----- \--* LCL_VAR int V02 loc1 u:1 <l:$28a, c:$28b>
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
N006 ( 9, 11) [000060] -----+----- * RETURN int $VN.Void
N005 ( 8, 10) [000059] -----+----- \--* SUB int <l:$290, c:$291>
N001 ( 1, 1) [000044] -----+----- +--* LCL_VAR int V05 tmp2 u:1 (last use) <l:$28c, c:$28d>
N004 ( 6, 8) [000058] -----+----- \--* MUL int <l:$28e, c:$28f>
N002 ( 1, 1) [000056] -----+----- +--* LCL_VAR int V02 loc1 u:1 (last use) <l:$28a, c:$28b>
N003 ( 1, 4) [000057] -----+----- \--* CNS_INT int 0x3B9ACA00 $47
SSA MEM: ByrefExposed, GcHeap = m:2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
SSA checks completed successfully
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Hoist loop code
No loops; no hoisting
*************** Finishing PHASE Hoist loop code [no changes]
*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
curSsaName stack: { }
Live vars after [000011]: {V00} +{V04} => {V00 V04}
orig [000013] copy [000000] VNs proved equivalent
Live vars after [000017]: {V00 V04} +{V01} => {V00 V01 V04}
orig [000019] copy [000000] VNs proved equivalent
orig [000019] copy [000011] VNs proved equivalent
orig [000018] copy [000017] VNs proved equivalent
orig [000018] copy [000011] VNs proved equivalent
orig [000025] copy [000017] VNs proved equivalent
orig [000025] copy [000011] VNs proved equivalent
orig [000026] copy [000000] VNs proved equivalent
orig [000026] copy [000011] VNs proved equivalent
Live vars after [000012]: {V00 V01 V04} -{V04} => {V00 V01}
orig [000012] copy [000000] VNs proved equivalent
orig [000012] copy [000017] VNs proved equivalent
Live vars after [000030]: {V00 V01} -{V01} => {V00}
orig [000030] copy [000000] VNs proved equivalent
orig [000030] copy [000011] VNs proved equivalent
orig [000038] copy [000017] VNs proved equivalent
orig [000038] copy [000011] VNs proved equivalent
Live vars after [000043]: {V00} +{V05} => {V00 V05}
orig [000045] copy [000000] VNs proved equivalent
orig [000045] copy [000017] VNs proved equivalent
orig [000045] copy [000011] VNs proved equivalent
Live vars after [000050]: {V00 V05} +{V02} => {V00 V02 V05}
Live vars after [000051]: {V00 V02 V05} -{V00} => {V02 V05}
orig [000051] copy [000017] VNs proved equivalent
orig [000051] copy [000050] VNs proved equivalent
orig [000051] copy [000011] VNs proved equivalent
orig [000051] copy [000043] VNs proved equivalent
orig [000052] copy [000000] VNs proved equivalent
orig [000052] copy [000017] VNs proved equivalent
orig [000052] copy [000011] VNs proved equivalent
orig [000052] copy [000043] VNs proved equivalent
Live vars after [000044]: {V02 V05} -{V05} => {V02}
orig [000044] copy [000000] VNs proved equivalent
orig [000044] copy [000017] VNs proved equivalent
orig [000044] copy [000050] VNs proved equivalent
orig [000044] copy [000011] VNs proved equivalent
Live vars after [000056]: {V02} -{V02} => {}
orig [000056] copy [000000] VNs proved equivalent
orig [000056] copy [000017] VNs proved equivalent
orig [000056] copy [000011] VNs proved equivalent
orig [000056] copy [000043] VNs proved equivalent
*************** Finishing PHASE VN based copy prop [no changes]
*************** Starting PHASE Redundant branch opts
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Redundant branch opts [no changes]
*************** Starting PHASE Optimize Valnum CSEs
CONST CSE is disabled
Standard CSE Heuristic
Standard CSE Heuristic
*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
N014 ( 13, 15) [000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
N013 ( 13, 15) [000010] ---XG+----- \--* ADD long <l:$2cf, c:$2ce>
N007 ( 7, 8) [000005] ---XG+----- +--* LSH long <l:$2c7, c:$2c6>
N005 ( 5, 6) [000003] ---XG+---U- | +--* CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N004 ( 4, 4) [000002] ---XG+----- | | \--* IND int <l:$281, c:$280>
N003 ( 2, 2) [000062] -----+-N--- | | \--* ADD byref $140
N001 ( 1, 1) [000000] -----+----- | | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000061] -----+----- | | \--* CNS_INT long 4 $100
N006 ( 1, 1) [000004] -----+----- | \--* CNS_INT int 32 $44
N012 ( 5, 6) [000009] ---XG+---U- \--* CAST long <- ulong <- uint <l:$2c9, c:$2cb>
N011 ( 4, 4) [000008] ---XG+----- \--* IND int <l:$283, c:$282>
N010 ( 2, 2) [000064] -----+-N--- \--* ADD byref $141
N008 ( 1, 1) [000006] -----+----- +--* LCL_VAR byref V00 arg0 u:1 $80
N009 ( 1, 1) [000063] -----+----- \--* CNS_INT long 12 $102
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
N004 ( 22, 8) [000017] DA---+----- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
N003 ( 22, 8) [000016] -----+----- \--* UDIV long <l:$2d0, c:$2d1>
N001 ( 1, 1) [000013] -----+----- +--* LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00 $103
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
N008 ( 9, 10) [000024] nA--G+--R-- * STOREIND int $VN.Void
N007 ( 2, 2) [000066] -----+-N--- +--* ADD byref $140
N005 ( 1, 1) [000018] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 $80
N006 ( 1, 1) [000065] -----+----- | \--* CNS_INT long 4 $100
N004 ( 4, 5) [000022] -----+----- \--* CAST int <- uint <- long <l:$284, c:$285>
N003 ( 3, 3) [000021] -----+----- \--* RSZ long <l:$2d2, c:$2d3>
N001 ( 1, 1) [000019] -----+----- +--* LCL_VAR long V01 loc0 u:1 <l:$2d0, c:$2d1>
N002 ( 1, 1) [000020] -----+----- \--* CNS_INT int 32 $44
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int $VN.Void
N003 ( 2, 2) [000068] -----+-N--- +--* ADD byref $141
N001 ( 1, 1) [000025] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000067] -----+----- | \--* CNS_INT long 12 $102
N004 ( 1, 1) [000026] -----+----- \--* LCL_VAR int V01 loc0 u:1 <l:$286, c:$287>
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 $VN.Void
N014 ( 17, 21) [000042] ----G+----- \--* ADD long <l:$2dc, c:$2dd>
N008 ( 11, 14) [000037] -----+----- +--* LSH long <l:$2d8, c:$2d9>
N006 ( 9, 12) [000035] -----+----- | +--* SUB long <l:$2d6, c:$2d7>
N001 ( 1, 1) [000012] -----+----- | | +--* LCL_VAR long V04 tmp1 u:1 (last use) <l:$2cc, c:$2cd>
N005 ( 7, 10) [000034] -----+---U- | | \--* CAST long <- ulong <- uint <l:$2d4, c:$2d5>
N004 ( 6, 8) [000033] -----+----- | | \--* MUL int <l:$288, c:$289>
N002 ( 1, 1) [000030] -----+----- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$286, c:$287>
N003 ( 1, 4) [000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00 $47
N007 ( 1, 1) [000036] -----+----- | \--* CNS_INT int 32 $44
N013 ( 5, 6) [000041] ----G+---U- \--* CAST long <- ulong <- uint <l:$2da, c:$2db>
N012 ( 4, 4) [000040] n---G+----- \--* IND int <l:$182, c:$1c2>
N011 ( 2, 2) [000070] -----+-N--- \--* ADD byref $142
N009 ( 1, 1) [000038] -----+----- +--* LCL_VAR byref V00 arg0 u:1 $80
N010 ( 1, 1) [000069] -----+----- \--* CNS_INT long 8 $105
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
N005 ( 23, 10) [000050] DA---+----- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
N004 ( 23, 10) [000049] -----+----- \--* CAST int <- uint <- long <l:$28a, c:$28b>
N003 ( 22, 8) [000048] -----+----- \--* UDIV long <l:$2de, c:$2df>
N001 ( 1, 1) [000045] -----+----- +--* LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00 $103
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int $VN.Void
N003 ( 2, 2) [000072] -----+-N--- +--* ADD byref $142
N001 ( 1, 1) [000051] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $80
N002 ( 1, 1) [000071] -----+----- | \--* CNS_INT long 8 $105
N004 ( 1, 1) [000052] -----+----- \--* LCL_VAR int V02 loc1 u:1 <l:$28a, c:$28b>
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
N006 ( 9, 11) [000060] -----+----- * RETURN int $VN.Void
N005 ( 8, 10) [000059] -----+----- \--* SUB int <l:$290, c:$291>
N001 ( 1, 1) [000044] -----+----- +--* LCL_VAR int V05 tmp2 u:1 (last use) <l:$28c, c:$28d>
N004 ( 6, 8) [000058] -----+----- \--* MUL int <l:$28e, c:$28f>
N002 ( 1, 1) [000056] -----+----- +--* LCL_VAR int V02 loc1 u:1 (last use) <l:$28a, c:$28b>
N003 ( 1, 4) [000057] -----+----- \--* CNS_INT int 0x3B9ACA00 $47
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Assertion prop
GenTreeNode creates assertion:
N004 ( 4, 4) [000002] ---XG+----- * IND int <l:$281, c:$280>
In BB01 New Global Constant Assertion: ($80,$0) LCLVAR {InitVal($40)} != 0, index = #01
BB01 valueGen = #01
BB01:
in = #NA
out = #01
Propagating #NA for BB01, stmt STMT00000, tree [000000], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000061], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000062], tree -> #NA
Propagating #NA for BB01, stmt STMT00000, tree [000002], tree -> #01
Propagating #01 for BB01, stmt STMT00000, tree [000003], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000004], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000005], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000006], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000063], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000064], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000008], tree -> #01
Non-null assertion prop for indirection [000008] in BB01:
Propagating #01 for BB01, stmt STMT00000, tree [000009], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000010], tree -> #NA
Propagating #01 for BB01, stmt STMT00000, tree [000011], tree -> #NA
Re-morphing this stmt:
STMT00000 ( 0x000[E-] ... 0x01A )
N014 ( 13, 15) [000011] DA-XG+----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
N013 ( 13, 15) [000010] ---XG+----- \--* ADD long <l:$2cf, c:$2ce>
N007 ( 7, 8) [000005] ---XG+----- +--* LSH long <l:$2c7, c:$2c6>
N005 ( 5, 6) [000003] ---XG+---U- | +--* CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N004 ( 4, 4) [000002] ---XG+----- | | \--* IND int <l:$281, c:$280>
N003 ( 2, 2) [000062] -----+-N--- | | \--* ADD byref $140
N001 ( 1, 1) [000000] -----+----- | | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000061] -----+----- | | \--* CNS_INT long 4 $100
N006 ( 1, 1) [000004] -----+----- | \--* CNS_INT int 32 $44
N012 ( 5, 6) [000009] ---XG+---U- \--* CAST long <- ulong <- uint <l:$2c9, c:$2cb>
N011 ( 4, 4) [000008] n---G+----- \--* IND int <l:$283, c:$282>
N010 ( 2, 2) [000064] -----+-N--- \--* ADD byref $141
N008 ( 1, 1) [000006] -----+----- +--* LCL_VAR byref V00 arg0 u:1 $80
N009 ( 1, 1) [000063] -----+----- \--* CNS_INT long 12 $102
optAssertionPropMain morphed tree:
N014 ( 13, 15) [000011] DA-XGO----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
N013 ( 13, 15) [000010] ---XGO----- \--* ADD long <l:$2cf, c:$2ce>
N007 ( 7, 8) [000005] ---XG------ +--* LSH long <l:$2c7, c:$2c6>
N005 ( 5, 6) [000003] ---XG----U- | +--* CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N004 ( 4, 4) [000002] ---XG------ | | \--* IND int <l:$281, c:$280>
N003 ( 2, 2) [000062] -------N--- | | \--* ADD byref $140
N001 ( 1, 1) [000000] ----------- | | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000061] ----------- | | \--* CNS_INT long 4 $100
N006 ( 1, 1) [000004] ----------- | \--* CNS_INT int 32 $44
N012 ( 5, 6) [000009] ----GO---U- \--* CAST long <- ulong <- uint <l:$2c9, c:$2cb>
N011 ( 4, 4) [000008] n---GO----- \--* IND int <l:$283, c:$282>
N010 ( 2, 2) [000064] -------N--- \--* ADD byref $141
N008 ( 1, 1) [000006] ----------- +--* LCL_VAR byref V00 arg0 u:1 $80
N009 ( 1, 1) [000063] ----------- \--* CNS_INT long 12 $102
Propagating #01 for BB01, stmt STMT00001, tree [000013], tree -> #NA
Propagating #01 for BB01, stmt STMT00001, tree [000015], tree -> #NA
Propagating #01 for BB01, stmt STMT00001, tree [000016], tree -> #NA
Divisor for DIV/MOD is proven to be never negative...
DIV/MOD is proven to never overflow...
Propagating #01 for BB01, stmt STMT00001, tree [000017], tree -> #NA
Re-morphing this stmt:
STMT00001 ( ??? ... ??? )
N004 ( 22, 8) [000017] DA---+----- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
N003 ( 22, 8) [000016] -----+----- \--* UDIV long <l:$2d0, c:$2d1>
N001 ( 1, 1) [000013] -----+----- +--* LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -----+-N--- \--* CNS_INT long 0x3B9ACA00 $103
optAssertionPropMain morphed tree:
N004 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
N003 ( 22, 8) [000016] ----------- \--* UDIV long <l:$2d0, c:$2d1>
N001 ( 1, 1) [000013] ----------- +--* LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -------N--- \--* CNS_INT long 0x3B9ACA00 $103
Propagating #01 for BB01, stmt STMT00002, tree [000019], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000020], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000021], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000022], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000018], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000065], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000066], tree -> #NA
Propagating #01 for BB01, stmt STMT00002, tree [000024], tree -> #NA
Propagating #01 for BB01, stmt STMT00003, tree [000025], tree -> #NA
Propagating #01 for BB01, stmt STMT00003, tree [000067], tree -> #NA
Propagating #01 for BB01, stmt STMT00003, tree [000068], tree -> #NA
Propagating #01 for BB01, stmt STMT00003, tree [000026], tree -> #NA
Propagating #01 for BB01, stmt STMT00003, tree [000029], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000012], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000030], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000032], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000033], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000034], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000035], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000036], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000037], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000038], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000069], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000070], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000040], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000041], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000042], tree -> #NA
Propagating #01 for BB01, stmt STMT00004, tree [000043], tree -> #NA
Propagating #01 for BB01, stmt STMT00005, tree [000045], tree -> #NA
Propagating #01 for BB01, stmt STMT00005, tree [000047], tree -> #NA
Propagating #01 for BB01, stmt STMT00005, tree [000048], tree -> #NA
Divisor for DIV/MOD is proven to be never negative...
DIV/MOD is proven to never overflow...
Propagating #01 for BB01, stmt STMT00005, tree [000049], tree -> #NA
Propagating #01 for BB01, stmt STMT00005, tree [000050], tree -> #NA
Re-morphing this stmt:
STMT00005 ( ??? ... ??? )
N005 ( 23, 10) [000050] DA---+----- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
N004 ( 23, 10) [000049] -----+----- \--* CAST int <- uint <- long <l:$28a, c:$28b>
N003 ( 22, 8) [000048] -----+----- \--* UDIV long <l:$2de, c:$2df>
N001 ( 1, 1) [000045] -----+----- +--* LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -----+-N--- \--* CNS_INT long 0x3B9ACA00 $103
optAssertionPropMain morphed tree:
N005 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
N004 ( 23, 10) [000049] ----------- \--* CAST int <- uint <- long <l:$28a, c:$28b>
N003 ( 22, 8) [000048] ----------- \--* UDIV long <l:$2de, c:$2df>
N001 ( 1, 1) [000045] ----------- +--* LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -------N--- \--* CNS_INT long 0x3B9ACA00 $103
Propagating #01 for BB01, stmt STMT00006, tree [000051], tree -> #NA
Propagating #01 for BB01, stmt STMT00006, tree [000071], tree -> #NA
Propagating #01 for BB01, stmt STMT00006, tree [000072], tree -> #NA
Propagating #01 for BB01, stmt STMT00006, tree [000052], tree -> #NA
Propagating #01 for BB01, stmt STMT00006, tree [000054], tree -> #NA
Propagating #01 for BB01, stmt STMT00007, tree [000044], tree -> #NA
Propagating #01 for BB01, stmt STMT00007, tree [000056], tree -> #NA
Propagating #01 for BB01, stmt STMT00007, tree [000057], tree -> #NA
Propagating #01 for BB01, stmt STMT00007, tree [000058], tree -> #NA
Propagating #01 for BB01, stmt STMT00007, tree [000059], tree -> #NA
Propagating #01 for BB01, stmt STMT00007, tree [000060], tree -> #NA
*************** Finishing PHASE Assertion prop
Trees after Assertion prop
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x01A )
N014 ( 13, 15) [000011] DA-XGO----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
N013 ( 13, 15) [000010] ---XGO----- \--* ADD long <l:$2cf, c:$2ce>
N007 ( 7, 8) [000005] ---XG------ +--* LSH long <l:$2c7, c:$2c6>
N005 ( 5, 6) [000003] ---XG----U- | +--* CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N004 ( 4, 4) [000002] ---XG------ | | \--* IND int <l:$281, c:$280>
N003 ( 2, 2) [000062] -------N--- | | \--* ADD byref $140
N001 ( 1, 1) [000000] ----------- | | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000061] ----------- | | \--* CNS_INT long 4 $100
N006 ( 1, 1) [000004] ----------- | \--* CNS_INT int 32 $44
N012 ( 5, 6) [000009] ----GO---U- \--* CAST long <- ulong <- uint <l:$2c9, c:$2cb>
N011 ( 4, 4) [000008] n---GO----- \--* IND int <l:$283, c:$282>
N010 ( 2, 2) [000064] -------N--- \--* ADD byref $141
N008 ( 1, 1) [000006] ----------- +--* LCL_VAR byref V00 arg0 u:1 $80
N009 ( 1, 1) [000063] ----------- \--* CNS_INT long 12 $102
***** BB01 [0000]
STMT00001 ( ??? ... ??? )
N004 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
N003 ( 22, 8) [000016] ----------- \--* UDIV long <l:$2d0, c:$2d1>
N001 ( 1, 1) [000013] ----------- +--* LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -------N--- \--* CNS_INT long 0x3B9ACA00 $103
***** BB01 [0000]
STMT00002 ( ??? ... 0x021 )
N008 ( 9, 10) [000024] nA--G+--R-- * STOREIND int $VN.Void
N007 ( 2, 2) [000066] -----+-N--- +--* ADD byref $140
N005 ( 1, 1) [000018] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 $80
N006 ( 1, 1) [000065] -----+----- | \--* CNS_INT long 4 $100
N004 ( 4, 5) [000022] -----+----- \--* CAST int <- uint <- long <l:$284, c:$285>
N003 ( 3, 3) [000021] -----+----- \--* RSZ long <l:$2d2, c:$2d3>
N001 ( 1, 1) [000019] -----+----- +--* LCL_VAR long V01 loc0 u:1 <l:$2d0, c:$2d1>
N002 ( 1, 1) [000020] -----+----- \--* CNS_INT int 32 $44
***** BB01 [0000]
STMT00003 ( ??? ... 0x029 )
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int $VN.Void
N003 ( 2, 2) [000068] -----+-N--- +--* ADD byref $141
N001 ( 1, 1) [000025] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000067] -----+----- | \--* CNS_INT long 12 $102
N004 ( 1, 1) [000026] -----+----- \--* LCL_VAR int V01 loc0 u:1 <l:$286, c:$287>
***** BB01 [0000]
STMT00004 ( ??? ... 0x04C )
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 $VN.Void
N014 ( 17, 21) [000042] ----G+----- \--* ADD long <l:$2dc, c:$2dd>
N008 ( 11, 14) [000037] -----+----- +--* LSH long <l:$2d8, c:$2d9>
N006 ( 9, 12) [000035] -----+----- | +--* SUB long <l:$2d6, c:$2d7>
N001 ( 1, 1) [000012] -----+----- | | +--* LCL_VAR long V04 tmp1 u:1 (last use) <l:$2cc, c:$2cd>
N005 ( 7, 10) [000034] -----+---U- | | \--* CAST long <- ulong <- uint <l:$2d4, c:$2d5>
N004 ( 6, 8) [000033] -----+----- | | \--* MUL int <l:$288, c:$289>
N002 ( 1, 1) [000030] -----+----- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$286, c:$287>
N003 ( 1, 4) [000032] -----+----- | | \--* CNS_INT int 0x3B9ACA00 $47
N007 ( 1, 1) [000036] -----+----- | \--* CNS_INT int 32 $44
N013 ( 5, 6) [000041] ----G+---U- \--* CAST long <- ulong <- uint <l:$2da, c:$2db>
N012 ( 4, 4) [000040] n---G+----- \--* IND int <l:$182, c:$1c2>
N011 ( 2, 2) [000070] -----+-N--- \--* ADD byref $142
N009 ( 1, 1) [000038] -----+----- +--* LCL_VAR byref V00 arg0 u:1 $80
N010 ( 1, 1) [000069] -----+----- \--* CNS_INT long 8 $105
***** BB01 [0000]
STMT00005 ( ??? ... ??? )
N005 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
N004 ( 23, 10) [000049] ----------- \--* CAST int <- uint <- long <l:$28a, c:$28b>
N003 ( 22, 8) [000048] ----------- \--* UDIV long <l:$2de, c:$2df>
N001 ( 1, 1) [000045] ----------- +--* LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -------N--- \--* CNS_INT long 0x3B9ACA00 $103
***** BB01 [0000]
STMT00006 ( ??? ... 0x04F )
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int $VN.Void
N003 ( 2, 2) [000072] -----+-N--- +--* ADD byref $142
N001 ( 1, 1) [000051] -----+----- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $80
N002 ( 1, 1) [000071] -----+----- | \--* CNS_INT long 8 $105
N004 ( 1, 1) [000052] -----+----- \--* LCL_VAR int V02 loc1 u:1 <l:$28a, c:$28b>
***** BB01 [0000]
STMT00007 ( ??? ... 0x05D )
N006 ( 9, 11) [000060] -----+----- * RETURN int $VN.Void
N005 ( 8, 10) [000059] -----+----- \--* SUB int <l:$290, c:$291>
N001 ( 1, 1) [000044] -----+----- +--* LCL_VAR int V05 tmp2 u:1 (last use) <l:$28c, c:$28d>
N004 ( 6, 8) [000058] -----+----- \--* MUL int <l:$28e, c:$28f>
N002 ( 1, 1) [000056] -----+----- +--* LCL_VAR int V02 loc1 u:1 (last use) <l:$28a, c:$28b>
N003 ( 1, 4) [000057] -----+----- \--* CNS_INT int 0x3B9ACA00 $47
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Optimize index checks
*************** Finishing PHASE Optimize index checks [no changes]
*************** Starting PHASE Optimize Induction Variables
*************** In optInductionVariables()
Skipping since this method has no natural loops
*************** Finishing PHASE Optimize Induction Variables [no changes]
*************** Starting PHASE VN-based dead store removal
*************** Finishing PHASE VN-based dead store removal [no changes]
*************** Starting PHASE Clone blocks with range checks
Current method has no bounds checks
*************** Finishing PHASE Clone blocks with range checks [no changes]
*************** Starting PHASE VN based intrinsic expansion
*************** Finishing PHASE VN based intrinsic expansion [no changes]
Removing PHI functions
*************** Starting PHASE Stress gtSplitTree
*************** Finishing PHASE Stress gtSplitTree [no changes]
*************** Starting PHASE Remove empty finally 3
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 3 [no changes]
*************** Starting PHASE Remove empty try 3
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 3 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 3
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 3 [no changes]
*************** Starting PHASE Create EH funclets
*************** Finishing PHASE Create EH funclets [no changes]
*************** Starting PHASE Expand casts
*************** Finishing PHASE Expand casts [no changes]
*************** Starting PHASE Expand runtime lookups
*************** Finishing PHASE Expand runtime lookups [no changes]
*************** Starting PHASE Expand static init
Nothing to expand.
*************** Finishing PHASE Expand static init [no changes]
*************** Starting PHASE Expand TLS access
Nothing to expand.
*************** Finishing PHASE Expand TLS access [no changes]
*************** Starting PHASE Expand stack array allocation
*************** Finishing PHASE Expand stack array allocation [no changes]
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Create throw helper blocks
*************** Finishing PHASE Create throw helper blocks [no changes]
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
optimized 0 BBJ_COND cases in 1 passes
*************** Finishing PHASE Optimize bools [no changes]
*************** Starting PHASE If conversion
*************** Finishing PHASE If conversion [no changes]
*************** Starting PHASE Recognize Switch
*************** Finishing PHASE Recognize Switch [no changes]
*************** Starting PHASE Optimize pre-layout
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** Finishing PHASE Optimize pre-layout [no changes]
*************** Starting PHASE Repair profile pre-layout
No PGO data. Skipping profile repair.
*************** Finishing PHASE Repair profile pre-layout [no changes]
*************** Starting PHASE Rationalize IR
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
[000073] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000061] ----------- t61 = CNS_INT long 4 $100
/--* t0 byref
+--* t61 long
N003 ( 2, 2) [000062] -------N--- t62 = * ADD byref $140
/--* t62 byref
N004 ( 4, 4) [000002] ---XG------ t2 = * IND int <l:$281, c:$280>
/--* t2 int
N005 ( 5, 6) [000003] ---XG----U- t3 = * CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N006 ( 1, 1) [000004] ----------- t4 = CNS_INT int 32 $44
/--* t3 long
+--* t4 int
N007 ( 7, 8) [000005] ---XG------ t5 = * LSH long <l:$2c7, c:$2c6>
N008 ( 1, 1) [000006] ----------- t6 = LCL_VAR byref V00 arg0 u:1 $80
N009 ( 1, 1) [000063] ----------- t63 = CNS_INT long 12 $102
/--* t6 byref
+--* t63 long
N010 ( 2, 2) [000064] -------N--- t64 = * ADD byref $141
/--* t64 byref
N011 ( 4, 4) [000008] n---GO----- t8 = * IND int <l:$283, c:$282>
/--* t8 int
N012 ( 5, 6) [000009] ----GO---U- t9 = * CAST long <- ulong <- uint <l:$2c9, c:$2cb>
/--* t5 long
+--* t9 long
N013 ( 13, 15) [000010] ---XGO----- t10 = * ADD long <l:$2cf, c:$2ce>
/--* t10 long
N014 ( 13, 15) [000011] DA-XGO----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
N001 ( 1, 1) [000013] ----------- t13 = LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -------N--- t15 = CNS_INT long 0x3B9ACA00 $103
/--* t13 long
+--* t15 long
N003 ( 22, 8) [000016] ----------- t16 = * UDIV long <l:$2d0, c:$2d1>
/--* t16 long
N004 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
N001 ( 1, 1) [000019] -----+----- t19 = LCL_VAR long V01 loc0 u:1 <l:$2d0, c:$2d1>
N002 ( 1, 1) [000020] -----+----- t20 = CNS_INT int 32 $44
/--* t19 long
+--* t20 int
N003 ( 3, 3) [000021] -----+----- t21 = * RSZ long <l:$2d2, c:$2d3>
/--* t21 long
N004 ( 4, 5) [000022] -----+----- t22 = * CAST int <- uint <- long <l:$284, c:$285>
N005 ( 1, 1) [000018] -----+----- t18 = LCL_VAR byref V00 arg0 u:1 $80
N006 ( 1, 1) [000065] -----+----- t65 = CNS_INT long 4 $100
/--* t18 byref
+--* t65 long
N007 ( 2, 2) [000066] -----+-N--- t66 = * ADD byref $140
/--* t66 byref
+--* t22 int
N008 ( 9, 10) [000024] nA--G+----- * STOREIND int $VN.Void
N001 ( 1, 1) [000025] -----+----- t25 = LCL_VAR byref V00 arg0 u:1 $80
N002 ( 1, 1) [000067] -----+----- t67 = CNS_INT long 12 $102
/--* t25 byref
+--* t67 long
N003 ( 2, 2) [000068] -----+-N--- t68 = * ADD byref $141
N004 ( 1, 1) [000026] -----+----- t26 = LCL_VAR int V01 loc0 u:1 <l:$286, c:$287>
/--* t68 byref
+--* t26 int
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int $VN.Void
N001 ( 1, 1) [000012] -----+----- t12 = LCL_VAR long V04 tmp1 u:1 (last use) <l:$2cc, c:$2cd>
N002 ( 1, 1) [000030] -----+----- t30 = LCL_VAR int V01 loc0 u:1 (last use) <l:$286, c:$287>
N003 ( 1, 4) [000032] -----+----- t32 = CNS_INT int 0x3B9ACA00 $47
/--* t30 int
+--* t32 int
N004 ( 6, 8) [000033] -----+----- t33 = * MUL int <l:$288, c:$289>
/--* t33 int
N005 ( 7, 10) [000034] -----+---U- t34 = * CAST long <- ulong <- uint <l:$2d4, c:$2d5>
/--* t12 long
+--* t34 long
N006 ( 9, 12) [000035] -----+----- t35 = * SUB long <l:$2d6, c:$2d7>
N007 ( 1, 1) [000036] -----+----- t36 = CNS_INT int 32 $44
/--* t35 long
+--* t36 int
N008 ( 11, 14) [000037] -----+----- t37 = * LSH long <l:$2d8, c:$2d9>
N009 ( 1, 1) [000038] -----+----- t38 = LCL_VAR byref V00 arg0 u:1 $80
N010 ( 1, 1) [000069] -----+----- t69 = CNS_INT long 8 $105
/--* t38 byref
+--* t69 long
N011 ( 2, 2) [000070] -----+-N--- t70 = * ADD byref $142
/--* t70 byref
N012 ( 4, 4) [000040] n---G+----- t40 = * IND int <l:$182, c:$1c2>
/--* t40 int
N013 ( 5, 6) [000041] ----G+---U- t41 = * CAST long <- ulong <- uint <l:$2da, c:$2db>
/--* t37 long
+--* t41 long
N014 ( 17, 21) [000042] ----G+----- t42 = * ADD long <l:$2dc, c:$2dd>
/--* t42 long
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 $VN.Void
N001 ( 1, 1) [000045] ----------- t45 = LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -------N--- t47 = CNS_INT long 0x3B9ACA00 $103
/--* t45 long
+--* t47 long
N003 ( 22, 8) [000048] ----------- t48 = * UDIV long <l:$2de, c:$2df>
/--* t48 long
N004 ( 23, 10) [000049] ----------- t49 = * CAST int <- uint <- long <l:$28a, c:$28b>
/--* t49 int
N005 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
N001 ( 1, 1) [000051] -----+----- t51 = LCL_VAR byref V00 arg0 u:1 (last use) $80
N002 ( 1, 1) [000071] -----+----- t71 = CNS_INT long 8 $105
/--* t51 byref
+--* t71 long
N003 ( 2, 2) [000072] -----+-N--- t72 = * ADD byref $142
N004 ( 1, 1) [000052] -----+----- t52 = LCL_VAR int V02 loc1 u:1 <l:$28a, c:$28b>
/--* t72 byref
+--* t52 int
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int $VN.Void
N001 ( 1, 1) [000044] -----+----- t44 = LCL_VAR int V05 tmp2 u:1 (last use) <l:$28c, c:$28d>
N002 ( 1, 1) [000056] -----+----- t56 = LCL_VAR int V02 loc1 u:1 (last use) <l:$28a, c:$28b>
N003 ( 1, 4) [000057] -----+----- t57 = CNS_INT int 0x3B9ACA00 $47
/--* t56 int
+--* t57 int
N004 ( 6, 8) [000058] -----+----- t58 = * MUL int <l:$28e, c:$28f>
/--* t44 int
+--* t58 int
N005 ( 8, 10) [000059] -----+----- t59 = * SUB int <l:$290, c:$291>
/--* t59 int
N006 ( 9, 11) [000060] -----+----- * RETURN int $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Lowering nodeinfo
0 parameter register to local mappings
Addressing mode:
Base
N001 ( 1, 1) [000000] ----------- * LCL_VAR byref V00 arg0 u:1 $80
+ 4
Removing unused node:
N002 ( 1, 1) [000061] -c--------- * CNS_INT long 4 $100
New addressing mode node:
N003 ( 2, 2) [000062] ----------- * LEA(b+4) byref
Addressing mode:
Base
N008 ( 1, 1) [000006] ----------- * LCL_VAR byref V00 arg0 u:1 $80
+ 12
Removing unused node:
N009 ( 1, 1) [000063] -c--------- * CNS_INT long 12 $102
New addressing mode node:
N010 ( 2, 2) [000064] ----------- * LEA(b+12) byref
lowering store lcl var/field (before):
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V00 arg0 u:1 $80
/--* t0 byref
N003 ( 2, 2) [000062] -c--------- t62 = * LEA(b+4) byref
/--* t62 byref
N004 ( 4, 4) [000002] -c-XG------ t2 = * IND int <l:$281, c:$280>
/--* t2 int
N005 ( 5, 6) [000003] ---XG----U- t3 = * CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N006 ( 1, 1) [000004] -c--------- t4 = CNS_INT int 32 $44
/--* t3 long
+--* t4 int
N007 ( 7, 8) [000005] ---XG------ t5 = * LSH long <l:$2c7, c:$2c6>
N008 ( 1, 1) [000006] ----------- t6 = LCL_VAR byref V00 arg0 u:1 $80
/--* t6 byref
N010 ( 2, 2) [000064] -c--------- t64 = * LEA(b+12) byref
/--* t64 byref
N011 ( 4, 4) [000008] nc--GO----- t8 = * IND int <l:$283, c:$282>
/--* t8 int
N012 ( 5, 6) [000009] ----GO---U- t9 = * CAST long <- ulong <- uint <l:$2c9, c:$2cb>
/--* t5 long
+--* t9 long
N013 ( 13, 15) [000010] ---XGO----- t10 = * ADD long <l:$2cf, c:$2ce>
/--* t10 long
N014 ( 13, 15) [000011] DA-XGO----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
lowering store lcl var/field (after):
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V00 arg0 u:1 $80
/--* t0 byref
N003 ( 2, 2) [000062] -c--------- t62 = * LEA(b+4) byref
/--* t62 byref
N004 ( 4, 4) [000002] -c-XG------ t2 = * IND int <l:$281, c:$280>
/--* t2 int
N005 ( 5, 6) [000003] ---XG----U- t3 = * CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N006 ( 1, 1) [000004] -c--------- t4 = CNS_INT int 32 $44
/--* t3 long
+--* t4 int
N007 ( 7, 8) [000005] ---XG------ t5 = * LSH long <l:$2c7, c:$2c6>
N008 ( 1, 1) [000006] ----------- t6 = LCL_VAR byref V00 arg0 u:1 $80
/--* t6 byref
N010 ( 2, 2) [000064] -c--------- t64 = * LEA(b+12) byref
/--* t64 byref
N011 ( 4, 4) [000008] nc--GO----- t8 = * IND int <l:$283, c:$282>
/--* t8 int
N012 ( 5, 6) [000009] ----GO---U- t9 = * CAST long <- ulong <- uint <l:$2c9, c:$2cb>
/--* t5 long
+--* t9 long
N013 ( 13, 15) [000010] ---XGO----- t10 = * ADD long <l:$2cf, c:$2ce>
/--* t10 long
N014 ( 13, 15) [000011] DA-XGO----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
lowering store lcl var/field (before):
N001 ( 1, 1) [000013] ----------- t13 = LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -------N--- t15 = CNS_INT long 0x44b82fa09b5a53 $103
[000074] -c--------- t74 = CNS_INT int 9
/--* t13 long
+--* t74 int
[000075] ----------- t75 = * RSZ long REG rax
/--* t75 long
+--* t15 long
[000076] ---------U- t76 = * MULHI long
[000077] -c--------- t77 = CNS_INT int 11
/--* t76 long
+--* t77 int
N003 ( 22, 8) [000016] ----------- t16 = * RSZ long
/--* t16 long
N004 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000013] ----------- t13 = LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -------N--- t15 = CNS_INT long 0x44b82fa09b5a53 $103
[000074] -c--------- t74 = CNS_INT int 9
/--* t13 long
+--* t74 int
[000075] ----------- t75 = * RSZ long REG rax
/--* t75 long
+--* t15 long
[000076] ---------U- t76 = * MULHI long
[000077] -c--------- t77 = CNS_INT int 11
/--* t76 long
+--* t77 int
N003 ( 22, 8) [000016] ----------- t16 = * RSZ long
/--* t16 long
N004 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
Addressing mode:
Base
N005 ( 1, 1) [000018] -----+----- * LCL_VAR byref V00 arg0 u:1 $80
+ 4
Removing unused node:
N006 ( 1, 1) [000065] -c---+----- * CNS_INT long 4 $100
New addressing mode node:
N007 ( 2, 2) [000066] -----+----- * LEA(b+4) byref
Lower of StoreInd didn't mark the node as self contained for reason: oper is not supported
N001 ( 1, 1) [000019] -----+----- t19 = LCL_VAR long V01 loc0 u:1 <l:$2d0, c:$2d1>
N002 ( 1, 1) [000020] -c---+----- t20 = CNS_INT int 32 $44
/--* t19 long
+--* t20 int
N003 ( 3, 3) [000021] -----+----- t21 = * RSZ long <l:$2d2, c:$2d3>
/--* t21 long
N004 ( 4, 5) [000022] -----+----- t22 = * CAST int <- uint <- long <l:$284, c:$285>
N005 ( 1, 1) [000018] -----+----- t18 = LCL_VAR byref V00 arg0 u:1 $80
/--* t18 byref
N007 ( 2, 2) [000066] -----+----- t66 = * LEA(b+4) byref
/--* t66 byref
+--* t22 int
N008 ( 9, 10) [000024] nA--G+----- * STOREIND int $VN.Void
Addressing mode:
Base
N001 ( 1, 1) [000025] -----+----- * LCL_VAR byref V00 arg0 u:1 $80
+ 12
Removing unused node:
N002 ( 1, 1) [000067] -c---+----- * CNS_INT long 12 $102
New addressing mode node:
N003 ( 2, 2) [000068] -----+----- * LEA(b+12) byref
Lower of StoreInd didn't mark the node as self contained for reason: oper is not supported
N001 ( 1, 1) [000025] -----+----- t25 = LCL_VAR byref V00 arg0 u:1 $80
/--* t25 byref
N003 ( 2, 2) [000068] -----+----- t68 = * LEA(b+12) byref
N004 ( 1, 1) [000026] -----+----- t26 = LCL_VAR int V01 loc0 u:1 <l:$286, c:$287>
/--* t68 byref
+--* t26 int
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int $VN.Void
Addressing mode:
Base
N009 ( 1, 1) [000038] -----+----- * LCL_VAR byref V00 arg0 u:1 $80
+ 8
Removing unused node:
N010 ( 1, 1) [000069] -c---+----- * CNS_INT long 8 $105
New addressing mode node:
N011 ( 2, 2) [000070] -----+----- * LEA(b+8) byref
lowering store lcl var/field (before):
N001 ( 1, 1) [000012] -----+----- t12 = LCL_VAR long V04 tmp1 u:1 (last use) <l:$2cc, c:$2cd>
N002 ( 1, 1) [000030] -----+----- t30 = LCL_VAR int V01 loc0 u:1 (last use) <l:$286, c:$287>
N003 ( 1, 4) [000032] -c---+----- t32 = CNS_INT int 0x3B9ACA00 $47
/--* t30 int
+--* t32 int
N004 ( 6, 8) [000033] -----+----- t33 = * MUL int <l:$288, c:$289>
/--* t33 int
N005 ( 7, 10) [000034] -----+---U- t34 = * CAST long <- ulong <- uint <l:$2d4, c:$2d5>
/--* t12 long
+--* t34 long
N006 ( 9, 12) [000035] -----+----- t35 = * SUB long <l:$2d6, c:$2d7>
N007 ( 1, 1) [000036] -c---+----- t36 = CNS_INT int 32 $44
/--* t35 long
+--* t36 int
N008 ( 11, 14) [000037] -----+----- t37 = * LSH long <l:$2d8, c:$2d9>
N009 ( 1, 1) [000038] -----+----- t38 = LCL_VAR byref V00 arg0 u:1 $80
/--* t38 byref
N011 ( 2, 2) [000070] -c---+----- t70 = * LEA(b+8) byref
/--* t70 byref
N012 ( 4, 4) [000040] nc--G+----- t40 = * IND int <l:$182, c:$1c2>
/--* t40 int
N013 ( 5, 6) [000041] ----G+---U- t41 = * CAST long <- ulong <- uint <l:$2da, c:$2db>
/--* t37 long
+--* t41 long
N014 ( 17, 21) [000042] ----G+----- t42 = * ADD long <l:$2dc, c:$2dd>
/--* t42 long
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000012] -----+----- t12 = LCL_VAR long V04 tmp1 u:1 (last use) <l:$2cc, c:$2cd>
N002 ( 1, 1) [000030] -----+----- t30 = LCL_VAR int V01 loc0 u:1 (last use) <l:$286, c:$287>
N003 ( 1, 4) [000032] -c---+----- t32 = CNS_INT int 0x3B9ACA00 $47
/--* t30 int
+--* t32 int
N004 ( 6, 8) [000033] -----+----- t33 = * MUL int <l:$288, c:$289>
/--* t33 int
N005 ( 7, 10) [000034] -----+---U- t34 = * CAST long <- ulong <- uint <l:$2d4, c:$2d5>
/--* t12 long
+--* t34 long
N006 ( 9, 12) [000035] -----+----- t35 = * SUB long <l:$2d6, c:$2d7>
N007 ( 1, 1) [000036] -c---+----- t36 = CNS_INT int 32 $44
/--* t35 long
+--* t36 int
N008 ( 11, 14) [000037] -----+----- t37 = * LSH long <l:$2d8, c:$2d9>
N009 ( 1, 1) [000038] -----+----- t38 = LCL_VAR byref V00 arg0 u:1 $80
/--* t38 byref
N011 ( 2, 2) [000070] -c---+----- t70 = * LEA(b+8) byref
/--* t70 byref
N012 ( 4, 4) [000040] nc--G+----- t40 = * IND int <l:$182, c:$1c2>
/--* t40 int
N013 ( 5, 6) [000041] ----G+---U- t41 = * CAST long <- ulong <- uint <l:$2da, c:$2db>
/--* t37 long
+--* t41 long
N014 ( 17, 21) [000042] ----G+----- t42 = * ADD long <l:$2dc, c:$2dd>
/--* t42 long
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000045] ----------- t45 = LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -------N--- t47 = CNS_INT long 0x44b82fa09b5a53 $103
[000078] -c--------- t78 = CNS_INT int 9
/--* t45 long
+--* t78 int
[000079] ----------- t79 = * RSZ long REG rax
/--* t79 long
+--* t47 long
[000080] ---------U- t80 = * MULHI long
[000081] -c--------- t81 = CNS_INT int 11
/--* t80 long
+--* t81 int
N003 ( 22, 8) [000048] ----------- t48 = * RSZ long
/--* t48 long
N004 ( 23, 10) [000049] ----------- t49 = * CAST int <- uint <- long <l:$28a, c:$28b>
/--* t49 int
N005 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
lowering store lcl var/field (after):
N001 ( 1, 1) [000045] ----------- t45 = LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -------N--- t47 = CNS_INT long 0x44b82fa09b5a53 $103
[000078] -c--------- t78 = CNS_INT int 9
/--* t45 long
+--* t78 int
[000079] ----------- t79 = * RSZ long REG rax
/--* t79 long
+--* t47 long
[000080] ---------U- t80 = * MULHI long
[000081] -c--------- t81 = CNS_INT int 11
/--* t80 long
+--* t81 int
N003 ( 22, 8) [000048] ----------- t48 = * RSZ long
/--* t48 long
N004 ( 23, 10) [000049] ----------- t49 = * CAST int <- uint <- long <l:$28a, c:$28b>
/--* t49 int
N005 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
Addressing mode:
Base
N001 ( 1, 1) [000051] -----+----- * LCL_VAR byref V00 arg0 u:1 (last use) $80
+ 8
Removing unused node:
N002 ( 1, 1) [000071] -c---+----- * CNS_INT long 8 $105
New addressing mode node:
N003 ( 2, 2) [000072] -----+----- * LEA(b+8) byref
Lower of StoreInd didn't mark the node as self contained for reason: oper is not supported
N001 ( 1, 1) [000051] -----+----- t51 = LCL_VAR byref V00 arg0 u:1 (last use) $80
/--* t51 byref
N003 ( 2, 2) [000072] -----+----- t72 = * LEA(b+8) byref
N004 ( 1, 1) [000052] -----+----- t52 = LCL_VAR int V02 loc1 u:1 <l:$28a, c:$28b>
/--* t72 byref
+--* t52 int
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int $VN.Void
lowering return node
N006 ( 9, 11) [000060] -----+----- * RETURN int $VN.Void
============
Lower has completed modifying nodes.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
[000073] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V00 arg0 u:1 $80
/--* t0 byref
N003 ( 2, 2) [000062] -c--------- t62 = * LEA(b+4) byref
/--* t62 byref
N004 ( 4, 4) [000002] -c-XG------ t2 = * IND int <l:$281, c:$280>
/--* t2 int
N005 ( 5, 6) [000003] ---XG----U- t3 = * CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N006 ( 1, 1) [000004] -c--------- t4 = CNS_INT int 32 $44
/--* t3 long
+--* t4 int
N007 ( 7, 8) [000005] ---XG------ t5 = * LSH long <l:$2c7, c:$2c6>
N008 ( 1, 1) [000006] ----------- t6 = LCL_VAR byref V00 arg0 u:1 $80
/--* t6 byref
N010 ( 2, 2) [000064] -c--------- t64 = * LEA(b+12) byref
/--* t64 byref
N011 ( 4, 4) [000008] nc--GO----- t8 = * IND int <l:$283, c:$282>
/--* t8 int
N012 ( 5, 6) [000009] ----GO---U- t9 = * CAST long <- ulong <- uint <l:$2c9, c:$2cb>
/--* t5 long
+--* t9 long
N013 ( 13, 15) [000010] ---XGO----- t10 = * ADD long <l:$2cf, c:$2ce>
/--* t10 long
N014 ( 13, 15) [000011] DA-XGO----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
N001 ( 1, 1) [000013] ----------- t13 = LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -------N--- t15 = CNS_INT long 0x44b82fa09b5a53 $103
[000074] -c--------- t74 = CNS_INT int 9
/--* t13 long
+--* t74 int
[000075] ----------- t75 = * RSZ long REG rax
/--* t75 long
+--* t15 long
[000076] ---------U- t76 = * MULHI long
[000077] -c--------- t77 = CNS_INT int 11
/--* t76 long
+--* t77 int
N003 ( 22, 8) [000016] ----------- t16 = * RSZ long
/--* t16 long
N004 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
N001 ( 1, 1) [000019] -----+----- t19 = LCL_VAR long V01 loc0 u:1 <l:$2d0, c:$2d1>
N002 ( 1, 1) [000020] -c---+----- t20 = CNS_INT int 32 $44
/--* t19 long
+--* t20 int
N003 ( 3, 3) [000021] -----+----- t21 = * RSZ long <l:$2d2, c:$2d3>
/--* t21 long
N004 ( 4, 5) [000022] -----+----- t22 = * CAST int <- uint <- long <l:$284, c:$285>
N005 ( 1, 1) [000018] -----+----- t18 = LCL_VAR byref V00 arg0 u:1 $80
/--* t18 byref
N007 ( 2, 2) [000066] -c---+----- t66 = * LEA(b+4) byref
/--* t66 byref
+--* t22 int
N008 ( 9, 10) [000024] nA--G+----- * STOREIND int $VN.Void
N001 ( 1, 1) [000025] -----+----- t25 = LCL_VAR byref V00 arg0 u:1 $80
/--* t25 byref
N003 ( 2, 2) [000068] -c---+----- t68 = * LEA(b+12) byref
N004 ( 1, 1) [000026] -----+----- t26 = LCL_VAR int V01 loc0 u:1 <l:$286, c:$287>
/--* t68 byref
+--* t26 int
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int $VN.Void
N001 ( 1, 1) [000012] -----+----- t12 = LCL_VAR long V04 tmp1 u:1 (last use) <l:$2cc, c:$2cd>
N002 ( 1, 1) [000030] -----+----- t30 = LCL_VAR int V01 loc0 u:1 (last use) <l:$286, c:$287>
N003 ( 1, 4) [000032] -c---+----- t32 = CNS_INT int 0x3B9ACA00 $47
/--* t30 int
+--* t32 int
N004 ( 6, 8) [000033] -----+----- t33 = * MUL int <l:$288, c:$289>
/--* t33 int
N005 ( 7, 10) [000034] -----+---U- t34 = * CAST long <- ulong <- uint <l:$2d4, c:$2d5>
/--* t12 long
+--* t34 long
N006 ( 9, 12) [000035] -----+----- t35 = * SUB long <l:$2d6, c:$2d7>
N007 ( 1, 1) [000036] -c---+----- t36 = CNS_INT int 32 $44
/--* t35 long
+--* t36 int
N008 ( 11, 14) [000037] -----+----- t37 = * LSH long <l:$2d8, c:$2d9>
N009 ( 1, 1) [000038] -----+----- t38 = LCL_VAR byref V00 arg0 u:1 $80
/--* t38 byref
N011 ( 2, 2) [000070] -c---+----- t70 = * LEA(b+8) byref
/--* t70 byref
N012 ( 4, 4) [000040] nc--G+----- t40 = * IND int <l:$182, c:$1c2>
/--* t40 int
N013 ( 5, 6) [000041] ----G+---U- t41 = * CAST long <- ulong <- uint <l:$2da, c:$2db>
/--* t37 long
+--* t41 long
N014 ( 17, 21) [000042] ----G+----- t42 = * ADD long <l:$2dc, c:$2dd>
/--* t42 long
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 $VN.Void
N001 ( 1, 1) [000045] ----------- t45 = LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -------N--- t47 = CNS_INT long 0x44b82fa09b5a53 $103
[000078] -c--------- t78 = CNS_INT int 9
/--* t45 long
+--* t78 int
[000079] ----------- t79 = * RSZ long REG rax
/--* t79 long
+--* t47 long
[000080] ---------U- t80 = * MULHI long
[000081] -c--------- t81 = CNS_INT int 11
/--* t80 long
+--* t81 int
N003 ( 22, 8) [000048] ----------- t48 = * RSZ long
/--* t48 long
N004 ( 23, 10) [000049] ----------- t49 = * CAST int <- uint <- long <l:$28a, c:$28b>
/--* t49 int
N005 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
N001 ( 1, 1) [000051] -----+----- t51 = LCL_VAR byref V00 arg0 u:1 (last use) $80
/--* t51 byref
N003 ( 2, 2) [000072] -c---+----- t72 = * LEA(b+8) byref
N004 ( 1, 1) [000052] -----+----- t52 = LCL_VAR int V02 loc1 u:1 <l:$28a, c:$28b>
/--* t72 byref
+--* t52 int
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int $VN.Void
N001 ( 1, 1) [000044] -----+----- t44 = LCL_VAR int V05 tmp2 u:1 (last use) <l:$28c, c:$28d>
N002 ( 1, 1) [000056] -----+----- t56 = LCL_VAR int V02 loc1 u:1 (last use) <l:$28a, c:$28b>
N003 ( 1, 4) [000057] -c---+----- t57 = CNS_INT int 0x3B9ACA00 $47
/--* t56 int
+--* t57 int
N004 ( 6, 8) [000058] -----+----- t58 = * MUL int <l:$28e, c:$28f>
/--* t44 int
+--* t58 int
N005 ( 8, 10) [000059] -----+----- t59 = * SUB int <l:$290, c:$291>
/--* t59 int
N006 ( 9, 11) [000060] -----+----- * RETURN int $VN.Void
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V04: refCnt = 2, refCntWtd = 4
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V04: refCnt = 3, refCntWtd = 6
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V00: refCnt = 5, refCntWtd = 5
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V05: refCnt = 2, refCntWtd = 4
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 6, refCntWtd = 6
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 3, refCntWtd = 6
New refCnts for V02: refCnt = 3, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 7, refCntWtd = 7
New refCnts for V00: refCnt = 8, refCntWtd = 8
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 byref single-def
; V01 loc0 long
; V02 loc1 int
; V03 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
; V04 tmp1 long "dup spill"
; V05 tmp2 long "dup spill"
In fgLocalVarLivenessInit
Local V03 should not be enregistered because: struct size does not match reg size
Tracked variable (5 out of 6) table:
V00 arg0 [ byref]: refCnt = 8, refCntWtd = 8
V04 tmp1 [ long]: refCnt = 3, refCntWtd = 6
V05 tmp2 [ long]: refCnt = 3, refCntWtd = 6
V01 loc0 [ long]: refCnt = 4, refCntWtd = 4
V02 loc1 [ int]: refCnt = 3, refCntWtd = 3
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(4)={ V04 V05 V01 V02} + ByrefExposed + GcHeap
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V04: refCnt = 2, refCntWtd = 4
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V04: refCnt = 3, refCntWtd = 6
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V00: refCnt = 5, refCntWtd = 5
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V05: refCnt = 2, refCntWtd = 4
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 6, refCntWtd = 6
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 3, refCntWtd = 6
New refCnts for V02: refCnt = 3, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 7, refCntWtd = 7
New refCnts for V00: refCnt = 8, refCntWtd = 8
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
[000073] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V00 arg0 u:1 $80
/--* t0 byref
N003 ( 2, 2) [000062] -c--------- t62 = * LEA(b+4) byref
/--* t62 byref
N004 ( 4, 4) [000002] -c-XG------ t2 = * IND int <l:$281, c:$280>
/--* t2 int
N005 ( 5, 6) [000003] ---XG----U- t3 = * CAST long <- ulong <- uint <l:$2c1, c:$2c3>
N006 ( 1, 1) [000004] -c--------- t4 = CNS_INT int 32 $44
/--* t3 long
+--* t4 int
N007 ( 7, 8) [000005] ---XG------ t5 = * LSH long <l:$2c7, c:$2c6>
N008 ( 1, 1) [000006] ----------- t6 = LCL_VAR byref V00 arg0 u:1 $80
/--* t6 byref
N010 ( 2, 2) [000064] -c--------- t64 = * LEA(b+12) byref
/--* t64 byref
N011 ( 4, 4) [000008] nc--GO----- t8 = * IND int <l:$283, c:$282>
/--* t8 int
N012 ( 5, 6) [000009] ----GO---U- t9 = * CAST long <- ulong <- uint <l:$2c9, c:$2cb>
/--* t5 long
+--* t9 long
N013 ( 13, 15) [000010] ---XGO----- t10 = * ADD long <l:$2cf, c:$2ce>
/--* t10 long
N014 ( 13, 15) [000011] DA-XGO----- * STORE_LCL_VAR long V04 tmp1 d:1 $241
N001 ( 1, 1) [000013] ----------- t13 = LCL_VAR long V04 tmp1 u:1 <l:$2cc, c:$2cd>
N002 ( 1, 4) [000015] -------N--- t15 = CNS_INT long 0x44b82fa09b5a53 $103
[000074] -c--------- t74 = CNS_INT int 9
/--* t13 long
+--* t74 int
[000075] ----------- t75 = * RSZ long REG rax
/--* t75 long
+--* t15 long
[000076] ---------U- t76 = * MULHI long
[000077] -c--------- t77 = CNS_INT int 11
/--* t76 long
+--* t77 int
N003 ( 22, 8) [000016] ----------- t16 = * RSZ long
/--* t16 long
N004 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 $VN.Void
N001 ( 1, 1) [000019] -----+----- t19 = LCL_VAR long V01 loc0 u:1 <l:$2d0, c:$2d1>
N002 ( 1, 1) [000020] -c---+----- t20 = CNS_INT int 32 $44
/--* t19 long
+--* t20 int
N003 ( 3, 3) [000021] -----+----- t21 = * RSZ long <l:$2d2, c:$2d3>
/--* t21 long
N004 ( 4, 5) [000022] -----+----- t22 = * CAST int <- uint <- long <l:$284, c:$285>
N005 ( 1, 1) [000018] -----+----- t18 = LCL_VAR byref V00 arg0 u:1 $80
/--* t18 byref
N007 ( 2, 2) [000066] -c---+----- t66 = * LEA(b+4) byref
/--* t66 byref
+--* t22 int
N008 ( 9, 10) [000024] nA--G+----- * STOREIND int $VN.Void
N001 ( 1, 1) [000025] -----+----- t25 = LCL_VAR byref V00 arg0 u:1 $80
/--* t25 byref
N003 ( 2, 2) [000068] -c---+----- t68 = * LEA(b+12) byref
N004 ( 1, 1) [000026] -----+----- t26 = LCL_VAR int V01 loc0 u:1 <l:$286, c:$287>
/--* t68 byref
+--* t26 int
N005 ( 6, 6) [000029] nA--G+----- * STOREIND int $VN.Void
N001 ( 1, 1) [000012] -----+----- t12 = LCL_VAR long V04 tmp1 u:1 (last use) <l:$2cc, c:$2cd>
N002 ( 1, 1) [000030] -----+----- t30 = LCL_VAR int V01 loc0 u:1 (last use) <l:$286, c:$287>
N003 ( 1, 4) [000032] -c---+----- t32 = CNS_INT int 0x3B9ACA00 $47
/--* t30 int
+--* t32 int
N004 ( 6, 8) [000033] -----+----- t33 = * MUL int <l:$288, c:$289>
/--* t33 int
N005 ( 7, 10) [000034] -----+---U- t34 = * CAST long <- ulong <- uint <l:$2d4, c:$2d5>
/--* t12 long
+--* t34 long
N006 ( 9, 12) [000035] -----+----- t35 = * SUB long <l:$2d6, c:$2d7>
N007 ( 1, 1) [000036] -c---+----- t36 = CNS_INT int 32 $44
/--* t35 long
+--* t36 int
N008 ( 11, 14) [000037] -----+----- t37 = * LSH long <l:$2d8, c:$2d9>
N009 ( 1, 1) [000038] -----+----- t38 = LCL_VAR byref V00 arg0 u:1 $80
/--* t38 byref
N011 ( 2, 2) [000070] -c---+----- t70 = * LEA(b+8) byref
/--* t70 byref
N012 ( 4, 4) [000040] nc--G+----- t40 = * IND int <l:$182, c:$1c2>
/--* t40 int
N013 ( 5, 6) [000041] ----G+---U- t41 = * CAST long <- ulong <- uint <l:$2da, c:$2db>
/--* t37 long
+--* t41 long
N014 ( 17, 21) [000042] ----G+----- t42 = * ADD long <l:$2dc, c:$2dd>
/--* t42 long
N015 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 $VN.Void
N001 ( 1, 1) [000045] ----------- t45 = LCL_VAR long V05 tmp2 u:1 <l:$2dc, c:$2dd>
N002 ( 1, 4) [000047] -------N--- t47 = CNS_INT long 0x44b82fa09b5a53 $103
[000078] -c--------- t78 = CNS_INT int 9
/--* t45 long
+--* t78 int
[000079] ----------- t79 = * RSZ long REG rax
/--* t79 long
+--* t47 long
[000080] ---------U- t80 = * MULHI long
[000081] -c--------- t81 = CNS_INT int 11
/--* t80 long
+--* t81 int
N003 ( 22, 8) [000048] ----------- t48 = * RSZ long
/--* t48 long
N004 ( 23, 10) [000049] ----------- t49 = * CAST int <- uint <- long <l:$28a, c:$28b>
/--* t49 int
N005 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 $VN.Void
N001 ( 1, 1) [000051] -----+----- t51 = LCL_VAR byref V00 arg0 u:1 (last use) $80
/--* t51 byref
N003 ( 2, 2) [000072] -c---+----- t72 = * LEA(b+8) byref
N004 ( 1, 1) [000052] -----+----- t52 = LCL_VAR int V02 loc1 u:1 <l:$28a, c:$28b>
/--* t72 byref
+--* t52 int
N005 ( 6, 6) [000054] nA--G+----- * STOREIND int $VN.Void
N001 ( 1, 1) [000044] -----+----- t44 = LCL_VAR int V05 tmp2 u:1 (last use) <l:$28c, c:$28d>
N002 ( 1, 1) [000056] -----+----- t56 = LCL_VAR int V02 loc1 u:1 (last use) <l:$28a, c:$28b>
N003 ( 1, 4) [000057] -c---+----- t57 = CNS_INT int 0x3B9ACA00 $47
/--* t56 int
+--* t57 int
N004 ( 6, 8) [000058] -----+----- t58 = * MUL int <l:$28e, c:$28f>
/--* t44 int
+--* t58 int
N005 ( 8, 10) [000059] -----+----- t59 = * SUB int <l:$290, c:$291>
/--* t59 int
N006 ( 9, 11) [000060] -----+----- * RETURN int $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01
use: {V00}
def: {V01 V02 V04 V05}
in: {V00}
out: {}
Interval 0: byref RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 0: (V00) byref RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 1: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 1: (V01) long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 2: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 2: (V02) int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 3: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 3: (V04) long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 4: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 4: (V05) long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
Start LSRA Block Sequence:
Current block: BB01
Final LSRA Block Sequence:
BB01 ( 1 )
BB01 [0000] [000..05E) (return), preds={} succs={}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. V00(t0)
N003. t62 = LEA(b+4) ; t0
N004. t2 = IND ; t62
N005. t3 = CAST ; t2
N006. CNS_INT 32
N007. t5 = LSH ; t3
N008. V00(t6)
N010. t64 = LEA(b+12); t6
N011. t8 = IND ; t64
N012. t9 = CAST ; t8
N013. t10 = ADD ; t5,t9
N014. V04(t11); t10
N001. V04(t13)
N002. t15 = CNS_INT 0x44b82fa09b5a53
N000. CNS_INT 9
N000. t75 = RSZ ; t13
N000. t76 = MULHI ; t75,t15
N000. CNS_INT 11
N003. t16 = RSZ ; t76
N004. V01(t17); t16
N001. V01(t19)
N002. CNS_INT 32
N003. t21 = RSZ ; t19
N004. t22 = CAST ; t21
N005. V00(t18)
N007. t66 = LEA(b+4) ; t18
N008. STOREIND ; t66,t22
N001. V00(t25)
N003. t68 = LEA(b+12); t25
N004. V01(t26)
N005. STOREIND ; t68,t26
N001. V04(t12*)
N002. V01(t30*)
N003. CNS_INT 0x3B9ACA00
N004. t33 = MUL ; t30*
N005. t34 = CAST ; t33
N006. t35 = SUB ; t12*,t34
N007. CNS_INT 32
N008. t37 = LSH ; t35
N009. V00(t38)
N011. t70 = LEA(b+8) ; t38
N012. t40 = IND ; t70
N013. t41 = CAST ; t40
N014. t42 = ADD ; t37,t41
N015. V05(t43); t42
N001. V05(t45)
N002. t47 = CNS_INT 0x44b82fa09b5a53
N000. CNS_INT 9
N000. t79 = RSZ ; t45
N000. t80 = MULHI ; t79,t47
N000. CNS_INT 11
N003. t48 = RSZ ; t80
N004. t49 = CAST ; t48
N005. V02(t50); t49
N001. V00(t51*)
N003. t72 = LEA(b+8) ; t51*
N004. V02(t52)
N005. STOREIND ; t72,t52
N001. V05(t44*)
N002. V02(t56*)
N003. CNS_INT 0x3B9ACA00
N004. t58 = MUL ; t56*
N005. t59 = SUB ; t44*,t58
N006. RETURN ; t59
buildIntervals second part ========
Arg V00 is live in reg rcx
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed wt=100.00>
NEW BLOCK BB01
<RefPosition #1 @1 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
DefList: { }
N003 (???,???) [000073] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N005 ( 1, 1) [000000] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $80
DefList: { }
N007 ( 2, 2) [000062] -c--------- * LEA(b+4) byref REG NA
Contained
DefList: { }
N009 ( 4, 4) [000002] -c-XG------ * IND int REG NA <l:$281, c:$280>
Contained
DefList: { }
N011 ( 5, 6) [000003] ---XG----U- * CAST long <- ulong <- uint REG NA <l:$2c1, c:$2c3>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
Interval 5: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #3 @12 RefTypeDef <Ivl:5> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N011.t3. CAST }
N013 ( 1, 1) [000004] -c--------- * CNS_INT int 32 REG NA $44
Contained
DefList: { N011.t3. CAST }
N015 ( 7, 8) [000005] ---XG------ * LSH long REG NA <l:$2c7, c:$2c6>
Notify VM instruction set (AVX2) must be supported.
<RefPosition #4 @15 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 6: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #5 @16 RefTypeDef <Ivl:6> LSH BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I6> to <I5>
DefList: { N015.t5. LSH }
N017 ( 1, 1) [000006] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $80
DefList: { N015.t5. LSH }
N019 ( 2, 2) [000064] -c--------- * LEA(b+12) byref REG NA
Contained
DefList: { N015.t5. LSH }
N021 ( 4, 4) [000008] nc--GO----- * IND int REG NA <l:$283, c:$282>
Contained
DefList: { N015.t5. LSH }
N023 ( 5, 6) [000009] ----GO---U- * CAST long <- ulong <- uint REG NA <l:$2c9, c:$2cb>
<RefPosition #6 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
Interval 7: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #7 @24 RefTypeDef <Ivl:7> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N015.t5. LSH; N023.t9. CAST }
N025 ( 13, 15) [000010] ---XGO----- * ADD long REG NA <l:$2cf, c:$2ce>
<RefPosition #8 @25 RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #9 @25 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 8: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #10 @26 RefTypeDef <Ivl:8> ADD BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I8> to <I6>
Assigning related <I8> to <I7>
DefList: { N025.t10. ADD }
N027 ( 13, 15) [000011] DA-XGO----- * STORE_LCL_VAR long V04 tmp1 d:1 NA REG NA $241
<RefPosition #11 @27 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V04/L3> to <I8>
<RefPosition #12 @28 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
DefList: { }
N029 ( 1, 1) [000013] ----------- * LCL_VAR long V04 tmp1 u:1 NA REG NA <l:$2cc, c:$2cd>
DefList: { }
N031 ( 1, 4) [000015] -------N--- * CNS_INT long 0x44b82fa09b5a53 REG NA $103
Interval 9: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #13 @32 RefTypeDef <Ivl:9> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N031.t15. CNS_INT }
N033 (???,???) [000074] -c--------- * CNS_INT int 9 REG NA
Contained
DefList: { N031.t15. CNS_INT }
N035 (???,???) [000075] ----------- * RSZ long REG rax
<RefPosition #14 @35 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
Interval 10: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #15 @36 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #16 @36 RefTypeDef <Ivl:10> RSZ BB01 regmask=[rax] minReg=1 fixed wt=400.00>
DefList: { N031.t15. CNS_INT; N035.t75. RSZ }
N037 (???,???) [000076] ---------U- * MULHI long REG NA
<RefPosition #17 @37 RefTypeUse <Ivl:10> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #18 @37 RefTypeUse <Ivl:9> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #19 @38 RefTypeKill BB01 regmask=[rdx] minReg=1 fixed>
Interval 11: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #20 @38 RefTypeDef <Ivl:11> MULHI BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N037.t76. MULHI }
N039 (???,???) [000077] -c--------- * CNS_INT int 11 REG NA
Contained
DefList: { N037.t76. MULHI }
N041 ( 22, 8) [000016] ----------- * RSZ long REG NA
<RefPosition #21 @41 RefTypeUse <Ivl:11> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 12: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #22 @42 RefTypeDef <Ivl:12> RSZ BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I12> to <I11>
DefList: { N041.t16. RSZ }
N043 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 NA REG NA $VN.Void
<RefPosition #23 @43 RefTypeUse <Ivl:12> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V01/L1> to <I12>
<RefPosition #24 @44 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
DefList: { }
N045 ( 1, 1) [000019] -----+----- * LCL_VAR long V01 loc0 u:1 NA REG NA <l:$2d0, c:$2d1>
DefList: { }
N047 ( 1, 1) [000020] -c---+----- * CNS_INT int 32 REG NA $44
Contained
DefList: { }
N049 ( 3, 3) [000021] -----+----- * RSZ long REG NA <l:$2d2, c:$2d3>
<RefPosition #25 @49 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
Interval 13: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #26 @50 RefTypeDef <Ivl:13> RSZ BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N049.t21. RSZ }
N051 ( 4, 5) [000022] -----+----- * CAST int <- uint <- long REG NA <l:$284, c:$285>
<RefPosition #27 @51 RefTypeUse <Ivl:13> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 14: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #28 @52 RefTypeDef <Ivl:14> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I14> to <I13>
DefList: { N051.t22. CAST }
N053 ( 1, 1) [000018] -----+----- * LCL_VAR byref V00 arg0 u:1 NA REG NA $80
DefList: { N051.t22. CAST }
N055 ( 2, 2) [000066] -c---+----- * LEA(b+4) byref REG NA
Contained
DefList: { N051.t22. CAST }
N057 ( 9, 10) [000024] nA--G+----- * STOREIND int REG NA $VN.Void
<RefPosition #29 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
<RefPosition #30 @57 RefTypeUse <Ivl:14> BB01 regmask=[allInt] minReg=1 last wt=100.00>
DefList: { }
N059 ( 1, 1) [000025] -----+----- * LCL_VAR byref V00 arg0 u:1 NA REG NA $80
DefList: { }
N061 ( 2, 2) [000068] -c---+----- * LEA(b+12) byref REG NA
Contained
DefList: { }
N063 ( 1, 1) [000026] -----+----- * LCL_VAR int V01 loc0 u:1 NA REG NA <l:$286, c:$287>
DefList: { }
N065 ( 6, 6) [000029] nA--G+----- * STOREIND int REG NA $VN.Void
<RefPosition #31 @65 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
<RefPosition #32 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
DefList: { }
N067 ( 1, 1) [000012] -----+----- * LCL_VAR long V04 tmp1 u:1 NA (last use) REG NA <l:$2cc, c:$2cd>
DefList: { }
N069 ( 1, 1) [000030] -----+----- * LCL_VAR int V01 loc0 u:1 NA (last use) REG NA <l:$286, c:$287>
DefList: { }
N071 ( 1, 4) [000032] -c---+----- * CNS_INT int 0x3B9ACA00 REG NA $47
Contained
DefList: { }
N073 ( 6, 8) [000033] -----+----- * MUL int REG NA <l:$288, c:$289>
<RefPosition #33 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00>
Interval 15: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #34 @74 RefTypeDef <Ivl:15> MUL BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N073.t33. MUL }
N075 ( 7, 10) [000034] -----+---U- * CAST long <- ulong <- uint REG NA <l:$2d4, c:$2d5>
<RefPosition #35 @75 RefTypeUse <Ivl:15> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 16: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #36 @76 RefTypeDef <Ivl:16> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N075.t34. CAST }
N077 ( 9, 12) [000035] -----+----- * SUB long REG NA <l:$2d6, c:$2d7>
<RefPosition #37 @77 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
<RefPosition #38 @77 RefTypeUse <Ivl:16> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 17: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #39 @78 RefTypeDef <Ivl:17> SUB BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I17> to <V04/L3>
DefList: { N077.t35. SUB }
N079 ( 1, 1) [000036] -c---+----- * CNS_INT int 32 REG NA $44
Contained
DefList: { N077.t35. SUB }
N081 ( 11, 14) [000037] -----+----- * LSH long REG NA <l:$2d8, c:$2d9>
<RefPosition #40 @81 RefTypeUse <Ivl:17> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 18: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #41 @82 RefTypeDef <Ivl:18> LSH BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I18> to <I17>
DefList: { N081.t37. LSH }
N083 ( 1, 1) [000038] -----+----- * LCL_VAR byref V00 arg0 u:1 NA REG NA $80
DefList: { N081.t37. LSH }
N085 ( 2, 2) [000070] -c---+----- * LEA(b+8) byref REG NA
Contained
DefList: { N081.t37. LSH }
N087 ( 4, 4) [000040] nc--G+----- * IND int REG NA <l:$182, c:$1c2>
Contained
DefList: { N081.t37. LSH }
N089 ( 5, 6) [000041] ----G+---U- * CAST long <- ulong <- uint REG NA <l:$2da, c:$2db>
<RefPosition #42 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
Interval 19: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #43 @90 RefTypeDef <Ivl:19> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N081.t37. LSH; N089.t41. CAST }
N091 ( 17, 21) [000042] ----G+----- * ADD long REG NA <l:$2dc, c:$2dd>
<RefPosition #44 @91 RefTypeUse <Ivl:18> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #45 @91 RefTypeUse <Ivl:19> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 20: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #46 @92 RefTypeDef <Ivl:20> ADD BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I20> to <I18>
Assigning related <I20> to <I19>
DefList: { N091.t42. ADD }
N093 ( 17, 21) [000043] DA--G+----- * STORE_LCL_VAR long V05 tmp2 d:1 NA REG NA $VN.Void
<RefPosition #47 @93 RefTypeUse <Ivl:20> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V05/L4> to <I20>
<RefPosition #48 @94 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
DefList: { }
N095 ( 1, 1) [000045] ----------- * LCL_VAR long V05 tmp2 u:1 NA REG NA <l:$2dc, c:$2dd>
DefList: { }
N097 ( 1, 4) [000047] -------N--- * CNS_INT long 0x44b82fa09b5a53 REG NA $103
Interval 21: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #49 @98 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N097.t47. CNS_INT }
N099 (???,???) [000078] -c--------- * CNS_INT int 9 REG NA
Contained
DefList: { N097.t47. CNS_INT }
N101 (???,???) [000079] ----------- * RSZ long REG rax
<RefPosition #50 @101 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
Interval 22: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #51 @102 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #52 @102 RefTypeDef <Ivl:22> RSZ BB01 regmask=[rax] minReg=1 fixed wt=400.00>
DefList: { N097.t47. CNS_INT; N101.t79. RSZ }
N103 (???,???) [000080] ---------U- * MULHI long REG NA
<RefPosition #53 @103 RefTypeUse <Ivl:22> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #54 @103 RefTypeUse <Ivl:21> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #55 @104 RefTypeKill BB01 regmask=[rdx] minReg=1 fixed>
Interval 23: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #56 @104 RefTypeDef <Ivl:23> MULHI BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N103.t80. MULHI }
N105 (???,???) [000081] -c--------- * CNS_INT int 11 REG NA
Contained
DefList: { N103.t80. MULHI }
N107 ( 22, 8) [000048] ----------- * RSZ long REG NA
<RefPosition #57 @107 RefTypeUse <Ivl:23> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 24: long RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #58 @108 RefTypeDef <Ivl:24> RSZ BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I24> to <I23>
DefList: { N107.t48. RSZ }
N109 ( 23, 10) [000049] ----------- * CAST int <- uint <- long REG NA <l:$28a, c:$28b>
<RefPosition #59 @109 RefTypeUse <Ivl:24> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 25: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #60 @110 RefTypeDef <Ivl:25> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I25> to <I24>
DefList: { N109.t49. CAST }
N111 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 NA REG NA $VN.Void
<RefPosition #61 @111 RefTypeUse <Ivl:25> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V02/L2> to <I25>
<RefPosition #62 @112 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
DefList: { }
N113 ( 1, 1) [000051] -----+----- * LCL_VAR byref V00 arg0 u:1 NA (last use) REG NA $80
DefList: { }
N115 ( 2, 2) [000072] -c---+----- * LEA(b+8) byref REG NA
Contained
DefList: { }
N117 ( 1, 1) [000052] -----+----- * LCL_VAR int V02 loc1 u:1 NA REG NA <l:$28a, c:$28b>
DefList: { }
N119 ( 6, 6) [000054] nA--G+----- * STOREIND int REG NA $VN.Void
<RefPosition #63 @119 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
<RefPosition #64 @119 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
DefList: { }
N121 ( 1, 1) [000044] -----+----- * LCL_VAR int V05 tmp2 u:1 NA (last use) REG NA <l:$28c, c:$28d>
DefList: { }
N123 ( 1, 1) [000056] -----+----- * LCL_VAR int V02 loc1 u:1 NA (last use) REG NA <l:$28a, c:$28b>
DefList: { }
N125 ( 1, 4) [000057] -c---+----- * CNS_INT int 0x3B9ACA00 REG NA $47
Contained
DefList: { }
N127 ( 6, 8) [000058] -----+----- * MUL int REG NA <l:$28e, c:$28f>
<RefPosition #65 @127 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
Interval 26: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #66 @128 RefTypeDef <Ivl:26> MUL BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N127.t58. MUL }
N129 ( 8, 10) [000059] -----+----- * SUB int REG NA <l:$290, c:$291>
<RefPosition #67 @129 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
<RefPosition #68 @129 RefTypeUse <Ivl:26> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Interval 27: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[allMask]
<RefPosition #69 @130 RefTypeDef <Ivl:27> SUB BB01 regmask=[allInt] minReg=1 wt=400.00>
Assigning related <I27> to <V05/L4>
DefList: { N129.t59. SUB }
N131 ( 9, 11) [000060] -----+----- * RETURN int REG NA $VN.Void
<RefPosition #70 @131 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #71 @131 RefTypeUse <Ivl:27> BB01 regmask=[rax] minReg=1 last fixed wt=100.00>
CHECKING LAST USES for BB01, liveout={}
==============================
use: {V00}
def: {V01 V02 V04 V05}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) byref RefPositions {#0@0 #2@11 #6@23 #29@57 #31@65 #42@89 #63@119} physReg:rcx Preferences=[rcx] Aversions=[rdx]
Interval 1: (V01) long RefPositions {#24@44 #25@49 #32@65 #33@73} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 2: (V02) int RefPositions {#62@112 #64@119 #65@127} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 3: (V04) long RefPositions {#12@28 #14@35 #37@77} physReg:NA Preferences=[rax rcx rbx rbp rsi rdi r8-r15] Aversions=[rdx] RelatedInterval <I17>
Interval 4: (V05) long RefPositions {#48@94 #50@101 #67@129} physReg:NA Preferences=[rax rcx rbx rbp rsi rdi r8-r15] Aversions=[rdx] RelatedInterval <I27>
Interval 5: long RefPositions {#3@12 #4@15} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I6>
Interval 6: long RefPositions {#5@16 #8@25} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I8>
Interval 7: long RefPositions {#7@24 #9@25} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I8>
Interval 8: long RefPositions {#10@26 #11@27} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V04/L3>
Interval 9: long (constant) RefPositions {#13@32 #18@37} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 10: long RefPositions {#16@36 #17@37} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 11: long RefPositions {#20@38 #21@41} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I12>
Interval 12: long RefPositions {#22@42 #23@43} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V01/L1>
Interval 13: long RefPositions {#26@50 #27@51} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I14>
Interval 14: int RefPositions {#28@52 #30@57} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 15: int RefPositions {#34@74 #35@75} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 16: long RefPositions {#36@76 #38@77} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 17: long (interfering uses) RefPositions {#39@78 #40@81} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I18>
Interval 18: long RefPositions {#41@82 #44@91} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I20>
Interval 19: long RefPositions {#43@90 #45@91} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I20>
Interval 20: long RefPositions {#46@92 #47@93} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V05/L4>
Interval 21: long (constant) RefPositions {#49@98 #54@103} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 22: long RefPositions {#52@102 #53@103} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 23: long RefPositions {#56@104 #57@107} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I24>
Interval 24: long RefPositions {#58@108 #59@109} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I25>
Interval 25: int RefPositions {#60@110 #61@111} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V02/L2>
Interval 26: int RefPositions {#66@128 #68@129} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 27: int (interfering uses) RefPositions {#69@130 #71@131} physReg:NA Preferences=[rax] Aversions=[allMask]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #3 @12 RefTypeDef <Ivl:5> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #4 @15 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #5 @16 RefTypeDef <Ivl:6> LSH BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #6 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #7 @24 RefTypeDef <Ivl:7> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #8 @25 RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #9 @25 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #10 @26 RefTypeDef <Ivl:8> ADD BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #11 @27 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #12 @28 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #13 @32 RefTypeDef <Ivl:9> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #14 @35 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #15 @36 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #16 @36 RefTypeDef <Ivl:10> RSZ BB01 regmask=[rax] minReg=1 fixed wt=400.00>
<RefPosition #17 @37 RefTypeUse <Ivl:10> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #18 @37 RefTypeUse <Ivl:9> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #19 @38 RefTypeKill BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #20 @38 RefTypeDef <Ivl:11> MULHI BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #21 @41 RefTypeUse <Ivl:11> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #22 @42 RefTypeDef <Ivl:12> RSZ BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #23 @43 RefTypeUse <Ivl:12> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #24 @44 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #25 @49 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #26 @50 RefTypeDef <Ivl:13> RSZ BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #27 @51 RefTypeUse <Ivl:13> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #28 @52 RefTypeDef <Ivl:14> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #29 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #30 @57 RefTypeUse <Ivl:14> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #31 @65 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #32 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #33 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #34 @74 RefTypeDef <Ivl:15> MUL BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #35 @75 RefTypeUse <Ivl:15> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #36 @76 RefTypeDef <Ivl:16> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #37 @77 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
<RefPosition #38 @77 RefTypeUse <Ivl:16> BB01 regmask=[allInt] minReg=1 last delay regOptional wt=100.00>
<RefPosition #39 @78 RefTypeDef <Ivl:17> SUB BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #40 @81 RefTypeUse <Ivl:17> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #41 @82 RefTypeDef <Ivl:18> LSH BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #42 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #43 @90 RefTypeDef <Ivl:19> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #44 @91 RefTypeUse <Ivl:18> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #45 @91 RefTypeUse <Ivl:19> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #46 @92 RefTypeDef <Ivl:20> ADD BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #47 @93 RefTypeUse <Ivl:20> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #48 @94 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #49 @98 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #50 @101 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #51 @102 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #52 @102 RefTypeDef <Ivl:22> RSZ BB01 regmask=[rax] minReg=1 fixed wt=400.00>
<RefPosition #53 @103 RefTypeUse <Ivl:22> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #54 @103 RefTypeUse <Ivl:21> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #55 @104 RefTypeKill BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #56 @104 RefTypeDef <Ivl:23> MULHI BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #57 @107 RefTypeUse <Ivl:23> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #58 @108 RefTypeDef <Ivl:24> RSZ BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #59 @109 RefTypeUse <Ivl:24> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #60 @110 RefTypeDef <Ivl:25> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #61 @111 RefTypeUse <Ivl:25> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #62 @112 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #63 @119 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
<RefPosition #64 @119 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #65 @127 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
<RefPosition #66 @128 RefTypeDef <Ivl:26> MUL BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #67 @129 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
<RefPosition #68 @129 RefTypeUse <Ivl:26> BB01 regmask=[allInt] minReg=1 last delay regOptional wt=100.00>
<RefPosition #69 @130 RefTypeDef <Ivl:27> SUB BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #70 @131 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #71 @131 RefTypeUse <Ivl:27> BB01 regmask=[rax] minReg=1 last fixed wt=100.00>
------------
REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval)
------------
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #6 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #29 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #31 @65 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #42 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #63 @119 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
-----------------
<RefPosition #12 @28 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #14 @35 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #37 @77 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
-----------------
<RefPosition #48 @94 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #50 @101 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #67 @129 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
-----------------
<RefPosition #24 @44 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #25 @49 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #32 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #33 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
-----------------
<RefPosition #62 @112 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #64 @119 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #65 @127 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00
BB01 [0000] [000..05E) (return), preds={} succs={}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V00(L0)
N007. LEA(b+4)
N009. IND
N011. CAST
Use:<V00/L0>(#2)
Def:<I5>(#3) Pref:<I6>
N013. CNS_INT 32
N015. LSH
Use:<I5>(#4) *
Def:<I6>(#5) Pref:<I8>
N017. V00(L0)
N019. LEA(b+12)
N021. IND
N023. CAST
Use:<V00/L0>(#6)
Def:<I7>(#7) Pref:<I8>
N025. ADD
Use:<I6>(#8) *
Use:<I7>(#9) *
Def:<I8>(#10) Pref:<V04/L3>
N027. V04(L3)
Use:<I8>(#11) *
Def:<V04/L3>(#12) Pref:<I17>
N029. V04(L3)
N031. CNS_INT 0x44b82fa09b5a53
Def:<I9>(#13)
N033. CNS_INT 9
N035. RSZ
Use:<V04/L3>(#14)
Def:<I10>(#16) rax
N037. MULHI
Use:<I10>(#17) *
Use:<I9>(#18) *
Kill: [rdx]
Def:<I11>(#20) Pref:<I12>
N039. CNS_INT 11
N041. RSZ
Use:<I11>(#21) *
Def:<I12>(#22) Pref:<V01/L1>
N043. V01(L1)
Use:<I12>(#23) *
Def:<V01/L1>(#24)
N045. V01(L1)
N047. CNS_INT 32
N049. RSZ
Use:<V01/L1>(#25)
Def:<I13>(#26) Pref:<I14>
N051. CAST
Use:<I13>(#27) *
Def:<I14>(#28)
N053. V00(L0)
N055. LEA(b+4)
N057. STOREIND
Use:<V00/L0>(#29)
Use:<I14>(#30) *
N059. V00(L0)
N061. LEA(b+12)
N063. V01(L1)
N065. STOREIND
Use:<V00/L0>(#31)
Use:<V01/L1>(#32)
N067. V04(L3)
N069. V01(L1)
N071. CNS_INT 0x3B9ACA00
N073. MUL
Use:<V01/L1>(#33) *
Def:<I15>(#34)
N075. CAST
Use:<I15>(#35) *
Def:<I16>(#36)
N077. SUB
Use:<V04/L3>(#37) *
Use:<I16>(#38) *
Def:<I17>(#39) Pref:<I18>
N079. CNS_INT 32
N081. LSH
Use:<I17>(#40) *
Def:<I18>(#41) Pref:<I20>
N083. V00(L0)
N085. LEA(b+8)
N087. IND
N089. CAST
Use:<V00/L0>(#42)
Def:<I19>(#43) Pref:<I20>
N091. ADD
Use:<I18>(#44) *
Use:<I19>(#45) *
Def:<I20>(#46) Pref:<V05/L4>
N093. V05(L4)
Use:<I20>(#47) *
Def:<V05/L4>(#48) Pref:<I27>
N095. V05(L4)
N097. CNS_INT 0x44b82fa09b5a53
Def:<I21>(#49)
N099. CNS_INT 9
N101. RSZ
Use:<V05/L4>(#50)
Def:<I22>(#52) rax
N103. MULHI
Use:<I22>(#53) *
Use:<I21>(#54) *
Kill: [rdx]
Def:<I23>(#56) Pref:<I24>
N105. CNS_INT 11
N107. RSZ
Use:<I23>(#57) *
Def:<I24>(#58) Pref:<I25>
N109. CAST
Use:<I24>(#59) *
Def:<I25>(#60) Pref:<V02/L2>
N111. V02(L2)
Use:<I25>(#61) *
Def:<V02/L2>(#62)
N113. V00(L0)
N115. LEA(b+8)
N117. V02(L2)
N119. STOREIND
Use:<V00/L0>(#63) *
Use:<V02/L2>(#64)
N121. V05(L4)
N123. V02(L2)
N125. CNS_INT 0x3B9ACA00
N127. MUL
Use:<V02/L2>(#65) *
Def:<I26>(#66)
N129. SUB
Use:<V05/L4>(#67) *
Use:<I26>(#68) *
Def:<I27>(#69)
N131. RETURN
Use:<I27>(#71) Fixed:rax(#70) *
Linear scan intervals after buildIntervals:
Interval 0: (V00) byref RefPositions {#0@0 #2@11 #6@23 #29@57 #31@65 #42@89 #63@119} physReg:rcx Preferences=[rcx] Aversions=[rdx]
Interval 1: (V01) long RefPositions {#24@44 #25@49 #32@65 #33@73} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 2: (V02) int RefPositions {#62@112 #64@119 #65@127} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 3: (V04) long RefPositions {#12@28 #14@35 #37@77} physReg:NA Preferences=[rax rcx rbx rbp rsi rdi r8-r15] Aversions=[rdx] RelatedInterval <I17>
Interval 4: (V05) long RefPositions {#48@94 #50@101 #67@129} physReg:NA Preferences=[rax rcx rbx rbp rsi rdi r8-r15] Aversions=[rdx] RelatedInterval <I27>
Interval 5: long RefPositions {#3@12 #4@15} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I6>
Interval 6: long RefPositions {#5@16 #8@25} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I8>
Interval 7: long RefPositions {#7@24 #9@25} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I8>
Interval 8: long RefPositions {#10@26 #11@27} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V04/L3>
Interval 9: long (constant) RefPositions {#13@32 #18@37} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 10: long RefPositions {#16@36 #17@37} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 11: long RefPositions {#20@38 #21@41} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I12>
Interval 12: long RefPositions {#22@42 #23@43} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V01/L1>
Interval 13: long RefPositions {#26@50 #27@51} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I14>
Interval 14: int RefPositions {#28@52 #30@57} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 15: int RefPositions {#34@74 #35@75} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 16: long RefPositions {#36@76 #38@77} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 17: long (interfering uses) RefPositions {#39@78 #40@81} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I18>
Interval 18: long RefPositions {#41@82 #44@91} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I20>
Interval 19: long RefPositions {#43@90 #45@91} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I20>
Interval 20: long RefPositions {#46@92 #47@93} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V05/L4>
Interval 21: long (constant) RefPositions {#49@98 #54@103} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 22: long RefPositions {#52@102 #53@103} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 23: long RefPositions {#56@104 #57@107} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I24>
Interval 24: long RefPositions {#58@108 #59@109} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I25>
Interval 25: int RefPositions {#60@110 #61@111} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V02/L2>
Interval 26: int RefPositions {#66@128 #68@129} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 27: int (interfering uses) RefPositions {#69@130 #71@131} physReg:NA Preferences=[rax] Aversions=[allMask]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) byref RefPositions {#0@0 #2@11 #6@23 #29@57 #31@65 #42@89 #63@119} physReg:rcx Preferences=[rcx] Aversions=[rdx]
Interval 1: (V01) long RefPositions {#24@44 #25@49 #32@65 #33@73} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 2: (V02) int RefPositions {#62@112 #64@119 #65@127} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 3: (V04) long RefPositions {#12@28 #14@35 #37@77} physReg:NA Preferences=[rax rcx rbx rbp rsi rdi r8-r15] Aversions=[rdx] RelatedInterval <I17>
Interval 4: (V05) long RefPositions {#48@94 #50@101 #67@129} physReg:NA Preferences=[rax rcx rbx rbp rsi rdi r8-r15] Aversions=[rdx] RelatedInterval <I27>
Interval 5: long RefPositions {#3@12 #4@15} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I6>
Interval 6: long RefPositions {#5@16 #8@25} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I8>
Interval 7: long RefPositions {#7@24 #9@25} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I8>
Interval 8: long RefPositions {#10@26 #11@27} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V04/L3>
Interval 9: long (constant) RefPositions {#13@32 #18@37} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 10: long RefPositions {#16@36 #17@37} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 11: long RefPositions {#20@38 #21@41} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I12>
Interval 12: long RefPositions {#22@42 #23@43} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V01/L1>
Interval 13: long RefPositions {#26@50 #27@51} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I14>
Interval 14: int RefPositions {#28@52 #30@57} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 15: int RefPositions {#34@74 #35@75} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 16: long RefPositions {#36@76 #38@77} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 17: long (interfering uses) RefPositions {#39@78 #40@81} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I18>
Interval 18: long RefPositions {#41@82 #44@91} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I20>
Interval 19: long RefPositions {#43@90 #45@91} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I20>
Interval 20: long RefPositions {#46@92 #47@93} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V05/L4>
Interval 21: long (constant) RefPositions {#49@98 #54@103} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 22: long RefPositions {#52@102 #53@103} physReg:NA Preferences=[rax] Aversions=[allMask]
Interval 23: long RefPositions {#56@104 #57@107} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I24>
Interval 24: long RefPositions {#58@108 #59@109} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <I25>
Interval 25: int RefPositions {#60@110 #61@111} physReg:NA Preferences=[allInt] Aversions=[allMask] RelatedInterval <V02/L2>
Interval 26: int RefPositions {#66@128 #68@129} physReg:NA Preferences=[allInt] Aversions=[allMask]
Interval 27: int (interfering uses) RefPositions {#69@130 #71@131} physReg:NA Preferences=[rax] Aversions=[allMask]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #3 @12 RefTypeDef <Ivl:5> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #4 @15 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #5 @16 RefTypeDef <Ivl:6> LSH BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #6 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #7 @24 RefTypeDef <Ivl:7> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #8 @25 RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #9 @25 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #10 @26 RefTypeDef <Ivl:8> ADD BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #11 @27 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #12 @28 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #13 @32 RefTypeDef <Ivl:9> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #14 @35 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #15 @36 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #16 @36 RefTypeDef <Ivl:10> RSZ BB01 regmask=[rax] minReg=1 fixed wt=400.00>
<RefPosition #17 @37 RefTypeUse <Ivl:10> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #18 @37 RefTypeUse <Ivl:9> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #19 @38 RefTypeKill BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #20 @38 RefTypeDef <Ivl:11> MULHI BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #21 @41 RefTypeUse <Ivl:11> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #22 @42 RefTypeDef <Ivl:12> RSZ BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #23 @43 RefTypeUse <Ivl:12> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #24 @44 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #25 @49 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #26 @50 RefTypeDef <Ivl:13> RSZ BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #27 @51 RefTypeUse <Ivl:13> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #28 @52 RefTypeDef <Ivl:14> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #29 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #30 @57 RefTypeUse <Ivl:14> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #31 @65 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #32 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #33 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
<RefPosition #34 @74 RefTypeDef <Ivl:15> MUL BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #35 @75 RefTypeUse <Ivl:15> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #36 @76 RefTypeDef <Ivl:16> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #37 @77 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
<RefPosition #38 @77 RefTypeUse <Ivl:16> BB01 regmask=[allInt] minReg=1 last delay regOptional wt=100.00>
<RefPosition #39 @78 RefTypeDef <Ivl:17> SUB BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #40 @81 RefTypeUse <Ivl:17> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #41 @82 RefTypeDef <Ivl:18> LSH BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #42 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #43 @90 RefTypeDef <Ivl:19> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #44 @91 RefTypeUse <Ivl:18> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #45 @91 RefTypeUse <Ivl:19> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #46 @92 RefTypeDef <Ivl:20> ADD BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #47 @93 RefTypeUse <Ivl:20> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #48 @94 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #49 @98 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #50 @101 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #51 @102 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #52 @102 RefTypeDef <Ivl:22> RSZ BB01 regmask=[rax] minReg=1 fixed wt=400.00>
<RefPosition #53 @103 RefTypeUse <Ivl:22> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #54 @103 RefTypeUse <Ivl:21> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #55 @104 RefTypeKill BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #56 @104 RefTypeDef <Ivl:23> MULHI BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #57 @107 RefTypeUse <Ivl:23> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #58 @108 RefTypeDef <Ivl:24> RSZ BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #59 @109 RefTypeUse <Ivl:24> BB01 regmask=[allInt] minReg=1 last regOptional wt=100.00>
<RefPosition #60 @110 RefTypeDef <Ivl:25> CAST BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #61 @111 RefTypeUse <Ivl:25> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #62 @112 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #63 @119 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
<RefPosition #64 @119 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #65 @127 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
<RefPosition #66 @128 RefTypeDef <Ivl:26> MUL BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #67 @129 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
<RefPosition #68 @129 RefTypeUse <Ivl:26> BB01 regmask=[allInt] minReg=1 last delay regOptional wt=100.00>
<RefPosition #69 @130 RefTypeDef <Ivl:27> SUB BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #70 @131 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #71 @131 RefTypeUse <Ivl:27> BB01 regmask=[rax] minReg=1 last fixed wt=100.00>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #6 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #29 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #31 @65 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #42 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=800.00>
<RefPosition #63 @119 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=800.00>
--- V01 (Interval 1)
<RefPosition #24 @44 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #25 @49 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #32 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #33 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=400.00>
--- V02 (Interval 2)
<RefPosition #62 @112 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #64 @119 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00>
<RefPosition #65 @127 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
--- V03
--- V04 (Interval 3)
<RefPosition #12 @28 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #14 @35 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #37 @77 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
--- V05 (Interval 4)
<RefPosition #48 @94 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #50 @101 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=600.00>
<RefPosition #67 @129 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=600.00>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.
-------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
-------------------------------------------+----+----+----+----+----+----+----+----+----+
| |V00a| | | | | | | |
0.#0 V00 Parm Keep rcx | |V00a| | | | | | | |
1.#1 BB1 PredBB0 | |V00a| | | | | | | |
[000003] 11.#2 V00 Use Keep rcx | |V00a| | | | | | | |
12.#3 I5 Def COREL(A) rax |I5 a|V00a| | | | | | | |
[000005] 15.#4 I5 Use * Keep rax |I5 a|V00a| | | | | | | |
16.#5 I6 Def COVRS(A) rax |I6 a|V00a| | | | | | | |
[000009] 23.#6 V00 Use Keep rcx |I6 a|V00a| | | | | | | |
24.#7 I7 Def ORDER(A) r8 |I6 a|V00a| | | | | |I7 a| |
[000010] 25.#8 I6 Use * Keep rax |I6 a|V00a| | | | | |I7 a| |
25.#9 I7 Use * Keep r8 |I6 a|V00a| | | | | |I7 a| |
26.#10 I8 Def RELPR(A) rax |I8 a|V00a| | | | | | | |
[000011] 27.#11 I8 Use * Keep rax |I8 a|V00a| | | | | | | |
28.#12 V04 Def COVRS(A) rax |V04a|V00a| | | | | | | |
[000015] 32.#13 C9 Def BSFIT(A) rdx |V04a|V00a|C9 a| | | | | | |
[000075] 35.#14 V04 Use Keep rax |V04a|V00a|C9 a| | | | | | |
36.#15 rax Fixd Keep rax |V04a|V00a|C9 a| | | | | | |
36.#16 I10 Def Spill rax | |V00a|C9 a| | | | | | |
Alloc rax |I10a|V00a|C9 a| | | | | | |
[000076] 37.#17 I10 Use * Keep rax |I10a|V00a|C9 a| | | | | | |
37.#18 C9 Use * Keep rdx |I10a|V00a|C9 a| | | | | | |
38.#19 Kill None [rdx]
| |V00a| | | | | | | |
38.#20 I11 Def BSFIT(A) rax |I11a|V00a| | | | | | | |
[000016] 41.#21 I11 Use * Keep rax |I11a|V00a| | | | | | | |
42.#22 I12 Def COVRS(A) rax |I12a|V00a| | | | | | | |
[000017] 43.#23 I12 Use * Keep rax |I12a|V00a| | | | | | | |
44.#24 V01 Def COVRS(A) rax |V01a|V00a| | | | | | | |
[000021] 49.#25 V01 Use Keep rax |V01a|V00a| | | | | | | |
50.#26 I13 Def BSFIT(A) rdx |V01a|V00a|I13a| | | | | | |
[000022] 51.#27 I13 Use * Keep rdx |V01a|V00a|I13a| | | | | | |
52.#28 I14 Def COVRS(A) rdx |V01a|V00a|I14a| | | | | | |
[000024] 57.#29 V00 Use Keep rcx |V01a|V00a|I14a| | | | | | |
57.#30 I14 Use * Keep rdx |V01a|V00a|I14a| | | | | | |
[000029] 65.#31 V00 Use Keep rcx |V01a|V00a| | | | | | | |
65.#32 V01 Use Keep rax |V01a|V00a| | | | | | | |
[000033] 73.#33 V01 Use * Keep rax |V01a|V00a| | | | | | | |
74.#34 I15 Def BSFIT(A) rax |I15a|V00a| | | | | | | |
[000034] 75.#35 I15 Use * Keep rax |I15a|V00a| | | | | | | |
76.#36 I16 Def BSFIT(A) rax |I16a|V00a| | | | | | | |
[000035] 77.#37 V04 Use * ReLod NA |I16a|V00a| | | | | | | |
ORDER(A) r8 |I16a|V00a| | | | | |V04a| |
77.#38 I16 Use *D Keep rax |I16a|V00a| | | | | |V04a| |
78.#39 I17 Def COVRS(A) r8 |I16a|V00a| | | | | |I17a| |
[000037] 81.#40 I17 Use * Keep r8 | |V00a| | | | | |I17a| |
82.#41 I18 Def COVRS(A) r8 | |V00a| | | | | |I18a| |
[000041] 89.#42 V00 Use Keep rcx | |V00a| | | | | |I18a| |
90.#43 I19 Def COREL(A) rax |I19a|V00a| | | | | |I18a| |
[000042] 91.#44 I18 Use * Keep r8 |I19a|V00a| | | | | |I18a| |
91.#45 I19 Use * Keep rax |I19a|V00a| | | | | |I18a| |
92.#46 I20 Def RELPR(A) rax |I20a|V00a| | | | | | | |
[000043] 93.#47 I20 Use * Keep rax |I20a|V00a| | | | | | | |
-------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
-------------------------------------------+----+----+----+----+----+----+----+----+----+
94.#48 V05 Def COVRS(A) rax |V05a|V00a| | | | | | | |
[000047] 98.#49 C21 Def BSFIT(A) rdx |V05a|V00a|C21a| | | | | | |
[000079] 101.#50 V05 Use Keep rax |V05a|V00a|C21a| | | | | | |
102.#51 rax Fixd Keep rax |V05a|V00a|C21a| | | | | | |
102.#52 I22 Def Spill rax | |V00a|C21a| | | | | | |
Alloc rax |I22a|V00a|C21a| | | | | | |
[000080] 103.#53 I22 Use * Keep rax |I22a|V00a|C21a| | | | | | |
103.#54 C21 Use * Keep rdx |I22a|V00a|C21a| | | | | | |
104.#55 Kill None [rdx]
| |V00a| | | | | | | |
104.#56 I23 Def BSFIT(A) rax |I23a|V00a| | | | | | | |
[000048] 107.#57 I23 Use * Keep rax |I23a|V00a| | | | | | | |
108.#58 I24 Def COVRS(A) rax |I24a|V00a| | | | | | | |
[000049] 109.#59 I24 Use * Keep rax |I24a|V00a| | | | | | | |
110.#60 I25 Def COVRS(A) rax |I25a|V00a| | | | | | | |
[000050] 111.#61 I25 Use * Keep rax |I25a|V00a| | | | | | | |
112.#62 V02 Def COVRS(A) rax |V02a|V00a| | | | | | | |
[000054] 119.#63 V00 Use * Keep rcx |V02a|V00a| | | | | | | |
119.#64 V02 Use Keep rax |V02a|V00a| | | | | | | |
[000058] 127.#65 V02 Use * Keep rax |V02a| | | | | | | | |
128.#66 I26 Def BSFIT(A) rax |I26a| | | | | | | | |
[000059] 129.#67 V05 Use * ReLod NA |I26a| | | | | | | | |
ORDER(A) rcx |I26a|V05a| | | | | | | |
129.#68 I26 Use *D Keep rax |I26a|V05a| | | | | | | |
130.#69 I27 Def COVRS(A) rcx |I26a|I27a| | | | | | | |
[000060] 131.#70 rax Fixd Keep rax | |I27a| | | | | | | |
131.#71 I27 Use * Copy rax | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[allMask] minReg=1 wt=100.00>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #3 @12 RefTypeDef <Ivl:5> CAST BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #4 @15 RefTypeUse <Ivl:5> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #5 @16 RefTypeDef <Ivl:6> LSH BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #6 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #7 @24 RefTypeDef <Ivl:7> CAST BB01 regmask=[r8] minReg=1 wt=400.00>
<RefPosition #8 @25 RefTypeUse <Ivl:6> BB01 regmask=[rax] minReg=1 last regOptional wt=100.00>
<RefPosition #9 @25 RefTypeUse <Ivl:7> BB01 regmask=[r8] minReg=1 last wt=100.00>
<RefPosition #10 @26 RefTypeDef <Ivl:8> ADD BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #11 @27 RefTypeUse <Ivl:8> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #12 @28 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 singleDefSpill wt=300.00>
<RefPosition #13 @32 RefTypeDef <Ivl:9> CNS_INT BB01 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #14 @35 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[rax] minReg=1 spillAfter wt=300.00>
<RefPosition #15 @36 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #16 @36 RefTypeDef <Ivl:10> RSZ BB01 regmask=[rax] minReg=1 fixed wt=400.00>
<RefPosition #17 @37 RefTypeUse <Ivl:10> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #18 @37 RefTypeUse <Ivl:9> BB01 regmask=[rdx] minReg=1 last regOptional wt=100.00>
<RefPosition #19 @38 RefTypeKill BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #20 @38 RefTypeDef <Ivl:11> MULHI BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #21 @41 RefTypeUse <Ivl:11> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #22 @42 RefTypeDef <Ivl:12> RSZ BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #23 @43 RefTypeUse <Ivl:12> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #24 @44 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #25 @49 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #26 @50 RefTypeDef <Ivl:13> RSZ BB01 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #27 @51 RefTypeUse <Ivl:13> BB01 regmask=[rdx] minReg=1 last regOptional wt=100.00>
<RefPosition #28 @52 RefTypeDef <Ivl:14> CAST BB01 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #29 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #30 @57 RefTypeUse <Ivl:14> BB01 regmask=[rdx] minReg=1 last wt=100.00>
<RefPosition #31 @65 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #32 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #33 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional wt=400.00>
<RefPosition #34 @74 RefTypeDef <Ivl:15> MUL BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #35 @75 RefTypeUse <Ivl:15> BB01 regmask=[rax] minReg=1 last regOptional wt=100.00>
<RefPosition #36 @76 RefTypeDef <Ivl:16> CAST BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #37 @77 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[r8] minReg=1 last reload wt=300.00>
<RefPosition #38 @77 RefTypeUse <Ivl:16> BB01 regmask=[rax] minReg=1 last delay regOptional wt=100.00>
<RefPosition #39 @78 RefTypeDef <Ivl:17> SUB BB01 regmask=[r8] minReg=1 wt=400.00>
<RefPosition #40 @81 RefTypeUse <Ivl:17> BB01 regmask=[r8] minReg=1 last wt=100.00>
<RefPosition #41 @82 RefTypeDef <Ivl:18> LSH BB01 regmask=[r8] minReg=1 wt=400.00>
<RefPosition #42 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #43 @90 RefTypeDef <Ivl:19> CAST BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #44 @91 RefTypeUse <Ivl:18> BB01 regmask=[r8] minReg=1 last regOptional wt=100.00>
<RefPosition #45 @91 RefTypeUse <Ivl:19> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #46 @92 RefTypeDef <Ivl:20> ADD BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #47 @93 RefTypeUse <Ivl:20> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #48 @94 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 singleDefSpill wt=300.00>
<RefPosition #49 @98 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[rdx] minReg=1 wt=400.00>
<RefPosition #50 @101 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[rax] minReg=1 spillAfter wt=300.00>
<RefPosition #51 @102 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #52 @102 RefTypeDef <Ivl:22> RSZ BB01 regmask=[rax] minReg=1 fixed wt=400.00>
<RefPosition #53 @103 RefTypeUse <Ivl:22> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #54 @103 RefTypeUse <Ivl:21> BB01 regmask=[rdx] minReg=1 last regOptional wt=100.00>
<RefPosition #55 @104 RefTypeKill BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #56 @104 RefTypeDef <Ivl:23> MULHI BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #57 @107 RefTypeUse <Ivl:23> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #58 @108 RefTypeDef <Ivl:24> RSZ BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #59 @109 RefTypeUse <Ivl:24> BB01 regmask=[rax] minReg=1 last regOptional wt=100.00>
<RefPosition #60 @110 RefTypeDef <Ivl:25> CAST BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #61 @111 RefTypeUse <Ivl:25> BB01 regmask=[rax] minReg=1 last wt=100.00>
<RefPosition #62 @112 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #63 @119 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 last wt=800.00>
<RefPosition #64 @119 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #65 @127 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional wt=300.00>
<RefPosition #66 @128 RefTypeDef <Ivl:26> MUL BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #67 @129 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[rcx] minReg=1 last reload wt=300.00>
<RefPosition #68 @129 RefTypeUse <Ivl:26> BB01 regmask=[rax] minReg=1 last delay regOptional wt=100.00>
<RefPosition #69 @130 RefTypeDef <Ivl:27> SUB BB01 regmask=[rcx] minReg=1 wt=400.00>
<RefPosition #70 @131 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1 wt=100.00>
<RefPosition #71 @131 RefTypeUse <Ivl:27> BB01 regmask=[rax] minReg=1 last move fixed wt=100.00>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #6 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #29 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #31 @65 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #42 @89 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=800.00>
<RefPosition #63 @119 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rcx] minReg=1 last wt=800.00>
--- V01 (Interval 1)
<RefPosition #24 @44 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #25 @49 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #32 @65 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rax] minReg=1 wt=400.00>
<RefPosition #33 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional wt=400.00>
--- V02 (Interval 2)
<RefPosition #62 @112 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #64 @119 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[rax] minReg=1 wt=300.00>
<RefPosition #65 @127 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional wt=300.00>
--- V03
--- V04 (Interval 3)
<RefPosition #12 @28 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 singleDefSpill wt=300.00>
<RefPosition #14 @35 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[rax] minReg=1 spillAfter wt=300.00>
<RefPosition #37 @77 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[r8] minReg=1 last reload wt=300.00>
--- V05 (Interval 4)
<RefPosition #48 @94 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[rax] minReg=1 singleDefSpill wt=300.00>
<RefPosition #50 @101 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[rax] minReg=1 spillAfter wt=300.00>
<RefPosition #67 @129 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[rcx] minReg=1 last reload wt=300.00>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00}
Has No Critical Edges
Prior to Resolution
BB01
use: {V00}
def: {V01 V02 V04 V05}
in: {V00}
out: {}
Var=Reg beg of BB01: V00=rcx
Var=Reg end of BB01: none
RESOLVING EDGES
Set V00 argument initial register to rcx
Trees after linear scan register allocator (LSRA)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
N003 (???,???) [000073] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t0 byref
N007 ( 2, 2) [000062] -c--------- t62 = * LEA(b+4) byref REG NA
/--* t62 byref
N009 ( 4, 4) [000002] -c-XG------ t2 = * IND int REG NA <l:$281, c:$280>
/--* t2 int
N011 ( 5, 6) [000003] ---XG----U- t3 = * CAST long <- ulong <- uint REG rax <l:$2c1, c:$2c3>
N013 ( 1, 1) [000004] -c--------- t4 = CNS_INT int 32 REG NA $44
/--* t3 long
+--* t4 int
N015 ( 7, 8) [000005] ---XG------ t5 = * LSH long REG rax <l:$2c7, c:$2c6>
N017 ( 1, 1) [000006] ----------- t6 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t6 byref
N019 ( 2, 2) [000064] -c--------- t64 = * LEA(b+12) byref REG NA
/--* t64 byref
N021 ( 4, 4) [000008] nc--GO----- t8 = * IND int REG NA <l:$283, c:$282>
/--* t8 int
N023 ( 5, 6) [000009] ----GO---U- t9 = * CAST long <- ulong <- uint REG r8 <l:$2c9, c:$2cb>
/--* t5 long
+--* t9 long
N025 ( 13, 15) [000010] ---XGO----- t10 = * ADD long REG rax <l:$2cf, c:$2ce>
/--* t10 long
N027 ( 13, 15) [000011] DA-XGO----# * STORE_LCL_VAR long V04 tmp1 d:1 rax REG rax $241
N029 ( 1, 1) [000013] ----------Z t13 = LCL_VAR long V04 tmp1 u:1 rax REG rax <l:$2cc, c:$2cd>
N031 ( 1, 4) [000015] -------N--- t15 = CNS_INT long 0x44b82fa09b5a53 REG rdx $103
N033 (???,???) [000074] -c--------- t74 = CNS_INT int 9 REG NA
/--* t13 long
+--* t74 int
N035 (???,???) [000075] ----------- t75 = * RSZ long REG rax
/--* t75 long
+--* t15 long
N037 (???,???) [000076] ---------U- t76 = * MULHI long REG rax
N039 (???,???) [000077] -c--------- t77 = CNS_INT int 11 REG NA
/--* t76 long
+--* t77 int
N041 ( 22, 8) [000016] ----------- t16 = * RSZ long REG rax
/--* t16 long
N043 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 rax REG rax $VN.Void
N045 ( 1, 1) [000019] -----+----- t19 = LCL_VAR long V01 loc0 u:1 rax REG rax <l:$2d0, c:$2d1>
N047 ( 1, 1) [000020] -c---+----- t20 = CNS_INT int 32 REG NA $44
/--* t19 long
+--* t20 int
N049 ( 3, 3) [000021] -----+----- t21 = * RSZ long REG rdx <l:$2d2, c:$2d3>
/--* t21 long
N051 ( 4, 5) [000022] -----+----- t22 = * CAST int <- uint <- long REG rdx <l:$284, c:$285>
N053 ( 1, 1) [000018] -----+----- t18 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t18 byref
N055 ( 2, 2) [000066] -c---+----- t66 = * LEA(b+4) byref REG NA
/--* t66 byref
+--* t22 int
N057 ( 9, 10) [000024] nA--G+----- * STOREIND int REG NA $VN.Void
N059 ( 1, 1) [000025] -----+----- t25 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t25 byref
N061 ( 2, 2) [000068] -c---+----- t68 = * LEA(b+12) byref REG NA
N063 ( 1, 1) [000026] -----+----- t26 = LCL_VAR int V01 loc0 u:1 rax REG rax <l:$286, c:$287>
/--* t68 byref
+--* t26 int
N065 ( 6, 6) [000029] nA--G+----- * STOREIND int REG NA $VN.Void
N067 ( 1, 1) [000012] -----+----z t12 = LCL_VAR long V04 tmp1 u:1 r8 (last use) REG r8 <l:$2cc, c:$2cd>
N069 ( 1, 1) [000030] -----+----- t30 = LCL_VAR int V01 loc0 u:1 rax (last use) REG rax <l:$286, c:$287>
N071 ( 1, 4) [000032] -c---+----- t32 = CNS_INT int 0x3B9ACA00 REG NA $47
/--* t30 int
+--* t32 int
N073 ( 6, 8) [000033] -----+----- t33 = * MUL int REG rax <l:$288, c:$289>
/--* t33 int
N075 ( 7, 10) [000034] -----+---U- t34 = * CAST long <- ulong <- uint REG rax <l:$2d4, c:$2d5>
/--* t12 long
+--* t34 long
N077 ( 9, 12) [000035] -----+----- t35 = * SUB long REG r8 <l:$2d6, c:$2d7>
N079 ( 1, 1) [000036] -c---+----- t36 = CNS_INT int 32 REG NA $44
/--* t35 long
+--* t36 int
N081 ( 11, 14) [000037] -----+----- t37 = * LSH long REG r8 <l:$2d8, c:$2d9>
N083 ( 1, 1) [000038] -----+----- t38 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t38 byref
N085 ( 2, 2) [000070] -c---+----- t70 = * LEA(b+8) byref REG NA
/--* t70 byref
N087 ( 4, 4) [000040] nc--G+----- t40 = * IND int REG NA <l:$182, c:$1c2>
/--* t40 int
N089 ( 5, 6) [000041] ----G+---U- t41 = * CAST long <- ulong <- uint REG rax <l:$2da, c:$2db>
/--* t37 long
+--* t41 long
N091 ( 17, 21) [000042] ----G+----- t42 = * ADD long REG rax <l:$2dc, c:$2dd>
/--* t42 long
N093 ( 17, 21) [000043] DA--G+----# * STORE_LCL_VAR long V05 tmp2 d:1 rax REG rax $VN.Void
N095 ( 1, 1) [000045] ----------Z t45 = LCL_VAR long V05 tmp2 u:1 rax REG rax <l:$2dc, c:$2dd>
N097 ( 1, 4) [000047] -------N--- t47 = CNS_INT long 0x44b82fa09b5a53 REG rdx $103
N099 (???,???) [000078] -c--------- t78 = CNS_INT int 9 REG NA
/--* t45 long
+--* t78 int
N101 (???,???) [000079] ----------- t79 = * RSZ long REG rax
/--* t79 long
+--* t47 long
N103 (???,???) [000080] ---------U- t80 = * MULHI long REG rax
N105 (???,???) [000081] -c--------- t81 = CNS_INT int 11 REG NA
/--* t80 long
+--* t81 int
N107 ( 22, 8) [000048] ----------- t48 = * RSZ long REG rax
/--* t48 long
N109 ( 23, 10) [000049] ----------- t49 = * CAST int <- uint <- long REG rax <l:$28a, c:$28b>
/--* t49 int
N111 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 rax REG rax $VN.Void
N113 ( 1, 1) [000051] -----+----- t51 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80
/--* t51 byref
N115 ( 2, 2) [000072] -c---+----- t72 = * LEA(b+8) byref REG NA
N117 ( 1, 1) [000052] -----+----- t52 = LCL_VAR int V02 loc1 u:1 rax REG rax <l:$28a, c:$28b>
/--* t72 byref
+--* t52 int
N119 ( 6, 6) [000054] nA--G+----- * STOREIND int REG NA $VN.Void
N121 ( 1, 1) [000044] -----+----z t44 = LCL_VAR int V05 tmp2 u:1 rcx (last use) REG rcx <l:$28c, c:$28d>
N123 ( 1, 1) [000056] -----+----- t56 = LCL_VAR int V02 loc1 u:1 rax (last use) REG rax <l:$28a, c:$28b>
N125 ( 1, 4) [000057] -c---+----- t57 = CNS_INT int 0x3B9ACA00 REG NA $47
/--* t56 int
+--* t57 int
N127 ( 6, 8) [000058] -----+----- t58 = * MUL int REG rax <l:$28e, c:$28f>
/--* t44 int
+--* t58 int
N129 ( 8, 10) [000059] -----+----- t59 = * SUB int REG rcx <l:$290, c:$291>
/--* t59 int
[000082] ----------- t82 = * COPY int REG rax
/--* t82 int
N131 ( 9, 11) [000060] -----+----- * RETURN int REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
Final allocation
-------------------------------------------+----+----+----+----+----+----+----+----+----+
TreeID Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
-------------------------------------------+----+----+----+----+----+----+----+----+----+
0.#0 V00 Parm Alloc rcx | |V00a| | | | | | | |
1.#1 BB1 PredBB0 | |V00a| | | | | | | |
[000003] 11.#2 V00 Use Keep rcx | |V00a| | | | | | | |
12.#3 I5 Def Alloc rax |I5 a|V00a| | | | | | | |
[000005] 15.#4 I5 Use * Keep rax |I5 i|V00a| | | | | | | |
16.#5 I6 Def Alloc rax |I6 a|V00a| | | | | | | |
[000009] 23.#6 V00 Use Keep rcx |I6 a|V00a| | | | | | | |
24.#7 I7 Def Alloc r8 |I6 a|V00a| | | | | |I7 a| |
[000010] 25.#8 I6 Use * Keep rax |I6 i|V00a| | | | | |I7 a| |
25.#9 I7 Use * Keep r8 | |V00a| | | | | |I7 i| |
26.#10 I8 Def Alloc rax |I8 a|V00a| | | | | | | |
[000011] 27.#11 I8 Use * Keep rax |I8 i|V00a| | | | | | | |
28.#12 V04 Def Alloc rax |V04a|V00a| | | | | | | |
[000015] 32.#13 C9 Def Alloc rdx |V04a|V00a|C9 a| | | | | | |
[000075] 35.#14 V04 Use Keep rax |V04i|V00a|C9 a| | | | | | |
Spill rax |V04i|V00a|C9 a| | | | | | |
36.#15 rax Fixd Keep rax | |V00a|C9 a| | | | | | |
36.#16 I10 Def Alloc rax |I10a|V00a|C9 a| | | | | | |
[000076] 37.#17 I10 Use * Keep rax |I10i|V00a|C9 a| | | | | | |
37.#18 C9 Use * Keep rdx | |V00a|C9 i| | | | | | |
38.#19 Kill None [rdx]
| |V00a| | | | | | | |
38.#20 I11 Def Alloc rax |I11a|V00a| | | | | | | |
[000016] 41.#21 I11 Use * Keep rax |I11i|V00a| | | | | | | |
42.#22 I12 Def Alloc rax |I12a|V00a| | | | | | | |
[000017] 43.#23 I12 Use * Keep rax |I12i|V00a| | | | | | | |
44.#24 V01 Def Alloc rax |V01a|V00a| | | | | | | |
[000021] 49.#25 V01 Use Keep rax |V01a|V00a| | | | | | | |
50.#26 I13 Def Alloc rdx |V01a|V00a|I13a| | | | | | |
[000022] 51.#27 I13 Use * Keep rdx |V01a|V00a|I13i| | | | | | |
52.#28 I14 Def Alloc rdx |V01a|V00a|I14a| | | | | | |
[000024] 57.#29 V00 Use Keep rcx |V01a|V00a|I14a| | | | | | |
57.#30 I14 Use * Keep rdx |V01a|V00a|I14i| | | | | | |
[000029] 65.#31 V00 Use Keep rcx |V01a|V00a| | | | | | | |
65.#32 V01 Use Keep rax |V01a|V00a| | | | | | | |
[000033] 73.#33 V01 Use * Keep rax |V01i|V00a| | | | | | | |
74.#34 I15 Def Alloc rax |I15a|V00a| | | | | | | |
[000034] 75.#35 I15 Use * Keep rax |I15i|V00a| | | | | | | |
76.#36 I16 Def Alloc rax |I16a|V00a| | | | | | | |
[000035] 77.#37 V04 Use * ReLod r8 |I16a|V00a| | | | | |V04a| |
Keep r8 |I16a|V00a| | | | | |V04i| |
77.#38 I16 Use *D Keep rax |I16i|V00a| | | | | | | |
78.#39 I17 Def Alloc r8 | |V00a| | | | | |I17a| |
[000037] 81.#40 I17 Use * Keep r8 | |V00a| | | | | |I17i| |
82.#41 I18 Def Alloc r8 | |V00a| | | | | |I18a| |
[000041] 89.#42 V00 Use Keep rcx | |V00a| | | | | |I18a| |
90.#43 I19 Def Alloc rax |I19a|V00a| | | | | |I18a| |
[000042] 91.#44 I18 Use * Keep r8 |I19a|V00a| | | | | |I18i| |
91.#45 I19 Use * Keep rax |I19i|V00a| | | | | | | |
92.#46 I20 Def Alloc rax |I20a|V00a| | | | | | | |
[000043] 93.#47 I20 Use * Keep rax |I20i|V00a| | | | | | | |
94.#48 V05 Def Alloc rax |V05a|V00a| | | | | | | |
[000047] 98.#49 C21 Def Alloc rdx |V05a|V00a|C21a| | | | | | |
[000079] 101.#50 V05 Use Keep rax |V05i|V00a|C21a| | | | | | |
Spill rax |V05i|V00a|C21a| | | | | | |
102.#51 rax Fixd Keep rax | |V00a|C21a| | | | | | |
102.#52 I22 Def Alloc rax |I22a|V00a|C21a| | | | | | |
[000080] 103.#53 I22 Use * Keep rax |I22i|V00a|C21a| | | | | | |
103.#54 C21 Use * Keep rdx | |V00a|C21i| | | | | | |
104.#55 Kill None [rdx]
| |V00a| | | | | | | |
104.#56 I23 Def Alloc rax |I23a|V00a| | | | | | | |
[000048] 107.#57 I23 Use * Keep rax |I23i|V00a| | | | | | | |
108.#58 I24 Def Alloc rax |I24a|V00a| | | | | | | |
[000049] 109.#59 I24 Use * Keep rax |I24i|V00a| | | | | | | |
110.#60 I25 Def Alloc rax |I25a|V00a| | | | | | | |
[000050] 111.#61 I25 Use * Keep rax |I25i|V00a| | | | | | | |
112.#62 V02 Def Alloc rax |V02a|V00a| | | | | | | |
[000054] 119.#63 V00 Use * Keep rcx |V02a|V00i| | | | | | | |
119.#64 V02 Use Keep rax |V02a| | | | | | | | |
[000058] 127.#65 V02 Use * Keep rax |V02i| | | | | | | | |
128.#66 I26 Def Alloc rax |I26a| | | | | | | | |
[000059] 129.#67 V05 Use * ReLod rcx |I26a|V05a| | | | | | | |
Keep rcx |I26a|V05i| | | | | | | |
129.#68 I26 Use *D Keep rax |I26i| | | | | | | | |
130.#69 I27 Def Alloc rcx | |I27a| | | | | | | |
[000060] 131.#70 rax Fixd Keep rax | |I27a| | | | | | | |
Move rax |I27i| | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars: 5
Total Reg Cand Vars: 5
Total number of Intervals: 27
Total number of RefPositions: 71
Total Number of spill temps created: 0
..........
BB01 [ 100.00]: SpillCount = 2, CopyReg = 1, COVERS = 12, COVERS_RELATED = 2, RELATED_PREFERENCE = 2, BEST_FIT = 8, REG_ORDER = 3
..........
Total SpillCount : 2 Weighted: 200.000000
Total CopyReg : 1 Weighted: 100.000000
Total ResolutionMovs : 0 Weighted: 0.000000
Total SplitEdges : 0 Weighted: 0.000000
..........
Total COVERS [# 4] : 12 Weighted: 1200.000000
Total COVERS_RELATED [# 6] : 2 Weighted: 200.000000
Total RELATED_PREFERENCE [# 7] : 2 Weighted: 200.000000
Total BEST_FIT [#11] : 8 Weighted: 800.000000
Total REG_ORDER [#13] : 3 Weighted: 300.000000
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(rcx)
BB01 [0000] [000..05E) (return), preds={} succs={}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V00(rcx)
N007. STK = LEA(b+4) ; rcx
N009. STK = IND ; STK
N011. rax = CAST ; STK
N013. CNS_INT 32
N015. rax = LSH ; rax
N017. V00(rcx)
N019. STK = LEA(b+12); rcx
N021. STK = IND ; STK
N023. r8 = CAST ; STK
N025. rax = ADD ; rax,r8
$ N027. V04(rax)R; rax
S N029. V04(rax)
N031. rdx = CNS_INT 0x44b82fa09b5a53
N033. CNS_INT 9
N035. rax = RSZ ; rax
N037. rax = MULHI ; rax,rdx
N039. CNS_INT 11
N041. rax = RSZ ; rax
* N043. V01(rax); rax
N045. V01(rax)
N047. CNS_INT 32
N049. rdx = RSZ ; rax
N051. rdx = CAST ; rdx
N053. V00(rcx)
N055. STK = LEA(b+4) ; rcx
N057. STOREIND ; STK,rdx
N059. V00(rcx)
N061. STK = LEA(b+12); rcx
N063. V01(rax)
N065. STOREIND ; STK,rax
N067. V04(r8*)R
N069. V01(rax*)
N071. CNS_INT 0x3B9ACA00
N073. rax = MUL ; rax*
N075. rax = CAST ; rax
N077. r8 = SUB ; r8*,rax
N079. CNS_INT 32
N081. r8 = LSH ; r8
N083. V00(rcx)
N085. STK = LEA(b+8) ; rcx
N087. STK = IND ; STK
N089. rax = CAST ; STK
N091. rax = ADD ; r8,rax
$ N093. V05(rax)R; rax
S N095. V05(rax)
N097. rdx = CNS_INT 0x44b82fa09b5a53
N099. CNS_INT 9
N101. rax = RSZ ; rax
N103. rax = MULHI ; rax,rdx
N105. CNS_INT 11
N107. rax = RSZ ; rax
N109. rax = CAST ; rax
* N111. V02(rax); rax
N113. V00(rcx*)
N115. STK = LEA(b+8) ; rcx*
N117. V02(rax)
N119. STOREIND ; STK,rax
N121. V05(rcx*)R
N123. V02(rax*)
N125. CNS_INT 0x3B9ACA00
N127. rax = MUL ; rax*
N129. rcx = SUB ; rcx*,rax
N000. rax = COPY ; rcx
N131. RETURN ; rax
Var=Reg end of BB01: none
*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..05E) (return), preds={} succs={}
N003 (???,???) [000073] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t0 byref
N007 ( 2, 2) [000062] -c--------- t62 = * LEA(b+4) byref REG NA
/--* t62 byref
N009 ( 4, 4) [000002] -c-XG------ t2 = * IND int REG NA <l:$281, c:$280>
/--* t2 int
N011 ( 5, 6) [000003] ---XG----U- t3 = * CAST long <- ulong <- uint REG rax <l:$2c1, c:$2c3>
N013 ( 1, 1) [000004] -c--------- t4 = CNS_INT int 32 REG NA $44
/--* t3 long
+--* t4 int
N015 ( 7, 8) [000005] ---XG------ t5 = * LSH long REG rax <l:$2c7, c:$2c6>
N017 ( 1, 1) [000006] ----------- t6 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t6 byref
N019 ( 2, 2) [000064] -c--------- t64 = * LEA(b+12) byref REG NA
/--* t64 byref
N021 ( 4, 4) [000008] nc--GO----- t8 = * IND int REG NA <l:$283, c:$282>
/--* t8 int
N023 ( 5, 6) [000009] ----GO---U- t9 = * CAST long <- ulong <- uint REG r8 <l:$2c9, c:$2cb>
/--* t5 long
+--* t9 long
N025 ( 13, 15) [000010] ---XGO----- t10 = * ADD long REG rax <l:$2cf, c:$2ce>
/--* t10 long
N027 ( 13, 15) [000011] DA-XGO----# * STORE_LCL_VAR long V04 tmp1 d:1 rax REG rax $241
N029 ( 1, 1) [000013] ----------Z t13 = LCL_VAR long V04 tmp1 u:1 rax REG rax <l:$2cc, c:$2cd>
N031 ( 1, 4) [000015] -------N--- t15 = CNS_INT long 0x44b82fa09b5a53 REG rdx $103
N033 (???,???) [000074] -c--------- t74 = CNS_INT int 9 REG NA
/--* t13 long
+--* t74 int
N035 (???,???) [000075] ----------- t75 = * RSZ long REG rax
/--* t75 long
+--* t15 long
N037 (???,???) [000076] ---------U- t76 = * MULHI long REG rax
N039 (???,???) [000077] -c--------- t77 = CNS_INT int 11 REG NA
/--* t76 long
+--* t77 int
N041 ( 22, 8) [000016] ----------- t16 = * RSZ long REG rax
/--* t16 long
N043 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 rax REG rax $VN.Void
N045 ( 1, 1) [000019] -----+----- t19 = LCL_VAR long V01 loc0 u:1 rax REG rax <l:$2d0, c:$2d1>
N047 ( 1, 1) [000020] -c---+----- t20 = CNS_INT int 32 REG NA $44
/--* t19 long
+--* t20 int
N049 ( 3, 3) [000021] -----+----- t21 = * RSZ long REG rdx <l:$2d2, c:$2d3>
/--* t21 long
N051 ( 4, 5) [000022] -----+----- t22 = * CAST int <- uint <- long REG rdx <l:$284, c:$285>
N053 ( 1, 1) [000018] -----+----- t18 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t18 byref
N055 ( 2, 2) [000066] -c---+----- t66 = * LEA(b+4) byref REG NA
/--* t66 byref
+--* t22 int
N057 ( 9, 10) [000024] nA--G+----- * STOREIND int REG NA $VN.Void
N059 ( 1, 1) [000025] -----+----- t25 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t25 byref
N061 ( 2, 2) [000068] -c---+----- t68 = * LEA(b+12) byref REG NA
N063 ( 1, 1) [000026] -----+----- t26 = LCL_VAR int V01 loc0 u:1 rax REG rax <l:$286, c:$287>
/--* t68 byref
+--* t26 int
N065 ( 6, 6) [000029] nA--G+----- * STOREIND int REG NA $VN.Void
N067 ( 1, 1) [000012] -----+----z t12 = LCL_VAR long V04 tmp1 u:1 r8 (last use) REG r8 <l:$2cc, c:$2cd>
N069 ( 1, 1) [000030] -----+----- t30 = LCL_VAR int V01 loc0 u:1 rax (last use) REG rax <l:$286, c:$287>
N071 ( 1, 4) [000032] -c---+----- t32 = CNS_INT int 0x3B9ACA00 REG NA $47
/--* t30 int
+--* t32 int
N073 ( 6, 8) [000033] -----+----- t33 = * MUL int REG rax <l:$288, c:$289>
/--* t33 int
N075 ( 7, 10) [000034] -----+---U- t34 = * CAST long <- ulong <- uint REG rax <l:$2d4, c:$2d5>
/--* t12 long
+--* t34 long
N077 ( 9, 12) [000035] -----+----- t35 = * SUB long REG r8 <l:$2d6, c:$2d7>
N079 ( 1, 1) [000036] -c---+----- t36 = CNS_INT int 32 REG NA $44
/--* t35 long
+--* t36 int
N081 ( 11, 14) [000037] -----+----- t37 = * LSH long REG r8 <l:$2d8, c:$2d9>
N083 ( 1, 1) [000038] -----+----- t38 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t38 byref
N085 ( 2, 2) [000070] -c---+----- t70 = * LEA(b+8) byref REG NA
/--* t70 byref
N087 ( 4, 4) [000040] nc--G+----- t40 = * IND int REG NA <l:$182, c:$1c2>
/--* t40 int
N089 ( 5, 6) [000041] ----G+---U- t41 = * CAST long <- ulong <- uint REG rax <l:$2da, c:$2db>
/--* t37 long
+--* t41 long
N091 ( 17, 21) [000042] ----G+----- t42 = * ADD long REG rax <l:$2dc, c:$2dd>
/--* t42 long
N093 ( 17, 21) [000043] DA--G+----# * STORE_LCL_VAR long V05 tmp2 d:1 rax REG rax $VN.Void
N095 ( 1, 1) [000045] ----------Z t45 = LCL_VAR long V05 tmp2 u:1 rax REG rax <l:$2dc, c:$2dd>
N097 ( 1, 4) [000047] -------N--- t47 = CNS_INT long 0x44b82fa09b5a53 REG rdx $103
N099 (???,???) [000078] -c--------- t78 = CNS_INT int 9 REG NA
/--* t45 long
+--* t78 int
N101 (???,???) [000079] ----------- t79 = * RSZ long REG rax
/--* t79 long
+--* t47 long
N103 (???,???) [000080] ---------U- t80 = * MULHI long REG rax
N105 (???,???) [000081] -c--------- t81 = CNS_INT int 11 REG NA
/--* t80 long
+--* t81 int
N107 ( 22, 8) [000048] ----------- t48 = * RSZ long REG rax
/--* t48 long
N109 ( 23, 10) [000049] ----------- t49 = * CAST int <- uint <- long REG rax <l:$28a, c:$28b>
/--* t49 int
N111 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 rax REG rax $VN.Void
N113 ( 1, 1) [000051] -----+----- t51 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80
/--* t51 byref
N115 ( 2, 2) [000072] -c---+----- t72 = * LEA(b+8) byref REG NA
N117 ( 1, 1) [000052] -----+----- t52 = LCL_VAR int V02 loc1 u:1 rax REG rax <l:$28a, c:$28b>
/--* t72 byref
+--* t52 int
N119 ( 6, 6) [000054] nA--G+----- * STOREIND int REG NA $VN.Void
N121 ( 1, 1) [000044] -----+----z t44 = LCL_VAR int V05 tmp2 u:1 rcx (last use) REG rcx <l:$28c, c:$28d>
N123 ( 1, 1) [000056] -----+----- t56 = LCL_VAR int V02 loc1 u:1 rax (last use) REG rax <l:$28a, c:$28b>
N125 ( 1, 4) [000057] -c---+----- t57 = CNS_INT int 0x3B9ACA00 REG NA $47
/--* t56 int
+--* t57 int
N127 ( 6, 8) [000058] -----+----- t58 = * MUL int REG rax <l:$28e, c:$28f>
/--* t44 int
+--* t58 int
N129 ( 8, 10) [000059] -----+----- t59 = * SUB int REG rcx <l:$290, c:$291>
/--* t59 int
[000082] ----------- t82 = * COPY int REG rax
/--* t82 int
N131 ( 9, 11) [000060] -----+----- * RETURN int REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Optimize layout
*************** In fgSearchImprovedLayout()
Initial BasicBlocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Not enough blocks to partition anything. Skipping reordering.
Reordering block list
*************** Finishing PHASE Optimize layout [no changes]
*************** Starting PHASE Optimize post-layout
*************** Finishing PHASE Optimize post-layout [no changes]
*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block [no changes]
*************** Starting PHASE Place 'align' instructions
*************** In placeLoopAlignInstructions()
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
Not checking for any loops as fgMightHaveNaturalLoops is false
*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(rcx)
Modified regs: [rax rcx rdx r8]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Set V00 to offset 0
Assign V04 tmp1, size=8, stkOffs=-0x10
Assign V05 tmp2, size=8, stkOffs=-0x18
--- delta bump 8 for RA
--- delta bump 24 for RSP frame
--- virtual stack offset to actual stack offset delta is 32
-- V00 was 0, now 32
-- V03 was 0, now 32
-- V04 was -16, now 16
-- V05 was -24, now 8
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 8, 8 ) byref -> rcx single-def
; V01 loc0 [V01,T03] ( 4, 4 ) long -> rax
; V02 loc1 [V02,T04] ( 3, 3 ) int -> rax
;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
; V04 tmp1 [V04,T01] ( 3, 6 ) long -> [rsp+0x10] spill-single-def "dup spill"
; V05 tmp2 [V05,T02] ( 3, 6 ) long -> [rsp+0x08] spill-single-def "dup spill"
;
; Lcl frame size = 24
Created:
G_M15891_IG02: ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
BB01 : first block
*************** After genMarkLabelsForCodegen()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..05E) (return) i LIR label
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
=============== Generating BB01 [0000] [000..05E) (return), preds={} succs={} flags=0x00000000.00001011: i LIR label
BB01 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
Recording Var Locations at start of BB01
V00(rcx)
Change life 0000000000000000 {} -> 0000000000000001 {V00}
V00 in reg rcx is becoming live [------]
Live regs: 0000000000000000 {} + {rcx} => 0000000000000002 {rcx}
Debug: New V00 debug range: first
Live regs: (unchanged) 0000000000000002 {rcx}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0002 {rcx}
L_M15891_BB01:
Label: G_M15891_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}
Scope info: begin block BB01, IL range [000..05E)
Added IP mapping: 0x0000 STACK_EMPTY (G_M15891_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000073] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t0 byref
Generating: N007 ( 2, 2) [000062] -c--------- t62 = * LEA(b+4) byref REG NA
/--* t62 byref
Generating: N009 ( 4, 4) [000002] -c-XG------ t2 = * IND int REG NA <l:$281, c:$280>
/--* t2 int
Generating: N011 ( 5, 6) [000003] ---XG----U- t3 = * CAST long <- ulong <- uint REG rax <l:$2c1, c:$2c3>
Mapped BB01 to G_M15891_IG02
IN0001: mov eax, dword ptr [rcx+0x04]
Generating: N013 ( 1, 1) [000004] -c--------- t4 = CNS_INT int 32 REG NA $44
/--* t3 long
+--* t4 int
Generating: N015 ( 7, 8) [000005] ---XG------ t5 = * LSH long REG rax <l:$2c7, c:$2c6>
IN0002: shl rax, 32
Generating: N017 ( 1, 1) [000006] ----------- t6 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t6 byref
Generating: N019 ( 2, 2) [000064] -c--------- t64 = * LEA(b+12) byref REG NA
/--* t64 byref
Generating: N021 ( 4, 4) [000008] nc--GO----- t8 = * IND int REG NA <l:$283, c:$282>
/--* t8 int
Generating: N023 ( 5, 6) [000009] ----GO---U- t9 = * CAST long <- ulong <- uint REG r8 <l:$2c9, c:$2cb>
IN0003: mov r8d, dword ptr [rcx+0x0C]
/--* t5 long
+--* t9 long
Generating: N025 ( 13, 15) [000010] ---XGO----- t10 = * ADD long REG rax <l:$2cf, c:$2ce>
IN0004: add rax, r8
/--* t10 long
Generating: N027 ( 13, 15) [000011] DA-XGO----# * STORE_LCL_VAR long V04 tmp1 d:1 rax REG rax $241
IN0005: mov qword ptr [V04 rsp+0x10], rax
V04 in reg rax is becoming live [000011]
Live regs: 0000000000000002 {rcx} + {rax} => 0000000000000003 {rax rcx}
Live vars after [000011]: {V00} +{V04} => {V00 V04}
Generating: N029 ( 1, 1) [000013] ----------Z t13 = LCL_VAR long V04 tmp1 u:1 rax REG rax <l:$2cc, c:$2cd>
Generating: N031 ( 1, 4) [000015] -------N--- t15 = CNS_INT long 0x44b82fa09b5a53 REG rdx $103
IN0006: mov rdx, 0x44B82FA09B5A53
Generating: N033 (???,???) [000074] -c--------- t74 = CNS_INT int 9 REG NA
/--* t13 long
+--* t74 int
Generating: N035 (???,???) [000075] ----------- t75 = * RSZ long REG rax
V04 in reg rax is becoming dead [000013]
Live regs: 0000000000000003 {rax rcx} - {rax} => 0000000000000002 {rcx}
IN0007: shr rax, 9
/--* t75 long
+--* t15 long
Generating: N037 (???,???) [000076] ---------U- t76 = * MULHI long REG rax
IN0008: mulx rax, rax, rax
Generating: N039 (???,???) [000077] -c--------- t77 = CNS_INT int 11 REG NA
/--* t76 long
+--* t77 int
Generating: N041 ( 22, 8) [000016] ----------- t16 = * RSZ long REG rax
IN0009: shr rax, 11
/--* t16 long
Generating: N043 ( 22, 8) [000017] DA--------- * STORE_LCL_VAR long V01 loc0 d:1 rax REG rax $VN.Void
V01 in reg rax is becoming live [000017]
Live regs: 0000000000000002 {rcx} + {rax} => 0000000000000003 {rax rcx}
Debug: New V01 debug range: first
Live vars after [000017]: {V00 V04} +{V01} => {V00 V01 V04}
Generating: N045 ( 1, 1) [000019] -----+----- t19 = LCL_VAR long V01 loc0 u:1 rax REG rax <l:$2d0, c:$2d1>
Generating: N047 ( 1, 1) [000020] -c---+----- t20 = CNS_INT int 32 REG NA $44
/--* t19 long
+--* t20 int
Generating: N049 ( 3, 3) [000021] -----+----- t21 = * RSZ long REG rdx <l:$2d2, c:$2d3>
IN000a: mov rdx, rax
IN000b: shr rdx, 32
/--* t21 long
Generating: N051 ( 4, 5) [000022] -----+----- t22 = * CAST int <- uint <- long REG rdx <l:$284, c:$285>
Generating: N053 ( 1, 1) [000018] -----+----- t18 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t18 byref
Generating: N055 ( 2, 2) [000066] -c---+----- t66 = * LEA(b+4) byref REG NA
/--* t66 byref
+--* t22 int
Generating: N057 ( 9, 10) [000024] nA--G+----- * STOREIND int REG NA $VN.Void
IN000c: mov dword ptr [rcx+0x04], edx
Generating: N059 ( 1, 1) [000025] -----+----- t25 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t25 byref
Generating: N061 ( 2, 2) [000068] -c---+----- t68 = * LEA(b+12) byref REG NA
Generating: N063 ( 1, 1) [000026] -----+----- t26 = LCL_VAR int V01 loc0 u:1 rax REG rax <l:$286, c:$287>
/--* t68 byref
+--* t26 int
Generating: N065 ( 6, 6) [000029] nA--G+----- * STOREIND int REG NA $VN.Void
IN000d: mov dword ptr [rcx+0x0C], eax
Generating: N067 ( 1, 1) [000012] -----+----z t12 = LCL_VAR long V04 tmp1 u:1 r8 (last use) REG r8 <l:$2cc, c:$2cd>
Generating: N069 ( 1, 1) [000030] -----+----- t30 = LCL_VAR int V01 loc0 u:1 rax (last use) REG rax <l:$286, c:$287>
Generating: N071 ( 1, 4) [000032] -c---+----- t32 = CNS_INT int 0x3B9ACA00 REG NA $47
/--* t30 int
+--* t32 int
Generating: N073 ( 6, 8) [000033] -----+----- t33 = * MUL int REG rax <l:$288, c:$289>
V01 in reg rax is becoming dead [000030]
Live regs: 0000000000000003 {rax rcx} - {rax} => 0000000000000002 {rcx}
Debug: Closing V01 debug range.
Live vars after [000030]: {V00 V01 V04} -{V01} => {V00 V04}
IN000e: imul eax, eax, 0x3B9ACA00
/--* t33 int
Generating: N075 ( 7, 10) [000034] -----+---U- t34 = * CAST long <- ulong <- uint REG rax <l:$2d4, c:$2d5>
-- suppressing mov because upper bits are zero.
/--* t12 long
+--* t34 long
Generating: N077 ( 9, 12) [000035] -----+----- t35 = * SUB long REG r8 <l:$2d6, c:$2d7>
IN000f: mov r8, qword ptr [V04 rsp+0x10]
V04 in reg r8 is becoming live [000012]
Live regs: 0000000000000002 {rcx} + {r8} => 0000000000000102 {rcx r8}
V04 in reg r8 is becoming dead [000012]
Live regs: 0000000000000102 {rcx r8} - {r8} => 0000000000000002 {rcx}
Live vars after [000012]: {V00 V04} -{V04} => {V00}
IN0010: sub r8, rax
Generating: N079 ( 1, 1) [000036] -c---+----- t36 = CNS_INT int 32 REG NA $44
/--* t35 long
+--* t36 int
Generating: N081 ( 11, 14) [000037] -----+----- t37 = * LSH long REG r8 <l:$2d8, c:$2d9>
IN0011: shl r8, 32
Generating: N083 ( 1, 1) [000038] -----+----- t38 = LCL_VAR byref V00 arg0 u:1 rcx REG rcx $80
/--* t38 byref
Generating: N085 ( 2, 2) [000070] -c---+----- t70 = * LEA(b+8) byref REG NA
/--* t70 byref
Generating: N087 ( 4, 4) [000040] nc--G+----- t40 = * IND int REG NA <l:$182, c:$1c2>
/--* t40 int
Generating: N089 ( 5, 6) [000041] ----G+---U- t41 = * CAST long <- ulong <- uint REG rax <l:$2da, c:$2db>
IN0012: mov eax, dword ptr [rcx+0x08]
/--* t37 long
+--* t41 long
Generating: N091 ( 17, 21) [000042] ----G+----- t42 = * ADD long REG rax <l:$2dc, c:$2dd>
IN0013: add rax, r8
/--* t42 long
Generating: N093 ( 17, 21) [000043] DA--G+----# * STORE_LCL_VAR long V05 tmp2 d:1 rax REG rax $VN.Void
IN0014: mov qword ptr [V05 rsp+0x08], rax
V05 in reg rax is becoming live [000043]
Live regs: 0000000000000002 {rcx} + {rax} => 0000000000000003 {rax rcx}
Live vars after [000043]: {V00} +{V05} => {V00 V05}
Generating: N095 ( 1, 1) [000045] ----------Z t45 = LCL_VAR long V05 tmp2 u:1 rax REG rax <l:$2dc, c:$2dd>
Generating: N097 ( 1, 4) [000047] -------N--- t47 = CNS_INT long 0x44b82fa09b5a53 REG rdx $103
IN0015: mov rdx, 0x44B82FA09B5A53
Generating: N099 (???,???) [000078] -c--------- t78 = CNS_INT int 9 REG NA
/--* t45 long
+--* t78 int
Generating: N101 (???,???) [000079] ----------- t79 = * RSZ long REG rax
V05 in reg rax is becoming dead [000045]
Live regs: 0000000000000003 {rax rcx} - {rax} => 0000000000000002 {rcx}
IN0016: shr rax, 9
/--* t79 long
+--* t47 long
Generating: N103 (???,???) [000080] ---------U- t80 = * MULHI long REG rax
IN0017: mulx rax, rax, rax
Generating: N105 (???,???) [000081] -c--------- t81 = CNS_INT int 11 REG NA
/--* t80 long
+--* t81 int
Generating: N107 ( 22, 8) [000048] ----------- t48 = * RSZ long REG rax
IN0018: shr rax, 11
/--* t48 long
Generating: N109 ( 23, 10) [000049] ----------- t49 = * CAST int <- uint <- long REG rax <l:$28a, c:$28b>
/--* t49 int
Generating: N111 ( 23, 10) [000050] DA--------- * STORE_LCL_VAR int V02 loc1 d:1 rax REG rax $VN.Void
V02 in reg rax is becoming live [000050]
Live regs: 0000000000000002 {rcx} + {rax} => 0000000000000003 {rax rcx}
Debug: New V02 debug range: first
Live vars after [000050]: {V00 V05} +{V02} => {V00 V02 V05}
Generating: N113 ( 1, 1) [000051] -----+----- t51 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80
/--* t51 byref
Generating: N115 ( 2, 2) [000072] -c---+----- t72 = * LEA(b+8) byref REG NA
Generating: N117 ( 1, 1) [000052] -----+----- t52 = LCL_VAR int V02 loc1 u:1 rax REG rax <l:$28a, c:$28b>
/--* t72 byref
+--* t52 int
Generating: N119 ( 6, 6) [000054] nA--G+----- * STOREIND int REG NA $VN.Void
V00 in reg rcx is becoming dead [000051]
Live regs: 0000000000000003 {rax rcx} - {rcx} => 0000000000000001 {rax}
Debug: Closing V00 debug range.
Live vars after [000051]: {V00 V02 V05} -{V00} => {V02 V05}
Byref regs: 0002 {rcx} => 0000 {}
IN0019: mov dword ptr [rcx+0x08], eax
Generating: N121 ( 1, 1) [000044] -----+----z t44 = LCL_VAR int V05 tmp2 u:1 rcx (last use) REG rcx <l:$28c, c:$28d>
Generating: N123 ( 1, 1) [000056] -----+----- t56 = LCL_VAR int V02 loc1 u:1 rax (last use) REG rax <l:$28a, c:$28b>
Generating: N125 ( 1, 4) [000057] -c---+----- t57 = CNS_INT int 0x3B9ACA00 REG NA $47
/--* t56 int
+--* t57 int
Generating: N127 ( 6, 8) [000058] -----+----- t58 = * MUL int REG rax <l:$28e, c:$28f>
V02 in reg rax is becoming dead [000056]
Live regs: 0000000000000001 {rax} - {rax} => 0000000000000000 {}
Debug: Closing V02 debug range.
Live vars after [000056]: {V02 V05} -{V02} => {V05}
IN001a: imul eax, eax, 0x3B9ACA00
/--* t44 int
+--* t58 int
Generating: N129 ( 8, 10) [000059] -----+----- t59 = * SUB int REG rcx <l:$290, c:$291>
IN001b: mov rcx, qword ptr [V05 rsp+0x08]
V05 in reg rcx is becoming live [000044]
Live regs: 0000000000000000 {} + {rcx} => 0000000000000002 {rcx}
V05 in reg rcx is becoming dead [000044]
Live regs: 0000000000000002 {rcx} - {rcx} => 0000000000000000 {}
Live vars after [000044]: {V05} -{V05} => {}
IN001c: sub ecx, eax
/--* t59 int
Generating: [000082] ----------- t82 = * COPY int REG rax
/--* t82 int
Generating: N131 ( 9, 11) [000060] -----+----- * RETURN int REG NA $VN.Void
IN001d: mov eax, ecx
Added IP mapping: EPILOG (G_M15891_IG02,ins#29,ofs#125) label
Reserving epilog IG for block BB01
Saved:
G_M15891_IG02: ; offs=0x000000, size=0x007D, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], byref
Created:
G_M15891_IG03: ; offs=0x00007D, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
*************** After placeholder IG creation
G_M15891_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M15891_IG02: ; offs=0x000000, size=0x007D, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], byref
G_M15891_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0002 {rcx}
Variable Live Range History Dump for BB01
V00 arg0: rcx [(G_M15891_IG02,ins#0,ofs#0), (G_M15891_IG02,ins#24,ofs#107)]
V01 loc0: rax [(G_M15891_IG02,ins#9,ofs#42), (G_M15891_IG02,ins#13,ofs#55)]
V02 loc1: rax [(G_M15891_IG02,ins#24,ofs#107), (G_M15891_IG02,ins#25,ofs#110)]
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 105, compSizeEstimate = 87 Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 8, 8 ) byref -> rcx single-def
; V01 loc0 [V01,T03] ( 4, 4 ) long -> rax
; V02 loc1 [V02,T04] ( 3, 3 ) int -> rax
;# V03 OutArgs [V03 ] ( 1, 1 ) struct ( 0) [rsp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
; V04 tmp1 [V04,T01] ( 3, 6 ) long -> [rsp+0x10] spill-single-def "dup spill"
; V05 tmp2 [V05,T02] ( 3, 6 ) long -> [rsp+0x08] spill-single-def "dup spill"
;
; Lcl frame size = 24
*************** Before prolog / epilog generation
G_M15891_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M15891_IG02: ; offs=0x000000, size=0x007D, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], byref
G_M15891_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0002 {rcx}
Recording Var Locations at start of BB01
V00(rcx)
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M15891_IG01,ins#0,ofs#0) label
__prolog:
Debug: New V00 debug range: first
IN001e: sub rsp, 24
*************** In genHomeRegisterParams()
1 registers in register parameter interference graph
rcx
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.
Saved:
G_M15891_IG01: ; offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0002 {rcx}
IN001f: add rsp, 24
IN0020: ret
Saved:
G_M15891_IG03: ; offs=0x00007D, size=0x0005, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M15891_IG01: ; func=00, offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M15891_IG02: ; offs=0x000004, size=0x007D, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], byref
G_M15891_IG03: ; offs=0x000081, size=0x0005, bbWeight=1, epilog, nogc, extend
*************** In emitJumpDistBind()
Emitter Jump List:
total jump count: 0
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x86 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x6)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M15891_IG01: ; offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN001e: 000000 sub rsp, 24
;; size=4 bbWeight=1 PerfScore 0.25
G_M15891_IG02: ; offs=0x000004, size=0x007D, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], byref
; byrRegs +[rcx]
IN0001: 000004 mov eax, dword ptr [rcx+0x04]
IN0002: 000007 shl rax, 32
IN0003: 00000B mov r8d, dword ptr [rcx+0x0C]
IN0004: 00000F add rax, r8
IN0005: 000012 mov qword ptr [rsp+0x10], rax
IN0006: 000017 mov rdx, 0x44B82FA09B5A53
IN0007: 000021 shr rax, 9
IN0008: 000025 mulx rax, rax, rax
IN0009: 00002A shr rax, 11
IN000a: 00002E mov rdx, rax
IN000b: 000031 shr rdx, 32
IN000c: 000035 mov dword ptr [rcx+0x04], edx
IN000d: 000038 mov dword ptr [rcx+0x0C], eax
IN000e: 00003B imul eax, eax, 0x3B9ACA00
IN000f: 000041 mov r8, qword ptr [rsp+0x10]
IN0010: 000046 sub r8, rax
IN0011: 000049 shl r8, 32
IN0012: 00004D mov eax, dword ptr [rcx+0x08]
IN0013: 000050 add rax, r8
IN0014: 000053 mov qword ptr [rsp+0x08], rax
IN0015: 000058 mov rdx, 0x44B82FA09B5A53
IN0016: 000062 shr rax, 9
IN0017: 000066 mulx rax, rax, rax
IN0018: 00006B shr rax, 11
IN0019: 00006F mov dword ptr [rcx+0x08], eax
IN001a: 000072 imul eax, eax, 0x3B9ACA00
IN001b: 000078 mov rcx, qword ptr [rsp+0x08]
; byrRegs -[rcx]
IN001c: 00007D sub ecx, eax
IN001d: 00007F mov eax, ecx
;; size=125 bbWeight=1 PerfScore 28.50
G_M15891_IG03: ; offs=0x000081, size=0x0005, bbWeight=1, epilog, nogc, extend
IN001f: 000081 add rsp, 24
IN0020: 000085 ret
;; size=5 bbWeight=1 PerfScore 1.25
Allocated method code size = 134 , actual size = 134, unused size = 0
; Total bytes of code 134, prolog size 4, PerfScore 30.00, instruction count 32, allocated bytes for code 134 (MethodHash=5d76c1ec) for method Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint (FullOpts)
; ============================================================
*************** After end code gen, before unwindEmit()
G_M15891_IG01: ; func=00, offs=0x000000, size=0x0004, bbWeight=1, PerfScore 0.25, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN001e: 000000 sub rsp, 24
G_M15891_IG02: ; offs=0x000004, size=0x007D, bbWeight=1, PerfScore 28.50, gcrefRegs=0000 {}, byrefRegs=0002 {rcx}, BB01 [0000], byref
IN0001: 000004 mov eax, dword ptr [rcx+0x04]
IN0002: 000007 shl rax, 32
IN0003: 00000B mov r8d, dword ptr [rcx+0x0C]
IN0004: 00000F add rax, r8
IN0005: 000012 mov qword ptr [V04 rsp+0x10], rax
IN0006: 000017 mov rdx, 0x44B82FA09B5A53
IN0007: 000021 shr rax, 9
IN0008: 000025 mulx rax, rax, rax
IN0009: 00002A shr rax, 11
IN000a: 00002E mov rdx, rax
IN000b: 000031 shr rdx, 32
IN000c: 000035 mov dword ptr [rcx+0x04], edx
IN000d: 000038 mov dword ptr [rcx+0x0C], eax
IN000e: 00003B imul eax, eax, 0x3B9ACA00
IN000f: 000041 mov r8, qword ptr [V04 rsp+0x10]
IN0010: 000046 sub r8, rax
IN0011: 000049 shl r8, 32
IN0012: 00004D mov eax, dword ptr [rcx+0x08]
IN0013: 000050 add rax, r8
IN0014: 000053 mov qword ptr [V05 rsp+0x08], rax
IN0015: 000058 mov rdx, 0x44B82FA09B5A53
IN0016: 000062 shr rax, 9
IN0017: 000066 mulx rax, rax, rax
IN0018: 00006B shr rax, 11
IN0019: 00006F mov dword ptr [rcx+0x08], eax
IN001a: 000072 imul eax, eax, 0x3B9ACA00
IN001b: 000078 mov rcx, qword ptr [V05 rsp+0x08]
IN001c: 00007D sub ecx, eax
IN001d: 00007F mov eax, ecx
G_M15891_IG03: ; offs=0x000081, size=0x0005, bbWeight=1, PerfScore 1.25, epilog, nogc, extend
IN001f: 000081 add rsp, 24
IN0020: 000085 ret
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x000086 (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x04
CountOfUnwindCodes: 1
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x04 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 2 * 8 + 8 = 24 = 0x18
allocUnwindInfo(pHotCode=0x00007FFA0FED5210, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x86, unwindSize=0x6, pUnwindBlock=0x000001238017767A, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 3
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000004 ( STACK_EMPTY )
IL offs EPILOG : 0x00000081 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 4
; Variable debug info: 3 live ranges, 3 vars for method Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint
(V00 arg0) : From 00000000h to 0000006Fh, in rcx
(V01 loc0) : From 0000002Eh to 0000003Bh, in rax
(V02 loc1) : From 0000006Fh to 00000072h, in rax
*************** In gcInfoBlockHdrSave()
Set code length to 134.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:
*************** Finishing PHASE Emit GC+EH tables
Method code size: 134
Allocations for Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint (MethodHash=5d76c1ec)
count: 1074, size: 100128, max = 7568
allocateMemory: 131072, nraUsed: 104136
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
ABI | 152 | 0.15%
AssertionProp | 6644 | 6.64%
ASTNode | 11992 | 11.98%
InstDesc | 4288 | 4.28%
ImpStack | 384 | 0.38%
BasicBlock | 864 | 0.86%
CallArgs | 0 | 0.00%
FlowEdge | 0 | 0.00%
DepthFirstSearch | 256 | 0.26%
Loops | 260 | 0.26%
TreeStatementList | 0 | 0.00%
SiScope | 0 | 0.00%
DominatorMemory | 128 | 0.13%
LSRA | 9168 | 9.16%
LSRA_Interval | 2688 | 2.68%
LSRA_RefPosition | 5760 | 5.75%
Reachability | 40 | 0.04%
SSA | 736 | 0.74%
ValueNumber | 13752 | 13.73%
LvaTable | 1584 | 1.58%
UnwindInfo | 0 | 0.00%
hashBv | 40 | 0.04%
bitset | 512 | 0.51%
FixedBitVect | 32 | 0.03%
Generic | 902 | 0.90%
LocalAddressVisitor | 448 | 0.45%
FieldSeqStore | 0 | 0.00%
MemorySsaMap | 40 | 0.04%
MemoryPhiArg | 0 | 0.00%
CSE | 3392 | 3.39%
GC | 1304 | 1.30%
CorTailCallInfo | 0 | 0.00%
Inlining | 472 | 0.47%
ArrayStack | 0 | 0.00%
DebugInfo | 264 | 0.26%
DebugOnly | 28927 | 28.89%
Codegen | 2752 | 2.75%
LoopOpt | 0 | 0.00%
LoopClone | 0 | 0.00%
LoopUnroll | 0 | 0.00%
LoopHoist | 0 | 0.00%
LoopIVOpts | 0 | 0.00%
Unknown | 91 | 0.09%
RangeCheck | 0 | 0.00%
CopyProp | 952 | 0.95%
Promotion | 120 | 0.12%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 808 | 0.81%
ClassLayout | 88 | 0.09%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 288 | 0.29%
Pgo | 0 | 0.00%
MaskConversionOpt | 0 | 0.00%
TryRegionClone | 0 | 0.00%
Async | 0 | 0.00%
RangeCheckCloning | 0 | 0.00%
Final metrics:
ActualCodeBytes : 134
AllocatedHotCodeBytes : 134
AllocatedColdCodeBytes : 0
ReadOnlyDataBytes : 0
GCInfoBytes : 2
EHClauseCount : 0
PhysicallyPromotedFields : 0
LoopsFoundDuringOpts : 0
LoopsInverted : 0
LoopsCloned : 0
LoopsUnrolled : 0
LoopAlignmentCandidates : 0
LoopsAligned : 0
LoopsIVWidened : 0
WidenedIVs : 0
UnusedIVsRemoved : 0
LoopsMadeDownwardsCounted : 0
LoopsStrengthReduced : 0
VarsInSsa : 5
HoistedExpressions : 0
RedundantBranchesEliminated : 0
JumpThreadingsPerformed : 0
CseCount : 0
BasicBlocksAtCodegen : 1
PerfScore : 30.000000
BytesAllocated : 104136
ImporterBranchFold : 0
ImporterSwitchFold : 0
DevirtualizedCall : 0
DevirtualizedCallUnboxedEntry : 0
DevirtualizedCallRemovedBox : 0
GDV : 0
ClassGDV : 0
MethodGDV : 0
MultiGuessGDV : 0
ChainedGDV : 0
EnumeratorGDV : 0
InlinerBranchFold : 0
InlineAttempt : 0
InlineCount : 0
ProfileConsistentBeforeInline : 0
ProfileConsistentAfterInline : 0
ProfileConsistentBeforeMorph : 0
ProfileConsistentAfterMorph : 0
ProfileSynthesizedBlendedOrRepaired : 0
ProfileInconsistentInitially : 0
ProfileInconsistentResetLeave : 0
ProfileInconsistentImporterBranchFold : 0
ProfileInconsistentImporterSwitchFold : 0
ProfileInconsistentChainedGDV : 0
ProfileInconsistentScratchBB : 0
ProfileInconsistentInlinerBranchFold : 0
ProfileInconsistentInlineeScale : 0
ProfileInconsistentInlinee : 0
ProfileInconsistentNoReturnInlinee : 0
ProfileInconsistentMayThrowInlinee : 0
NewRefClassHelperCalls : 0
StackAllocatedRefClasses : 0
NewBoxedValueClassHelperCalls : 0
StackAllocatedBoxedValueClasses : 0
NewArrayHelperCalls : 0
StackAllocatedArrays : 0
LocalAssertionCount : 1
LocalAssertionOverflow : 0
MorphTrackedLocals : 5
MorphLocals : 6
EnumeratorGDVProvisionalNoEscape : 0
EnumeratorGDVCanCloneToEnsureNoEscape : 0
****** DONE compiling Managed.New.Decimal+DecCalc:DecDivMod1E9(byref):uint
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