static long mul2s(int a, int b)
{
return (long)a * (long)b;
}generates
; Method Program:<<Main>$>g__mul2|0_13(uint,uint):ulong (FullOpts)
G_M14403_IG01: ;; offset=0x0000
sub esp, 12
mov dword ptr [esp+0x08], edx
;; size=7 bbWeight=1 PerfScore 1.25
G_M14403_IG02: ;; offset=0x0007
mov edx, ecx
mulx edx, eax, dword ptr [esp+0x08]
;; size=9 bbWeight=1 PerfScore 5.25
G_M14403_IG03: ;; offset=0x0010
add esp, 12
ret
;; size=4 bbWeight=1 PerfScore 1.25
; Total bytes of code: 20****** START compiling Program:<<Main>$>g__mul2|0_13(uint,uint):ulong (MethodHash=3bd9c7bc)
Generating code for Windows x86
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: optimizer should use profile data
IL to import:
IL_0000 02 ldarg.0
IL_0001 6e conv.u8
IL_0002 03 ldarg.1
IL_0003 6e conv.u8
IL_0004 5a mul
IL_0005 2a ret
2 return registers for return type long
[00..04) reg eax
[04..08) reg edx
Parameter V00 ABI info: [00..04) reg ecx
Parameter V01 ABI info: [00..04) reg edx
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 int
*************** In compInitDebuggingInfo() for Program:<<Main>$>g__mul2|0_13(uint,uint):ulong
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 2
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 006h
1: 01h 01h V01 arg1 000h 006h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:<<Main>$>g__mul2|0_13(uint,uint):ulong
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [0000] [000..006)
IL Code Size,Instr 6, 6, Basic Block count 1, Local Variable Num,Ref count 2, 2 for method Program:<<Main>$>g__mul2|0_13(uint,uint):ulong
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:<<Main>$>g__mul2|0_13(uint,uint):ulong'
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
Trees after Pre-import
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)
*************** Finishing PHASE Profile incorporation [no changes]
*************** Starting PHASE Canonicalize entry
*************** Finishing PHASE Canonicalize entry [no changes]
*************** Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:<<Main>$>g__mul2|0_13(uint,uint):ulong'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) conv.u8
[ 1] 2 (0x002) ldarg.1
[ 2] 3 (0x003) conv.u8
[ 2] 4 (0x004) mul
[ 1] 5 (0x005) ret
STMT00000 ( 0x000[E-] ... ??? )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ---------U- +--* CAST long <- ulong <- uint
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ---------U- \--* CAST long <- ulong <- uint
[000002] ----------- \--* LCL_VAR int V01 arg1
*************** Finishing PHASE Importation
Trees after Importation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ---------U- +--* CAST long <- ulong <- uint
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ---------U- \--* CAST long <- ulong <- uint
[000002] ----------- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import [no changes]
*************** Starting PHASE Morph - Init
*************** Finishing PHASE Morph - Init [no changes]
*************** Starting PHASE Morph - Inlining
INLINER: no pgo data
**************** Inline Tree
Inlines into 06000010 [via ExtendedDefaultPolicy] Program:<<Main>$>g__mul2|0_13(uint,uint):ulong:
Budget: initialTime=78, finalTime=78, initialBudget=1560, currentBudget=1560
Budget: initialSize=268, finalSize=268
*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ---------U- +--* CAST long <- ulong <- uint
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ---------U- \--* CAST long <- ulong <- uint
[000002] ----------- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE DFS blocks and remove dead code 1
*************** Finishing PHASE DFS blocks and remove dead code 1 [no changes]
*************** Starting PHASE Allocate Objects
no newobjs or newarr in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks [no changes]
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty try/catch/fault
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try/catch/fault [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Head and tail merge
*************** Finishing PHASE Head and tail merge
Trees after Head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ---------U- +--* CAST long <- ulong <- uint
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ---------U- \--* CAST long <- ulong <- uint
[000002] ----------- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks [no changes]
*************** Starting PHASE Update flow graph early pass
*************** Finishing PHASE Update flow graph early pass [no changes]
*************** Starting PHASE Morph - Promote Structs
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 int
*************** Finishing PHASE Morph - Promote Structs [no changes]
*************** Starting PHASE DFS blocks and remove dead code 2
*************** Finishing PHASE DFS blocks and remove dead code 2 [no changes]
*************** Starting PHASE Morph - Structs/AddrExp
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ---------U- +--* CAST long <- ulong <- uint
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ---------U- \--* CAST long <- ulong <- uint
[000002] ----------- \--* LCL_VAR int V01 arg1
*************** Finishing PHASE Morph - Structs/AddrExp [no changes]
*************** Starting PHASE Optimize mask conversions
Skipping. There are no converts of locals
*************** Finishing PHASE Optimize mask conversions [no changes]
*************** Starting PHASE Early liveness
Tracked variable (2 out of 2) table:
V00 arg0 [ int]: refCnt = 1, refCntWtd = 0
V01 arg1 [ int]: refCnt = 1, refCntWtd = 0
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V00 V01}
DEF(0)={ }
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (2)={V00 V01}
OUT(0)={ }
*************** Finishing PHASE Early liveness
Trees after Early liveness
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ---------U- +--* CAST long <- ulong <- uint
[000000] ----------- | \--* LCL_VAR int V00 arg0 (last use)
[000003] ---------U- \--* CAST long <- ulong <- uint
[000002] ----------- \--* LCL_VAR int V01 arg1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Forward Substitution
===> BB01
*************** Finishing PHASE Forward Substitution [no changes]
*************** Starting PHASE Physical promotion
*************** Finishing PHASE Physical promotion [no changes]
*************** Starting PHASE Identify candidates for implicit byref copy omission
*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]
*************** Starting PHASE Morph - ByRefs
*************** Finishing PHASE Morph - ByRefs [no changes]
*************** Starting PHASE Morph - Global
Cross-block table size 64 (for 2 tracked locals)
Morphing BB01
BB01 ineligible for cross-block
Assertions in: #NA
fgMorphTree BB01, STMT00000 (before)
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ---------U- +--* CAST long <- ulong <- uint
[000000] ----------- | \--* LCL_VAR int V00 arg0 (last use)
[000003] ---------U- \--* CAST long <- ulong <- uint
[000002] ----------- \--* LCL_VAR int V01 arg1 (last use)
morph assertion stats: 64 table size, 0 assertions, 0 dropped
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+---U- \--* MUL long
[000001] -----+-N-U- +--* CAST long <- ulong <- uint
[000000] -----+----- | \--* LCL_VAR int V00 arg0 (last use)
[000003] -----+-N-U- \--* CAST long <- ulong <- uint
[000002] -----+----- \--* LCL_VAR int V01 arg1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Post-Morph
*************** In fgMarkDemotedImplicitByRefArgs()
*************** Finishing PHASE Post-Morph
Trees after Post-Morph
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+---U- \--* MUL long
[000001] -----+-N-U- +--* CAST long <- ulong <- uint
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N-U- \--* CAST long <- ulong <- uint
[000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie [no changes]
*************** Starting PHASE Compute block weights
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute block weights [no changes]
*************** Starting PHASE Remove empty finally 2
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 2 [no changes]
*************** Starting PHASE Remove empty try 2
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 2 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 2
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 2 [no changes]
*************** Starting PHASE Invert loops
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
*************** Finishing PHASE Invert loops
Trees after Invert loops
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+---U- \--* MUL long
[000001] -----+-N-U- +--* CAST long <- ulong <- uint
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N-U- \--* CAST long <- ulong <- uint
[000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Optimize control flow
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** Finishing PHASE Optimize control flow [no changes]
*************** Starting PHASE Post-morph head and tail merge
*************** Finishing PHASE Post-morph head and tail merge
Trees after Post-morph head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+---U- \--* MUL long
[000001] -----+-N-U- +--* CAST long <- ulong <- uint
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N-U- \--* CAST long <- ulong <- uint
[000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE DFS blocks and remove dead code 3
*************** Finishing PHASE DFS blocks and remove dead code 3 [no changes]
*************** Starting PHASE Find loops
*************** In optFindLoopsPhase()
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
*************** Finishing PHASE Find loops
Trees after Find loops
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+---U- \--* MUL long
[000001] -----+-N-U- +--* CAST long <- ulong <- uint
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N-U- \--* CAST long <- ulong <- uint
[000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Repair profile post-morph
No PGO data. Skipping profile repair.
*************** Finishing PHASE Repair profile post-morph [no changes]
*************** Starting PHASE Set block weights
After computing the dominance tree:
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
Return blocks: BB01
*************** Finishing PHASE Set block weights [no changes]
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
No loops to clone
*************** Finishing PHASE Clone loops [no changes]
*************** Starting PHASE Unroll loops
*************** Finishing PHASE Unroll loops [no changes]
*************** Starting PHASE Compute dominators
*************** Finishing PHASE Compute dominators [no changes]
*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function
*************** Finishing PHASE Morph array ops [no changes]
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1)
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+---U- \--* MUL long
[000001] -----+-N-U- +--* CAST long <- ulong <- uint
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N-U- \--* CAST long <- ulong <- uint
[000002] -----+----- \--* LCL_VAR int V01 arg1
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
*************** Finishing PHASE Mark local vars [no changes]
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
Trees after Find oper order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
( 16, 13) [000005] -----+----- * RETURN long
( 15, 12) [000004] L----+---U- \--* MUL long
( 2, 3) [000001] -----+-N-U- +--* CAST long <- ulong <- uint
( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0
( 2, 3) [000003] -----+-N-U- \--* CAST long <- ulong <- uint
( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 6 tree nodes
*************** Finishing PHASE Set block order
Trees after Set block order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
N006 ( 16, 13) [000005] -----+----- * RETURN long
N005 ( 15, 12) [000004] L----+---U- \--* MUL long
N002 ( 2, 3) [000001] -----+-N-U- +--* CAST long <- ulong <- uint
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0
N004 ( 2, 3) [000003] -----+-N-U- \--* CAST long <- ulong <- uint
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Tracked variable (2 out of 2) table:
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3
V01 arg1 [ int]: refCnt = 3, refCntWtd = 3
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V00 V01}
DEF(0)={ }
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (2)={V00 V01}
OUT(0)={ }
*************** In optRemoveRedundantZeroInits()
Analyzing BB01
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
V00.1: defined in BB00 1 uses (global)
V01.1: defined in BB00 1 uses (global)
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
N006 ( 16, 13) [000005] -----+----- * RETURN long
N005 ( 15, 12) [000004] L----+---U- \--* MUL long
N002 ( 2, 3) [000001] -----+-N-U- +--* CAST long <- ulong <- uint
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use)
N004 ( 2, 3) [000003] -----+-N-U- \--* CAST long <- ulong <- uint
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use)
SSA MEM: ByrefExposed, GcHeap = m:1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
[info] HasGlobalUse overestimated for V01.1
SSA checks completed successfully
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method
*************** Finishing PHASE Early Value Propagation [no changes]
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
Visiting BB01
The SSA definition for ByrefExposed (#1) at start of BB01 is $c0 {InitVal($42)}
The SSA definition for GcHeap (#1) at start of BB01 is $c0 {InitVal($42)}
***** BB01, STMT00000(before)
N006 ( 16, 13) [000005] -----+----- * RETURN long
N005 ( 15, 12) [000004] L----+---U- \--* MUL long
N002 ( 2, 3) [000001] -----+-N-U- +--* CAST long <- ulong <- uint
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use)
N004 ( 2, 3) [000003] -----+-N-U- \--* CAST long <- ulong <- uint
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use)
N001 [000000] LCL_VAR V00 arg0 u:1 (last use) => $80 {InitVal($40)}
N002 [000001] CAST => $100 {$80, long <- ulong <- uint}
N003 [000002] LCL_VAR V01 arg1 u:1 (last use) => $81 {InitVal($41)}
N004 [000003] CAST => $101 {$81, long <- ulong <- uint}
N005 [000004] MUL => $102 {MUL($100, $101)}
N006 [000005] RETURN => $VN.Void
***** BB01, STMT00000(after)
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
N005 ( 15, 12) [000004] L----+---U- \--* MUL long $102
N002 ( 2, 3) [000001] -----+-N-U- +--* CAST long <- ulong <- uint $100
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use) $80
N004 ( 2, 3) [000003] -----+-N-U- \--* CAST long <- ulong <- uint $101
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use) $81
*************** Finishing PHASE Do value numbering
Trees after Do value numbering
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
N005 ( 15, 12) [000004] L----+---U- \--* MUL long $102
N002 ( 2, 3) [000001] -----+-N-U- +--* CAST long <- ulong <- uint $100
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use) $80
N004 ( 2, 3) [000003] -----+-N-U- \--* CAST long <- ulong <- uint $101
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use) $81
SSA MEM: ByrefExposed, GcHeap = m:1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
[info] HasGlobalUse overestimated for V01.1
SSA checks completed successfully
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Hoist loop code
No loops; no hoisting
*************** Finishing PHASE Hoist loop code [no changes]
*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
curSsaName stack: { }
Live vars after [000000]: {V00 V01} -{V00} => {V01}
Live vars after [000002]: {V01} -{V01} => {}
orig [000002] copy [000000] VNs proved equivalent
*************** Finishing PHASE VN based copy prop [no changes]
*************** Starting PHASE Redundant branch opts
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Redundant branch opts [no changes]
*************** Starting PHASE Optimize Valnum CSEs
CONST CSE is disabled
Standard CSE Heuristic
Standard CSE Heuristic
*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
N005 ( 15, 12) [000004] L----+---U- \--* MUL long $102
N002 ( 2, 3) [000001] -----+-N-U- +--* CAST long <- ulong <- uint $100
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use) $80
N004 ( 2, 3) [000003] -----+-N-U- \--* CAST long <- ulong <- uint $101
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use) $81
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Assertion prop
*************** Finishing PHASE Assertion prop [no changes]
*************** Starting PHASE Optimize index checks
*************** Finishing PHASE Optimize index checks [no changes]
*************** Starting PHASE Optimize Induction Variables
*************** In optInductionVariables()
Skipping since this method has no natural loops
*************** Finishing PHASE Optimize Induction Variables [no changes]
*************** Starting PHASE VN-based dead store removal
*************** Finishing PHASE VN-based dead store removal [no changes]
*************** Starting PHASE Clone blocks with range checks
Current method has no bounds checks
*************** Finishing PHASE Clone blocks with range checks [no changes]
*************** Starting PHASE VN based intrinsic expansion
*************** Finishing PHASE VN based intrinsic expansion [no changes]
Removing PHI functions
*************** Starting PHASE Stress gtSplitTree
*************** Finishing PHASE Stress gtSplitTree [no changes]
*************** Starting PHASE Remove empty finally 3
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 3 [no changes]
*************** Starting PHASE Remove empty try 3
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 3 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 3
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 3 [no changes]
*************** Starting PHASE Create EH funclets
*************** Finishing PHASE Create EH funclets [no changes]
*************** Starting PHASE Expand casts
*************** Finishing PHASE Expand casts [no changes]
*************** Starting PHASE Expand runtime lookups
*************** Finishing PHASE Expand runtime lookups [no changes]
*************** Starting PHASE Expand static init
Nothing to expand.
*************** Finishing PHASE Expand static init [no changes]
*************** Starting PHASE Expand TLS access
Nothing to expand.
*************** Finishing PHASE Expand TLS access [no changes]
*************** Starting PHASE Expand stack array allocation
*************** Finishing PHASE Expand stack array allocation [no changes]
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Create throw helper blocks
*************** Finishing PHASE Create throw helper blocks [no changes]
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
optimized 0 BBJ_COND cases in 1 passes
*************** Finishing PHASE Optimize bools [no changes]
*************** Starting PHASE If conversion
*************** Finishing PHASE If conversion [no changes]
*************** Starting PHASE Recognize Switch
*************** Finishing PHASE Recognize Switch [no changes]
*************** Starting PHASE Optimize pre-layout
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** Finishing PHASE Optimize pre-layout [no changes]
*************** Starting PHASE Repair profile pre-layout
No PGO data. Skipping profile repair.
*************** Finishing PHASE Repair profile pre-layout [no changes]
*************** Starting PHASE Rationalize IR
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
[000006] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
/--* t0 int
N002 ( 2, 3) [000001] -----+-N-U- t1 = * CAST long <- ulong <- uint $100
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t2 int
N004 ( 2, 3) [000003] -----+-N-U- t3 = * CAST long <- ulong <- uint $101
/--* t1 long
+--* t3 long
N005 ( 15, 12) [000004] L----+---U- t4 = * MUL long $102
/--* t4 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Lowering nodeinfo
lvaTable after PromoteLongVars
; Initial local variable assignments
;
; V00 arg0 int single-def
; V01 arg1 int single-def
0 parameter register to local mappings
Decomposing TYP_LONG tree. BEFORE:
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
/--* t0 int
N002 ( 2, 3) [000001] -----+-N-U- t1 = * CAST long <- ulong <- uint $100
Decomposing TYP_LONG tree. AFTER:
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
/--* t0 int
N002 ( 2, 3) [000001] -----+-N-U- t1 = * CAST long <- ulong <- uint $100
Decomposing TYP_LONG tree. BEFORE:
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t2 int
N004 ( 2, 3) [000003] -----+-N-U- t3 = * CAST long <- ulong <- uint $101
Decomposing TYP_LONG tree. AFTER:
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t2 int
N004 ( 2, 3) [000003] -----+-N-U- t3 = * CAST long <- ulong <- uint $101
Decomposing TYP_LONG tree. BEFORE:
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
/--* t0 int
N002 ( 2, 3) [000001] -----+-N-U- t1 = * CAST long <- ulong <- uint $100
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t2 int
N004 ( 2, 3) [000003] -----+-N-U- t3 = * CAST long <- ulong <- uint $101
/--* t1 long
+--* t3 long
N005 ( 15, 12) [000004] L----+---U- t4 = * MUL long $102
lvaGrabTemp returning 2 (V02 rat0) called for ReplaceWithLclVar is creating a new local variable.
ReplaceWithLclVar created store :
[000007] DA--------- * STORE_LCL_VAR long V02 rat0
Promoting long local V02:
lvaGrabTemp returning 3 (V03 rat1) (a long lifetime temp) called for field V02.lo (fldOffset=0x0).
lvaGrabTemp returning 4 (V04 rat2) (a long lifetime temp) called for field V02.hi (fldOffset=0x4).
Decomposing TYP_LONG tree. AFTER:
[000008] ----------- t8 = LCL_VAR int V03 rat1
[000009] ----------- t9 = LCL_VAR int V04 rat2
/--* t8 int
+--* t9 int
[000010] ----------- t10 = * LONG long
Decomposing TYP_LONG tree. BEFORE:
[000008] ----------- t8 = LCL_VAR int V03 rat1
[000009] ----------- t9 = LCL_VAR int V04 rat2
/--* t8 int
+--* t9 int
[000010] ----------- t10 = * LONG long
/--* t10 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
Decomposing TYP_LONG tree. AFTER:
[000008] ----------- t8 = LCL_VAR int V03 rat1
[000009] ----------- t9 = LCL_VAR int V04 rat2
/--* t8 int
+--* t9 int
[000010] ----------- t10 = * LONG long
/--* t10 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t0 int
+--* t2 int
N005 ( 15, 12) [000004] L----+---U- t4 = * MUL_LONG long
/--* t4 long
[000007] DA--------- * STORE_LCL_VAR long (P) V02 rat0
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2
lowering store lcl var/field (after):
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t0 int
+--* t2 int
N005 ( 15, 12) [000004] L----+---U- t4 = * MUL_LONG long
/--* t4 long
[000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2
lowering return node
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
============
Lower has completed modifying nodes.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
[000006] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t0 int
+--* t2 int
N005 ( 15, 12) [000004] L----+---U- t4 = * MUL_LONG long
/--* t4 long
[000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2
[000008] ----------- t8 = LCL_VAR int V03 rat1
[000009] ----------- t9 = LCL_VAR int V04 rat2
/--* t8 int
+--* t9 int
[000010] -c--------- t10 = * LONG long
/--* t10 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V03: refCnt = 1, refCntWtd = 2
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 1, refCntWtd = 2
New refCnts for V03: refCnt = 2, refCntWtd = 3
New refCnts for V04: refCnt = 2, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 int single-def
; V01 arg1 int single-def
; V02 rat0 long multireg-ret multireg-dest "ReplaceWithLclVar is creating a new local variable"
; V03 rat1 int "field V02.lo (fldOffset=0x0)" P-INDEP
; V04 rat2 int "field V02.hi (fldOffset=0x4)" P-INDEP
In fgLocalVarLivenessInit
Tracked variable (4 out of 5) table:
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3
V01 arg1 [ int]: refCnt = 3, refCntWtd = 3
V03 rat1 [ int]: refCnt = 2, refCntWtd = 3
V04 rat2 [ int]: refCnt = 2, refCntWtd = 3
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V00 V01 }
DEF(2)={ V03 V04}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (2)={V00 V01}
OUT(0)={ }
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V03: refCnt = 1, refCntWtd = 2
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 1, refCntWtd = 2
New refCnts for V03: refCnt = 2, refCntWtd = 3
New refCnts for V04: refCnt = 2, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
[000006] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t0 int
+--* t2 int
N005 ( 15, 12) [000004] L----+---U- t4 = * MUL_LONG long
/--* t4 long
[000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2
[000008] ----------- t8 = LCL_VAR int V03 rat1 (last use)
[000009] ----------- t9 = LCL_VAR int V04 rat2 (last use)
/--* t8 int
+--* t9 int
[000010] -c--------- t10 = * LONG long
/--* t10 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01
use: {V00 V01}
def: {V03 V04}
in: {V00 V01}
out: {}
Interval 0: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 0: (V00) int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 1: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 1: (V01) int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 2: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 2: (V03) int (field) RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 3: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 3: (V04) int (field) RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Double alignment:
Bytes that could be saved by not using EBP frame: 9
Sum of weighted ref counts for EBP enregistered variables: 150.000000
Sum of weighted ref counts for weighted stack based doubles: 0.000000
Predicting not to double-align ESP to save 9 bytes of code.
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
Start LSRA Block Sequence:
Current block: BB01
Final LSRA Block Sequence:
BB01 ( 1 )
BB01 [0000] [000..006) (return), preds={} succs={}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. V00(t0*)
N003. V01(t2*)
N005. t4 = MUL_LONG ; t0*,t2*
N000. V02 MEM; t4
N000. V03(t8*)
N000. V04(t9*)
N000. t10 = LONG ; t8*,t9*
N006. RETURN ; t10
buildIntervals second part ========
Arg V00 is live in reg ecx
Arg V01 is live in reg edx
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed wt=100.00>
NEW BLOCK BB01
<RefPosition #2 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
DefList: { }
N003 (???,???) [000006] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N005 ( 1, 1) [000000] -----+----- * LCL_VAR int V00 arg0 u:1 NA (last use) REG NA $80
DefList: { }
N007 ( 1, 1) [000002] -----+----- * LCL_VAR int V01 arg1 u:1 NA (last use) REG NA $81
DefList: { }
N009 ( 15, 12) [000004] L----+---U- * MUL_LONG long REG NA,NA
Notify VM instruction set (AVX2) must be supported.
<RefPosition #3 @9 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
<RefPosition #5 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
Interval 4: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
<RefPosition #6 @10 RefTypeDef <Ivl:4> MUL_LONG[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
Interval 5: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
<RefPosition #7 @10 RefTypeDef <Ivl:5> MUL_LONG[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
DefList: { N009.t4. MUL_LONG; N009.t4. MUL_LONG }
N011 (???,???) [000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0 NA
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2 REG NA,NA
<RefPosition #8 @11 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V03/L2> to <I4>
<RefPosition #9 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #10 @13 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V04/L3> to <I5>
<RefPosition #11 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 last wt=400.00>
DefList: { }
N015 (???,???) [000008] ----------- * LCL_VAR int V03 rat1 NA (last use) REG NA
DefList: { }
N017 (???,???) [000009] ----------- * LCL_VAR int V04 rat2 NA (last use) REG NA
DefList: { }
N019 (???,???) [000010] -c--------- * LONG long REG NA
Contained
DefList: { }
N021 ( 16, 13) [000005] -----+----- * RETURN long REG NA $VN.Void
<RefPosition #12 @21 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #13 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
<RefPosition #14 @21 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #15 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
CHECKING LAST USES for BB01, liveout={}
==============================
use: {V00 V01}
def: {V03 V04}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) int RefPositions {#0@0 #4@9} physReg:ecx Preferences=[ecx edx] Aversions=[]
Interval 1: (V01) int RefPositions {#1@0 #5@9} physReg:edx Preferences=[edx] Aversions=[]
Interval 2: (V03) int (field) RefPositions {#9@12 #13@21} physReg:NA Preferences=[eax] Aversions=[]
Interval 3: (V04) int (field) RefPositions {#11@14 #15@21} physReg:NA Preferences=[edx] Aversions=[]
Interval 4: int RefPositions {#6@10 #8@11} physReg:NA Preferences=[allInt] Aversions=[] RelatedInterval <V03/L2>
Interval 5: int RefPositions {#7@10 #10@13} physReg:NA Preferences=[allInt] Aversions=[] RelatedInterval <V04/L3>
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3 @9 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
<RefPosition #5 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
<RefPosition #6 @10 RefTypeDef <Ivl:4> MUL_LONG[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #7 @10 RefTypeDef <Ivl:5> MUL_LONG[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #8 @11 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #9 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #10 @13 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #11 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #12 @21 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #13 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
<RefPosition #14 @21 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #15 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
------------
REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval)
------------
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
-----------------
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #5 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
-----------------
<RefPosition #9 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #13 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
-----------------
<RefPosition #11 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #15 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00 V01
BB01 [0000] [000..006) (return), preds={} succs={}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V00(L0)
N007. V01(L1)
N009. MUL_LONG
Use:<V00/L0>(#4) Fixed:edx(#3) *
Use:<V01/L1>(#5) *
Def:<I4>(#6) Pref:<V03/L2>
Def:<I5>(#7) Pref:<V04/L3>
N011. V02 MEM
Use:<I4>(#8) *
Def:<V03/L2>(#9)
N015. V03(L2)
N017. V04(L3)
N019. LONG
N021. RETURN
Linear scan intervals after buildIntervals:
Interval 0: (V00) int RefPositions {#0@0 #4@9} physReg:ecx Preferences=[ecx edx] Aversions=[]
Interval 1: (V01) int RefPositions {#1@0 #5@9} physReg:edx Preferences=[edx] Aversions=[]
Interval 2: (V03) int (field) RefPositions {#9@12 #13@21} physReg:NA Preferences=[eax] Aversions=[]
Interval 3: (V04) int (field) RefPositions {#11@14 #15@21} physReg:NA Preferences=[edx] Aversions=[]
Interval 4: int RefPositions {#6@10 #8@11} physReg:NA Preferences=[allInt] Aversions=[] RelatedInterval <V03/L2>
Interval 5: int RefPositions {#7@10 #10@13} physReg:NA Preferences=[allInt] Aversions=[] RelatedInterval <V04/L3>
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) int RefPositions {#0@0 #4@9} physReg:ecx Preferences=[ecx edx] Aversions=[]
Interval 1: (V01) int RefPositions {#1@0 #5@9} physReg:edx Preferences=[edx] Aversions=[]
Interval 2: (V03) int (field) RefPositions {#9@12 #13@21} physReg:NA Preferences=[eax] Aversions=[]
Interval 3: (V04) int (field) RefPositions {#11@14 #15@21} physReg:NA Preferences=[edx] Aversions=[]
Interval 4: int RefPositions {#6@10 #8@11} physReg:NA Preferences=[allInt] Aversions=[] RelatedInterval <V03/L2>
Interval 5: int RefPositions {#7@10 #10@13} physReg:NA Preferences=[allInt] Aversions=[] RelatedInterval <V04/L3>
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3 @9 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
<RefPosition #5 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
<RefPosition #6 @10 RefTypeDef <Ivl:4> MUL_LONG[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #7 @10 RefTypeDef <Ivl:5> MUL_LONG[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #8 @11 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #9 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #10 @13 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #11 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #12 @21 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #13 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
<RefPosition #14 @21 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #15 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #5 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
--- V02
--- V03 (Interval 2)
<RefPosition #9 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #13 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
--- V04 (Interval 3)
<RefPosition #11 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #15 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.
------------------------------------------+----+----+----+----+
TreeID LocRP# Name Type Action Reg |eax |ecx |edx |edi |
------------------------------------------+----+----+----+----+
| |V00a|V01a| |
0.#0 V00 Parm Keep ecx | |V00a|V01a| |
0.#1 V01 Parm THISA(A) edx | |V00a|V01a| |
1.#2 BB1 PredBB0 | |V00a|V01a| |
[000004] 9.#3 edx Fixd Keep edx | |V00a|V01a| |
9.#4 V00 Use * Spill edx | |V00i| | |
Copy edx | |V00a|V00a| |
9.#5 V01 Use * ReLod NA | |V00a|V00a| |
NoReg | |V00a|V00a| |
10.#6 I4 Def RELPR(A) eax |I4 a| | | |
10.#7 I5 Def RELPR(A) edx |I4 a| |I5 a| |
[000007] 11.#8 I4 Use * Keep eax |I4 a| |I5 a| |
12.#9 V03 Def COVRS(A) eax |V03a| |I5 a| |
13.#10 I5 Use * Keep edx |V03a| |I5 a| |
14.#11 V04 Def COVRS(A) edx |V03a| |V04a| |
[000005] 21.#12 eax Fixd Keep eax |V03a| |V04a| |
21.#13 V03 Use * Keep eax |V03a| |V04a| |
21.#14 edx Fixd Keep edx |V03a| |V04a| |
21.#15 V04 Use * Keep edx | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[] minReg=1 singleDefSpill regOptional wt=100.00>
<RefPosition #2 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3 @9 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[edx] minReg=1 last copy fixed wt=300.00>
<RefPosition #5 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[] minReg=1 last regOptional wt=150.00>
<RefPosition #6 @10 RefTypeDef <Ivl:4> MUL_LONG[0] BB01 regmask=[eax] minReg=1 wt=400.00>
<RefPosition #7 @10 RefTypeDef <Ivl:5> MUL_LONG[1] BB01 regmask=[edx] minReg=1 wt=400.00>
<RefPosition #8 @11 RefTypeUse <Ivl:4> BB01 regmask=[eax] minReg=1 last wt=100.00>
<RefPosition #9 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[eax] minReg=1 wt=400.00>
<RefPosition #10 @13 RefTypeUse <Ivl:5> BB01 regmask=[edx] minReg=1 last wt=100.00>
<RefPosition #11 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[edx] minReg=1 wt=400.00>
<RefPosition #12 @21 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #13 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
<RefPosition #14 @21 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #15 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[edx] minReg=1 last copy fixed wt=300.00>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[] minReg=1 singleDefSpill regOptional wt=100.00>
<RefPosition #5 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[] minReg=1 last regOptional wt=150.00>
--- V02
--- V03 (Interval 2)
<RefPosition #9 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[eax] minReg=1 wt=400.00>
<RefPosition #13 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
--- V04 (Interval 3)
<RefPosition #11 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[edx] minReg=1 wt=400.00>
<RefPosition #15 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V01}
Has No Critical Edges
Prior to Resolution
BB01
use: {V00 V01}
def: {V03 V04}
in: {V00 V01}
out: {}
Var=Reg beg of BB01: V00=ecx
Var=Reg end of BB01: none
RESOLVING EDGES
Set V00 argument initial register to ecx
Set V01 argument initial register to STK
Trees after linear scan register allocator (LSRA)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
N003 (???,???) [000006] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 ecx (last use) REG ecx $80
N007 ( 1, 1) [000002] -c---+----- t2 = LCL_VAR int V01 arg1 u:1 NA (last use) REG NA $81
/--* t0 int
+--* t2 int
N009 ( 15, 12) [000004] L----+---U- t4 = * MUL_LONG long REG eax,edx
/--* t4 long
N011 (???,???) [000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0 eax
* int field V02.lo (fldOffset=0x0) -> V03 rat1 eax
* int field V02.hi (fldOffset=0x4) -> V04 rat2 edx REG eax,edx
N015 (???,???) [000008] ----------- t8 = LCL_VAR int V03 rat1 eax (last use) REG eax
N017 (???,???) [000009] ----------- t9 = LCL_VAR int V04 rat2 edx (last use) REG edx
/--* t8 int
+--* t9 int
N019 (???,???) [000010] -c--------- t10 = * LONG long REG NA
/--* t10 long
N021 ( 16, 13) [000005] -----+----- * RETURN long REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------------------+----+----+----+----+
TreeID LocRP# Name Type Action Reg |eax |ecx |edx |edi |
------------------------------------------+----+----+----+----+
0.#0 V00 Parm Alloc ecx | |V00a| | |
0.#1 V01 Parm NoReg | |V00a| | |
1.#2 BB1 PredBB0 | |V00a| | |
[000004] 9.#3 edx Fixd Keep edx | |V00a| | |
9.#4 V00 Use * Copy edx | |V00i|V00i| |
9.#5 V01 Use * NoReg | | | | |
10.#6 I4 Def Alloc eax |I4 a| | | |
10.#7 I5 Def Alloc edx |I4 a| |I5 a| |
[000007] 11.#8 I4 Use * Keep eax |I4 i| |I5 a| |
12.#9 V03 Def Alloc eax |V03a| |I5 a| |
13.#10 I5 Use * Keep edx |V03a| |I5 i| |
14.#11 V04 Def Alloc edx |V03a| |V04a| |
[000005] 21.#12 eax Fixd Keep eax |V03a| |V04a| |
21.#13 V03 Use * Keep eax |V03i| |V04a| |
21.#14 edx Fixd Keep edx | | |V04a| |
21.#15 V04 Use * Keep edx | | |V04i| |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars: 4
Total Reg Cand Vars: 4
Total number of Intervals: 5
Total number of RefPositions: 15
Total Number of spill temps created: 0
..........
BB00 [ 100.00]: SpillCount = 1, THIS_ASSIGNED = 1
BB01 [ 100.00]: COVERS = 2, RELATED_PREFERENCE = 2
..........
Total SpillCount : 1 Weighted: 100.000000
Total CopyReg : 0 Weighted: 0.000000
Total ResolutionMovs : 0 Weighted: 0.000000
Total SplitEdges : 0 Weighted: 0.000000
..........
Total THIS_ASSIGNED [# 3] : 1 Weighted: 100.000000
Total COVERS [# 4] : 2 Weighted: 200.000000
Total RELATED_PREFERENCE [# 7] : 2 Weighted: 200.000000
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(ecx) V01(edx=>STK)
BB01 [0000] [000..006) (return), preds={} succs={}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V00(ecx*)
N007. V01(STK*)
N009. eax,edx = MUL_LONG ; ecx*
* N011. eax,edx = V02 MEM; eax,edx
N015. V03(eax*)
N017. V04(edx*)
N019. STK = LONG ; eax*,edx*
N021. RETURN ; STK
Var=Reg end of BB01: none
*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
N003 (???,???) [000006] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 ecx (last use) REG ecx $80
N007 ( 1, 1) [000002] -c---+----- t2 = LCL_VAR int V01 arg1 u:1 NA (last use) REG NA $81
/--* t0 int
+--* t2 int
N009 ( 15, 12) [000004] L----+---U- t4 = * MUL_LONG long REG eax,edx
/--* t4 long
N011 (???,???) [000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0 eax
* int field V02.lo (fldOffset=0x0) -> V03 rat1 eax
* int field V02.hi (fldOffset=0x4) -> V04 rat2 edx REG eax,edx
N015 (???,???) [000008] ----------- t8 = LCL_VAR int V03 rat1 eax (last use) REG eax
N017 (???,???) [000009] ----------- t9 = LCL_VAR int V04 rat2 edx (last use) REG edx
/--* t8 int
+--* t9 int
N019 (???,???) [000010] -c--------- t10 = * LONG long REG NA
/--* t10 long
N021 ( 16, 13) [000005] -----+----- * RETURN long REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Optimize layout
*************** In fgSearchImprovedLayout()
Initial BasicBlocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Not enough blocks to partition anything. Skipping reordering.
Reordering block list
*************** Finishing PHASE Optimize layout [no changes]
*************** Starting PHASE Optimize post-layout
*************** Finishing PHASE Optimize post-layout [no changes]
*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block [no changes]
*************** Starting PHASE Place 'align' instructions
*************** In placeLoopAlignInstructions()
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
Not checking for any loops as fgMightHaveNaturalLoops is false
*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(ecx)
Modified regs: [eax ecx edx]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V01 arg1, size=4, stkOffs=-0x8
Assign V02 rat0, size=8, stkOffs=-0x10
--- delta bump 4 for RA
--- delta bump 12 for RSP frame
--- virtual stack offset to actual stack offset delta is 16
-- V01 was -8, now 8
-- V02 was -16, now 0
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 3, 3 ) int -> ecx single-def
; V01 arg1 [V01,T01] ( 3, 3 ) int -> [esp+0x08] single-def
; V02 rat0 [V02 ] ( 1, 2 ) long -> [esp+0x00] multireg-ret multireg-dest "ReplaceWithLclVar is creating a new local variable"
; V03 rat1 [V03,T02] ( 2, 3 ) int -> eax "field V02.lo (fldOffset=0x0)" P-INDEP
; V04 rat2 [V04,T03] ( 2, 3 ) int -> edx "field V02.hi (fldOffset=0x4)" P-INDEP
;
; Lcl frame size = 12
Created:
G_M14403_IG02: ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=00000000 {}
Mark labels for codegen
BB01 : first block
*************** After genMarkLabelsForCodegen()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR label
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
=============== Generating BB01 [0000] [000..006) (return), preds={} succs={} flags=0x00000000.00001011: i LIR label
BB01 IN (2)={V00 V01}
OUT(0)={ }
Recording Var Locations at start of BB01
V00(ecx)
Change life 0000000000000000 {} -> 0000000000000003 {V00 V01}
V00 in reg ecx is becoming live [------]
Live regs: 00000000 {} + {ecx} => 00000002 {ecx}
Debug: New V00 debug range: first
Debug: New V01 debug range: first
Live regs: (unchanged) 00000002 {ecx}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M14403_BB01:
Label: G_M14403_IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB01, IL range [000..006)
Added IP mapping: 0x0000 STACK_EMPTY (G_M14403_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000006] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 ecx (last use) REG ecx $80
Generating: N007 ( 1, 1) [000002] -c---+----- t2 = LCL_VAR int V01 arg1 u:1 NA (last use) REG NA $81
/--* t0 int
+--* t2 int
Generating: N009 ( 15, 12) [000004] L----+---U- t4 = * MUL_LONG long REG eax,edx
V00 in reg ecx is becoming dead [000000]
Live regs: 00000002 {ecx} - {ecx} => 00000000 {}
Debug: Closing V00 debug range.
Live vars after [000000]: {V00 V01} -{V00} => {V01}
Debug: Closing V01 debug range.
Live vars after [000002]: {V01} -{V01} => {}
Mapped BB01 to G_M14403_IG02
IN0001: mov edx, ecx
IN0002: mulx edx, eax, dword ptr [V01 esp+0x08]
/--* t4 long
Generating: N011 (???,???) [000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0 eax
* int field V02.lo (fldOffset=0x0) -> V03 rat1 eax
* int field V02.hi (fldOffset=0x4) -> V04 rat2 edx REG eax,edx
V03 in reg eax is becoming live [000007]
Live regs: 00000000 {} + {eax} => 00000001 {eax}
V04 in reg edx is becoming live [000007]
Live regs: 00000001 {eax} + {edx} => 00000005 {eax edx}
Live vars after [000007]: {} +{V03 V04} => {V03 V04}
Generating: N015 (???,???) [000008] ----------- t8 = LCL_VAR int V03 rat1 eax (last use) REG eax
Generating: N017 (???,???) [000009] ----------- t9 = LCL_VAR int V04 rat2 edx (last use) REG edx
/--* t8 int
+--* t9 int
Generating: N019 (???,???) [000010] -c--------- t10 = * LONG long REG NA
/--* t10 long
Generating: N021 ( 16, 13) [000005] -----+----- * RETURN long REG NA $VN.Void
V03 in reg eax is becoming dead [000008]
Live regs: 00000005 {eax edx} - {eax} => 00000004 {edx}
Live vars after [000008]: {V03 V04} -{V03} => {V04}
V04 in reg edx is becoming dead [000009]
Live regs: 00000004 {edx} - {edx} => 00000000 {}
Live vars after [000009]: {V04} -{V04} => {}
Added IP mapping: EPILOG (G_M14403_IG02,ins#2,ofs#9) label
Reserving epilog IG for block BB01
Saved:
G_M14403_IG02: ; offs=0x000000, size=0x0009, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
Created:
G_M14403_IG03: ; offs=0x000009, size=0x0000, bbWeight=1, gcrefRegs=00000000 {}
*************** After placeholder IG creation
G_M14403_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=00000000 {} <-- Prolog IG
G_M14403_IG02: ; offs=0x000000, size=0x0009, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M14403_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Variable Live Range History Dump for BB01
V00 arg0: ecx [(G_M14403_IG02,ins#0,ofs#0), (G_M14403_IG02,ins#0,ofs#0)]
V01 arg1: esp'[8] (1 slot) [(G_M14403_IG02,ins#0,ofs#0), (G_M14403_IG02,ins#0,ofs#0)]
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 16, compSizeEstimate = 13 Program:<<Main>$>g__mul2|0_13(uint,uint):ulong
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 3, 3 ) int -> ecx single-def
; V01 arg1 [V01,T01] ( 3, 3 ) int -> [esp+0x08] single-def
; V02 rat0 [V02 ] ( 1, 2 ) long -> [esp+0x00] multireg-ret multireg-dest "ReplaceWithLclVar is creating a new local variable"
; V03 rat1 [V03,T02] ( 2, 3 ) int -> eax "field V02.lo (fldOffset=0x0)" P-INDEP
; V04 rat2 [V04,T03] ( 2, 3 ) int -> edx "field V02.hi (fldOffset=0x4)" P-INDEP
;
; Lcl frame size = 12
*************** Before prolog / epilog generation
G_M14403_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=00000000 {} <-- Prolog IG
G_M14403_IG02: ; offs=0x000000, size=0x0009, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M14403_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
V00(ecx)
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M14403_IG01,ins#0,ofs#0) label
__prolog:
Debug: New V00 debug range: first
Debug: New V01 debug range: first
IN0003: sub esp, 12
*************** In genHomeRegisterParams()
IN0004: mov dword ptr [V01 esp+0x08], edx
1 registers in register parameter interference graph
ecx
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Saved:
G_M14403_IG01: ; offs=0x000000, size=0x0007, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN0005: add esp, 12
IN0006: ret
Saved:
G_M14403_IG03: ; offs=0x000009, size=0x0004, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M14403_IG01: ; func=00, offs=0x000000, size=0x0007, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M14403_IG02: ; offs=0x000007, size=0x0009, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M14403_IG03: ; offs=0x000010, size=0x0004, bbWeight=1, epilog, nogc, extend
*************** In emitJumpDistBind()
Emitter Jump List:
total jump count: 0
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x14 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x4)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M14403_IG01: ; offs=0x000000, size=0x0007, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0003: 000000 sub esp, 12
IN0004: 000003 mov dword ptr [esp+0x08], edx
;; size=7 bbWeight=1 PerfScore 1.25
G_M14403_IG02: ; offs=0x000007, size=0x0009, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
IN0001: 000007 mov edx, ecx
IN0002: 000009 mulx edx, eax, dword ptr [esp+0x08]
;; size=9 bbWeight=1 PerfScore 5.25
G_M14403_IG03: ; offs=0x000010, size=0x0004, bbWeight=1, epilog, nogc, extend
IN0005: 000010 add esp, 12
IN0006: 000013 ret
;; size=4 bbWeight=1 PerfScore 1.25
Allocated method code size = 20 , actual size = 20, unused size = 0
; Total bytes of code 20, prolog size 3, PerfScore 7.75, instruction count 6, allocated bytes for code 20 (MethodHash=3bd9c7bc) for method Program:<<Main>$>g__mul2|0_13(uint,uint):ulong (FullOpts)
; ============================================================
*************** After end code gen, before unwindEmit()
G_M14403_IG01: ; func=00, offs=0x000000, size=0x0007, bbWeight=1, PerfScore 1.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0003: 000000 sub esp, 12
IN0004: 000003 mov dword ptr [V01 esp+0x08], edx
G_M14403_IG02: ; offs=0x000007, size=0x0009, bbWeight=1, PerfScore 5.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
IN0001: 000007 mov edx, ecx
IN0002: 000009 mulx edx, eax, dword ptr [V01 esp+0x08]
G_M14403_IG03: ; offs=0x000010, size=0x0004, bbWeight=1, PerfScore 1.25, epilog, nogc, extend
IN0005: 000010 add esp, 12
IN0006: 000013 ret
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
allocUnwindInfo(pHotCode=0x00007FFA293F4570, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x14, unwindSize=0x4, pUnwindBlock=0x0000007DB0B7B630, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 3
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000007 ( STACK_EMPTY )
IL offs EPILOG : 0x00000010 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 4
; Variable debug info: 3 live ranges, 2 vars for method Program:<<Main>$>g__mul2|0_13(uint,uint):ulong
(V00 arg0) : From 00000000h to 00000007h, in ecx
(V01 arg1) : From 00000000h to 00000007h, in edx
(V01 arg1) : From 00000007h to 00000008h, in esp'[8] (1 slot)
*************** In gcInfoBlockHdrSave()
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
*************** In gcInfoBlockHdrSave()
GCINFO: methodSize = 0014
GCINFO: prologSize = 0003
GCINFO: epilogSize = 0004
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
GC Info for method Program:<<Main>$>g__mul2|0_13(uint,uint):ulong
GC info size = 6
Method info block:
method size = 0014
prolog size = 3
epilog size = 4
epilog count = 1
epilog end = yes
callee-saved regs =
ebp frame = no
fully interruptible= no
double align = no
arguments size = 0 DWORDs
stack frame size = 3 DWORDs
untracked count = 0
var ptr tab count = 0
epilog at 0010
14 B0 83 BB 3C |
Pointer table:
FF 00 06 ...|
*************** Finishing PHASE Emit GC+EH tables
Method code size: 20
Allocations for Program:<<Main>$>g__mul2|0_13(uint,uint):ulong (MethodHash=3bd9c7bc)
count: 332, size: 41104, max = 3208
allocateMemory: 65536, nraUsed: 44240
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
ABI | 152 | 0.37%
AssertionProp | 6500 | 15.81%
ASTNode | 1744 | 4.24%
InstDesc | 2352 | 5.72%
ImpStack | 384 | 0.93%
BasicBlock | 336 | 0.82%
CallArgs | 0 | 0.00%
FlowEdge | 0 | 0.00%
DepthFirstSearch | 224 | 0.54%
Loops | 260 | 0.63%
TreeStatementList | 0 | 0.00%
SiScope | 0 | 0.00%
DominatorMemory | 128 | 0.31%
LSRA | 4708 | 11.45%
LSRA_Interval | 528 | 1.28%
LSRA_RefPosition | 1280 | 3.11%
Reachability | 40 | 0.10%
SSA | 320 | 0.78%
ValueNumber | 5424 | 13.20%
LvaTable | 1612 | 3.92%
UnwindInfo | 0 | 0.00%
hashBv | 40 | 0.10%
bitset | 32 | 0.08%
FixedBitVect | 16 | 0.04%
Generic | 686 | 1.67%
LocalAddressVisitor | 32 | 0.08%
FieldSeqStore | 0 | 0.00%
MemorySsaMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 1256 | 3.06%
GC | 24 | 0.06%
CorTailCallInfo | 0 | 0.00%
Inlining | 472 | 1.15%
ArrayStack | 0 | 0.00%
DebugInfo | 224 | 0.54%
DebugOnly | 8848 | 21.53%
Codegen | 2144 | 5.22%
LoopOpt | 0 | 0.00%
LoopClone | 0 | 0.00%
LoopUnroll | 0 | 0.00%
LoopHoist | 0 | 0.00%
LoopIVOpts | 0 | 0.00%
Unknown | 42 | 0.10%
RangeCheck | 0 | 0.00%
CopyProp | 424 | 1.03%
Promotion | 120 | 0.29%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 648 | 1.58%
ClassLayout | 0 | 0.00%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 104 | 0.25%
Pgo | 0 | 0.00%
MaskConversionOpt | 0 | 0.00%
TryRegionClone | 0 | 0.00%
Async | 0 | 0.00%
RangeCheckCloning | 0 | 0.00%
Final metrics:
ActualCodeBytes : 20
AllocatedHotCodeBytes : 20
AllocatedColdCodeBytes : 0
ReadOnlyDataBytes : 0
GCInfoBytes : 6
EHClauseCount : 0
PhysicallyPromotedFields : 0
LoopsFoundDuringOpts : 0
LoopsInverted : 0
LoopsCloned : 0
LoopsUnrolled : 0
LoopAlignmentCandidates : 0
LoopsAligned : 0
LoopsIVWidened : 0
WidenedIVs : 0
UnusedIVsRemoved : 0
LoopsMadeDownwardsCounted : 0
LoopsStrengthReduced : 0
VarsInSsa : 2
HoistedExpressions : 0
RedundantBranchesEliminated : 0
JumpThreadingsPerformed : 0
CseCount : 0
BasicBlocksAtCodegen : 1
PerfScore : 7.750000
BytesAllocated : 44240
ImporterBranchFold : 0
ImporterSwitchFold : 0
DevirtualizedCall : 0
DevirtualizedCallUnboxedEntry : 0
DevirtualizedCallRemovedBox : 0
GDV : 0
ClassGDV : 0
MethodGDV : 0
MultiGuessGDV : 0
ChainedGDV : 0
EnumeratorGDV : 0
InlinerBranchFold : 0
InlineAttempt : 0
InlineCount : 0
ProfileConsistentBeforeInline : 0
ProfileConsistentAfterInline : 0
ProfileConsistentBeforeMorph : 0
ProfileConsistentAfterMorph : 0
ProfileSynthesizedBlendedOrRepaired : 0
ProfileInconsistentInitially : 0
ProfileInconsistentResetLeave : 0
ProfileInconsistentImporterBranchFold : 0
ProfileInconsistentImporterSwitchFold : 0
ProfileInconsistentChainedGDV : 0
ProfileInconsistentScratchBB : 0
ProfileInconsistentInlinerBranchFold : 0
ProfileInconsistentInlineeScale : 0
ProfileInconsistentInlinee : 0
ProfileInconsistentNoReturnInlinee : 0
ProfileInconsistentMayThrowInlinee : 0
NewRefClassHelperCalls : 0
StackAllocatedRefClasses : 0
NewBoxedValueClassHelperCalls : 0
StackAllocatedBoxedValueClasses : 0
NewArrayHelperCalls : 0
StackAllocatedArrays : 0
LocalAssertionCount : 0
LocalAssertionOverflow : 0
MorphTrackedLocals : 2
MorphLocals : 2
EnumeratorGDVProvisionalNoEscape : 0
EnumeratorGDVCanCloneToEnsureNoEscape : 0
****** DONE compiling Program:<<Main>$>g__mul2|0_13(uint,uint):ulong
****** START compiling Program:<<Main>$>g__mul2s|0_14(int,int):long (MethodHash=2bf748dd)
Generating code for Windows x86
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: optimizer should use profile data
IL to import:
IL_0000 02 ldarg.0
IL_0001 6a conv.i8
IL_0002 03 ldarg.1
IL_0003 6a conv.i8
IL_0004 5a mul
IL_0005 2a ret
2 return registers for return type long
[00..04) reg eax
[04..08) reg edx
Parameter V00 ABI info: [00..04) reg ecx
Parameter V01 ABI info: [00..04) reg edx
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 int
*************** In compInitDebuggingInfo() for Program:<<Main>$>g__mul2s|0_14(int,int):long
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 2
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 006h
1: 01h 01h V01 arg1 000h 006h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:<<Main>$>g__mul2s|0_14(int,int):long
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [0000] [000..006)
IL Code Size,Instr 6, 6, Basic Block count 1, Local Variable Num,Ref count 2, 2 for method Program:<<Main>$>g__mul2s|0_14(int,int):long
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:<<Main>$>g__mul2s|0_14(int,int):long'
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
Trees after Pre-import
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)
*************** Finishing PHASE Profile incorporation [no changes]
*************** Starting PHASE Canonicalize entry
*************** Finishing PHASE Canonicalize entry [no changes]
*************** Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:<<Main>$>g__mul2s|0_14(int,int):long'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) conv.i8
[ 1] 2 (0x002) ldarg.1
[ 2] 3 (0x003) conv.i8
[ 2] 4 (0x004) mul
[ 1] 5 (0x005) ret
STMT00000 ( 0x000[E-] ... ??? )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ----------- +--* CAST long <- int
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ----------- \--* CAST long <- int
[000002] ----------- \--* LCL_VAR int V01 arg1
*************** Finishing PHASE Importation
Trees after Importation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ----------- +--* CAST long <- int
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ----------- \--* CAST long <- int
[000002] ----------- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import [no changes]
*************** Starting PHASE Morph - Init
*************** Finishing PHASE Morph - Init [no changes]
*************** Starting PHASE Morph - Inlining
INLINER: no pgo data
**************** Inline Tree
Inlines into 06000011 [via ExtendedDefaultPolicy] Program:<<Main>$>g__mul2s|0_14(int,int):long:
Budget: initialTime=78, finalTime=78, initialBudget=1560, currentBudget=1560
Budget: initialSize=268, finalSize=268
*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ----------- +--* CAST long <- int
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ----------- \--* CAST long <- int
[000002] ----------- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE DFS blocks and remove dead code 1
*************** Finishing PHASE DFS blocks and remove dead code 1 [no changes]
*************** Starting PHASE Allocate Objects
no newobjs or newarr in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks [no changes]
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty try/catch/fault
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try/catch/fault [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Head and tail merge
*************** Finishing PHASE Head and tail merge
Trees after Head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ----------- +--* CAST long <- int
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ----------- \--* CAST long <- int
[000002] ----------- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks [no changes]
*************** Starting PHASE Update flow graph early pass
*************** Finishing PHASE Update flow graph early pass [no changes]
*************** Starting PHASE Morph - Promote Structs
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 int
*************** Finishing PHASE Morph - Promote Structs [no changes]
*************** Starting PHASE DFS blocks and remove dead code 2
*************** Finishing PHASE DFS blocks and remove dead code 2 [no changes]
*************** Starting PHASE Morph - Structs/AddrExp
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ----------- +--* CAST long <- int
[000000] ----------- | \--* LCL_VAR int V00 arg0
[000003] ----------- \--* CAST long <- int
[000002] ----------- \--* LCL_VAR int V01 arg1
*************** Finishing PHASE Morph - Structs/AddrExp [no changes]
*************** Starting PHASE Optimize mask conversions
Skipping. There are no converts of locals
*************** Finishing PHASE Optimize mask conversions [no changes]
*************** Starting PHASE Early liveness
Tracked variable (2 out of 2) table:
V00 arg0 [ int]: refCnt = 1, refCntWtd = 0
V01 arg1 [ int]: refCnt = 1, refCntWtd = 0
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V00 V01}
DEF(0)={ }
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (2)={V00 V01}
OUT(0)={ }
*************** Finishing PHASE Early liveness
Trees after Early liveness
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ----------- +--* CAST long <- int
[000000] ----------- | \--* LCL_VAR int V00 arg0 (last use)
[000003] ----------- \--* CAST long <- int
[000002] ----------- \--* LCL_VAR int V01 arg1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Forward Substitution
===> BB01
*************** Finishing PHASE Forward Substitution [no changes]
*************** Starting PHASE Physical promotion
*************** Finishing PHASE Physical promotion [no changes]
*************** Starting PHASE Identify candidates for implicit byref copy omission
*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]
*************** Starting PHASE Morph - ByRefs
*************** Finishing PHASE Morph - ByRefs [no changes]
*************** Starting PHASE Morph - Global
Cross-block table size 64 (for 2 tracked locals)
Morphing BB01
BB01 ineligible for cross-block
Assertions in: #NA
fgMorphTree BB01, STMT00000 (before)
[000005] ----------- * RETURN long
[000004] ----------- \--* MUL long
[000001] ----------- +--* CAST long <- int
[000000] ----------- | \--* LCL_VAR int V00 arg0 (last use)
[000003] ----------- \--* CAST long <- int
[000002] ----------- \--* LCL_VAR int V01 arg1 (last use)
morph assertion stats: 64 table size, 0 assertions, 0 dropped
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+----- \--* MUL long
[000001] -----+-N--- +--* CAST long <- int
[000000] -----+----- | \--* LCL_VAR int V00 arg0 (last use)
[000003] -----+-N--- \--* CAST long <- int
[000002] -----+----- \--* LCL_VAR int V01 arg1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Post-Morph
*************** In fgMarkDemotedImplicitByRefArgs()
*************** Finishing PHASE Post-Morph
Trees after Post-Morph
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+----- \--* MUL long
[000001] -----+-N--- +--* CAST long <- int
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N--- \--* CAST long <- int
[000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie [no changes]
*************** Starting PHASE Compute block weights
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute block weights [no changes]
*************** Starting PHASE Remove empty finally 2
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 2 [no changes]
*************** Starting PHASE Remove empty try 2
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 2 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 2
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 2 [no changes]
*************** Starting PHASE Invert loops
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
*************** Finishing PHASE Invert loops
Trees after Invert loops
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+----- \--* MUL long
[000001] -----+-N--- +--* CAST long <- int
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N--- \--* CAST long <- int
[000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Optimize control flow
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** Finishing PHASE Optimize control flow [no changes]
*************** Starting PHASE Post-morph head and tail merge
*************** Finishing PHASE Post-morph head and tail merge
Trees after Post-morph head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+----- \--* MUL long
[000001] -----+-N--- +--* CAST long <- int
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N--- \--* CAST long <- int
[000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE DFS blocks and remove dead code 3
*************** Finishing PHASE DFS blocks and remove dead code 3 [no changes]
*************** Starting PHASE Find loops
*************** In optFindLoopsPhase()
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
*************** Finishing PHASE Find loops
Trees after Find loops
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+----- \--* MUL long
[000001] -----+-N--- +--* CAST long <- int
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N--- \--* CAST long <- int
[000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Repair profile post-morph
No PGO data. Skipping profile repair.
*************** Finishing PHASE Repair profile post-morph [no changes]
*************** Starting PHASE Set block weights
After computing the dominance tree:
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
Return blocks: BB01
*************** Finishing PHASE Set block weights [no changes]
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
No loops to clone
*************** Finishing PHASE Clone loops [no changes]
*************** Starting PHASE Unroll loops
*************** Finishing PHASE Unroll loops [no changes]
*************** Starting PHASE Compute dominators
*************** Finishing PHASE Compute dominators [no changes]
*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function
*************** Finishing PHASE Morph array ops [no changes]
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1)
STMT00000 ( 0x000[E-] ... 0x005 )
[000005] -----+----- * RETURN long
[000004] L----+----- \--* MUL long
[000001] -----+-N--- +--* CAST long <- int
[000000] -----+----- | \--* LCL_VAR int V00 arg0
[000003] -----+-N--- \--* CAST long <- int
[000002] -----+----- \--* LCL_VAR int V01 arg1
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
*************** Finishing PHASE Mark local vars [no changes]
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
Trees after Find oper order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
( 16, 13) [000005] -----+----- * RETURN long
( 15, 12) [000004] L----+----- \--* MUL long
( 2, 3) [000001] -----+-N--- +--* CAST long <- int
( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0
( 2, 3) [000003] -----+-N--- \--* CAST long <- int
( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 6 tree nodes
*************** Finishing PHASE Set block order
Trees after Set block order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
N006 ( 16, 13) [000005] -----+----- * RETURN long
N005 ( 15, 12) [000004] L----+----- \--* MUL long
N002 ( 2, 3) [000001] -----+-N--- +--* CAST long <- int
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0
N004 ( 2, 3) [000003] -----+-N--- \--* CAST long <- int
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Tracked variable (2 out of 2) table:
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3
V01 arg1 [ int]: refCnt = 3, refCntWtd = 3
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V00 V01}
DEF(0)={ }
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (2)={V00 V01}
OUT(0)={ }
*************** In optRemoveRedundantZeroInits()
Analyzing BB01
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
V00.1: defined in BB00 1 uses (global)
V01.1: defined in BB00 1 uses (global)
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
N006 ( 16, 13) [000005] -----+----- * RETURN long
N005 ( 15, 12) [000004] L----+----- \--* MUL long
N002 ( 2, 3) [000001] -----+-N--- +--* CAST long <- int
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use)
N004 ( 2, 3) [000003] -----+-N--- \--* CAST long <- int
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use)
SSA MEM: ByrefExposed, GcHeap = m:1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
[info] HasGlobalUse overestimated for V01.1
SSA checks completed successfully
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method
*************** Finishing PHASE Early Value Propagation [no changes]
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
Visiting BB01
The SSA definition for ByrefExposed (#1) at start of BB01 is $c0 {InitVal($42)}
The SSA definition for GcHeap (#1) at start of BB01 is $c0 {InitVal($42)}
***** BB01, STMT00000(before)
N006 ( 16, 13) [000005] -----+----- * RETURN long
N005 ( 15, 12) [000004] L----+----- \--* MUL long
N002 ( 2, 3) [000001] -----+-N--- +--* CAST long <- int
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use)
N004 ( 2, 3) [000003] -----+-N--- \--* CAST long <- int
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use)
N001 [000000] LCL_VAR V00 arg0 u:1 (last use) => $80 {InitVal($40)}
N002 [000001] CAST => $100 {$80, long <- int}
N003 [000002] LCL_VAR V01 arg1 u:1 (last use) => $81 {InitVal($41)}
N004 [000003] CAST => $101 {$81, long <- int}
N005 [000004] MUL => $102 {MUL($100, $101)}
N006 [000005] RETURN => $VN.Void
***** BB01, STMT00000(after)
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
N005 ( 15, 12) [000004] L----+----- \--* MUL long $102
N002 ( 2, 3) [000001] -----+-N--- +--* CAST long <- int $100
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use) $80
N004 ( 2, 3) [000003] -----+-N--- \--* CAST long <- int $101
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use) $81
*************** Finishing PHASE Do value numbering
Trees after Do value numbering
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
N005 ( 15, 12) [000004] L----+----- \--* MUL long $102
N002 ( 2, 3) [000001] -----+-N--- +--* CAST long <- int $100
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use) $80
N004 ( 2, 3) [000003] -----+-N--- \--* CAST long <- int $101
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use) $81
SSA MEM: ByrefExposed, GcHeap = m:1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[info] HasGlobalUse overestimated for V00.1
[info] HasGlobalUse overestimated for V01.1
SSA checks completed successfully
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Hoist loop code
No loops; no hoisting
*************** Finishing PHASE Hoist loop code [no changes]
*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
curSsaName stack: { }
Live vars after [000000]: {V00 V01} -{V00} => {V01}
Live vars after [000002]: {V01} -{V01} => {}
orig [000002] copy [000000] VNs proved equivalent
*************** Finishing PHASE VN based copy prop [no changes]
*************** Starting PHASE Redundant branch opts
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Redundant branch opts [no changes]
*************** Starting PHASE Optimize Valnum CSEs
CONST CSE is disabled
Standard CSE Heuristic
Standard CSE Heuristic
*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x005 )
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
N005 ( 15, 12) [000004] L----+----- \--* MUL long $102
N002 ( 2, 3) [000001] -----+-N--- +--* CAST long <- int $100
N001 ( 1, 1) [000000] -----+----- | \--* LCL_VAR int V00 arg0 u:1 (last use) $80
N004 ( 2, 3) [000003] -----+-N--- \--* CAST long <- int $101
N003 ( 1, 1) [000002] -----+----- \--* LCL_VAR int V01 arg1 u:1 (last use) $81
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Assertion prop
*************** Finishing PHASE Assertion prop [no changes]
*************** Starting PHASE Optimize index checks
*************** Finishing PHASE Optimize index checks [no changes]
*************** Starting PHASE Optimize Induction Variables
*************** In optInductionVariables()
Skipping since this method has no natural loops
*************** Finishing PHASE Optimize Induction Variables [no changes]
*************** Starting PHASE VN-based dead store removal
*************** Finishing PHASE VN-based dead store removal [no changes]
*************** Starting PHASE Clone blocks with range checks
Current method has no bounds checks
*************** Finishing PHASE Clone blocks with range checks [no changes]
*************** Starting PHASE VN based intrinsic expansion
*************** Finishing PHASE VN based intrinsic expansion [no changes]
Removing PHI functions
*************** Starting PHASE Stress gtSplitTree
*************** Finishing PHASE Stress gtSplitTree [no changes]
*************** Starting PHASE Remove empty finally 3
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally 3 [no changes]
*************** Starting PHASE Remove empty try 3
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try 3 [no changes]
*************** Starting PHASE Remove empty try-catch-fault 3
*************** In fgRemoveEmptyTryCatchOrTryFault()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try-catch-fault 3 [no changes]
*************** Starting PHASE Create EH funclets
*************** Finishing PHASE Create EH funclets [no changes]
*************** Starting PHASE Expand casts
*************** Finishing PHASE Expand casts [no changes]
*************** Starting PHASE Expand runtime lookups
*************** Finishing PHASE Expand runtime lookups [no changes]
*************** Starting PHASE Expand static init
Nothing to expand.
*************** Finishing PHASE Expand static init [no changes]
*************** Starting PHASE Expand TLS access
Nothing to expand.
*************** Finishing PHASE Expand TLS access [no changes]
*************** Starting PHASE Expand stack array allocation
*************** Finishing PHASE Expand stack array allocation [no changes]
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Create throw helper blocks
*************** Finishing PHASE Create throw helper blocks [no changes]
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
optimized 0 BBJ_COND cases in 1 passes
*************** Finishing PHASE Optimize bools [no changes]
*************** Starting PHASE If conversion
*************** Finishing PHASE If conversion [no changes]
*************** Starting PHASE Recognize Switch
*************** Finishing PHASE Recognize Switch [no changes]
*************** Starting PHASE Optimize pre-layout
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** Finishing PHASE Optimize pre-layout [no changes]
*************** Starting PHASE Repair profile pre-layout
No PGO data. Skipping profile repair.
*************** Finishing PHASE Repair profile pre-layout [no changes]
*************** Starting PHASE Rationalize IR
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
[000006] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
/--* t0 int
N002 ( 2, 3) [000001] -----+-N--- t1 = * CAST long <- int $100
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t2 int
N004 ( 2, 3) [000003] -----+-N--- t3 = * CAST long <- int $101
/--* t1 long
+--* t3 long
N005 ( 15, 12) [000004] L----+----- t4 = * MUL long $102
/--* t4 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Lowering nodeinfo
lvaTable after PromoteLongVars
; Initial local variable assignments
;
; V00 arg0 int single-def
; V01 arg1 int single-def
0 parameter register to local mappings
Decomposing TYP_LONG tree. BEFORE:
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
/--* t0 int
N002 ( 2, 3) [000001] -----+-N--- t1 = * CAST long <- int $100
Decomposing TYP_LONG tree. AFTER:
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
/--* t0 int
N002 ( 2, 3) [000001] -----+-N--- t1 = * CAST long <- int $100
Decomposing TYP_LONG tree. BEFORE:
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t2 int
N004 ( 2, 3) [000003] -----+-N--- t3 = * CAST long <- int $101
Decomposing TYP_LONG tree. AFTER:
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t2 int
N004 ( 2, 3) [000003] -----+-N--- t3 = * CAST long <- int $101
Decomposing TYP_LONG tree. BEFORE:
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
/--* t0 int
N002 ( 2, 3) [000001] -----+-N--- t1 = * CAST long <- int $100
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t2 int
N004 ( 2, 3) [000003] -----+-N--- t3 = * CAST long <- int $101
/--* t1 long
+--* t3 long
N005 ( 15, 12) [000004] L----+----- t4 = * MUL long $102
lvaGrabTemp returning 2 (V02 rat0) called for ReplaceWithLclVar is creating a new local variable.
ReplaceWithLclVar created store :
[000007] DA--------- * STORE_LCL_VAR long V02 rat0
Promoting long local V02:
lvaGrabTemp returning 3 (V03 rat1) (a long lifetime temp) called for field V02.lo (fldOffset=0x0).
lvaGrabTemp returning 4 (V04 rat2) (a long lifetime temp) called for field V02.hi (fldOffset=0x4).
Decomposing TYP_LONG tree. AFTER:
[000008] ----------- t8 = LCL_VAR int V03 rat1
[000009] ----------- t9 = LCL_VAR int V04 rat2
/--* t8 int
+--* t9 int
[000010] ----------- t10 = * LONG long
Decomposing TYP_LONG tree. BEFORE:
[000008] ----------- t8 = LCL_VAR int V03 rat1
[000009] ----------- t9 = LCL_VAR int V04 rat2
/--* t8 int
+--* t9 int
[000010] ----------- t10 = * LONG long
/--* t10 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
Decomposing TYP_LONG tree. AFTER:
[000008] ----------- t8 = LCL_VAR int V03 rat1
[000009] ----------- t9 = LCL_VAR int V04 rat2
/--* t8 int
+--* t9 int
[000010] ----------- t10 = * LONG long
/--* t10 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t0 int
+--* t2 int
N005 ( 15, 12) [000004] L----+----- t4 = * MUL_LONG long
/--* t4 long
[000007] DA--------- * STORE_LCL_VAR long (P) V02 rat0
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2
lowering store lcl var/field (after):
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t0 int
+--* t2 int
N005 ( 15, 12) [000004] L----+----- t4 = * MUL_LONG long
/--* t4 long
[000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2
lowering return node
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
============
Lower has completed modifying nodes.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
[000006] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t0 int
+--* t2 int
N005 ( 15, 12) [000004] L----+----- t4 = * MUL_LONG long
/--* t4 long
[000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2
[000008] ----------- t8 = LCL_VAR int V03 rat1
[000009] ----------- t9 = LCL_VAR int V04 rat2
/--* t8 int
+--* t9 int
[000010] -c--------- t10 = * LONG long
/--* t10 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V03: refCnt = 1, refCntWtd = 2
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 1, refCntWtd = 2
New refCnts for V03: refCnt = 2, refCntWtd = 3
New refCnts for V04: refCnt = 2, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 int single-def
; V01 arg1 int single-def
; V02 rat0 long multireg-ret multireg-dest "ReplaceWithLclVar is creating a new local variable"
; V03 rat1 int "field V02.lo (fldOffset=0x0)" P-INDEP
; V04 rat2 int "field V02.hi (fldOffset=0x4)" P-INDEP
In fgLocalVarLivenessInit
Tracked variable (4 out of 5) table:
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3
V01 arg1 [ int]: refCnt = 3, refCntWtd = 3
V03 rat1 [ int]: refCnt = 2, refCntWtd = 3
V04 rat2 [ int]: refCnt = 2, refCntWtd = 3
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(2)={V00 V01 }
DEF(2)={ V03 V04}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (2)={V00 V01}
OUT(0)={ }
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V03: refCnt = 1, refCntWtd = 2
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 1, refCntWtd = 2
New refCnts for V03: refCnt = 2, refCntWtd = 3
New refCnts for V04: refCnt = 2, refCntWtd = 3
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
[000006] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 (last use) $80
N003 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 (last use) $81
/--* t0 int
+--* t2 int
N005 ( 15, 12) [000004] L----+----- t4 = * MUL_LONG long
/--* t4 long
[000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2
[000008] ----------- t8 = LCL_VAR int V03 rat1 (last use)
[000009] ----------- t9 = LCL_VAR int V04 rat2 (last use)
/--* t8 int
+--* t9 int
[000010] -c--------- t10 = * LONG long
/--* t10 long
N006 ( 16, 13) [000005] -----+----- * RETURN long $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01
use: {V00 V01}
def: {V03 V04}
in: {V00 V01}
out: {}
Interval 0: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 0: (V00) int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 1: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 1: (V01) int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 2: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 2: (V03) int (field) RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 3: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Interval 3: (V04) int (field) RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
Double alignment:
Bytes that could be saved by not using EBP frame: 9
Sum of weighted ref counts for EBP enregistered variables: 150.000000
Sum of weighted ref counts for weighted stack based doubles: 0.000000
Predicting not to double-align ESP to save 9 bytes of code.
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = false, singleExit = true
TUPLE STYLE DUMP BEFORE LSRA
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
Start LSRA Block Sequence:
Current block: BB01
Final LSRA Block Sequence:
BB01 ( 1 )
BB01 [0000] [000..006) (return), preds={} succs={}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. V00(t0*)
N003. V01(t2*)
N005. t4 = MUL_LONG ; t0*,t2*
N000. V02 MEM; t4
N000. V03(t8*)
N000. V04(t9*)
N000. t10 = LONG ; t8*,t9*
N006. RETURN ; t10
buildIntervals second part ========
Arg V00 is live in reg ecx
Arg V01 is live in reg edx
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed wt=100.00>
NEW BLOCK BB01
<RefPosition #2 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
DefList: { }
N003 (???,???) [000006] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N005 ( 1, 1) [000000] -----+----- * LCL_VAR int V00 arg0 u:1 NA (last use) REG NA $80
DefList: { }
N007 ( 1, 1) [000002] -----+----- * LCL_VAR int V01 arg1 u:1 NA (last use) REG NA $81
DefList: { }
N009 ( 15, 12) [000004] L----+----- * MUL_LONG long REG NA,NA
<RefPosition #3 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #4 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #5 @10 RefTypeKill BB01 regmask=[eax edx] minReg=1>
Interval 4: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
<RefPosition #6 @10 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #7 @10 RefTypeDef <Ivl:4> MUL_LONG[0] BB01 regmask=[eax] minReg=1 fixed wt=400.00>
Assigning related <I4> to <V00/L0>
Assigning related <I4> to <V01/L1>
Interval 5: int RefPositions {} physReg:NA Preferences=[allInt] Aversions=[]
<RefPosition #8 @10 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #9 @10 RefTypeDef <Ivl:5> MUL_LONG[1] BB01 regmask=[edx] minReg=1 fixed wt=400.00>
Interval <V00/L0> already has a related interval
Interval <V01/L1> already has a related interval
DefList: { N009.t4. MUL_LONG; N009.t4. MUL_LONG }
N011 (???,???) [000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0 NA
* int field V02.lo (fldOffset=0x0) -> V03 rat1
* int field V02.hi (fldOffset=0x4) -> V04 rat2 REG NA,NA
<RefPosition #10 @11 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V03/L2> to <I4>
<RefPosition #11 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 last wt=400.00>
<RefPosition #12 @13 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
Assigning related <V04/L3> to <I5>
<RefPosition #13 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 last wt=400.00>
DefList: { }
N015 (???,???) [000008] ----------- * LCL_VAR int V03 rat1 NA (last use) REG NA
DefList: { }
N017 (???,???) [000009] ----------- * LCL_VAR int V04 rat2 NA (last use) REG NA
DefList: { }
N019 (???,???) [000010] -c--------- * LONG long REG NA
Contained
DefList: { }
N021 ( 16, 13) [000005] -----+----- * RETURN long REG NA $VN.Void
<RefPosition #14 @21 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #15 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
<RefPosition #16 @21 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #17 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
CHECKING LAST USES for BB01, liveout={}
==============================
use: {V00 V01}
def: {V03 V04}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) int RefPositions {#0@0 #3@9} physReg:ecx Preferences=[ecx] Aversions=[] RelatedInterval <I4>
Interval 1: (V01) int RefPositions {#1@0 #4@9} physReg:edx Preferences=[edx] Aversions=[] RelatedInterval <I4>
Interval 2: (V03) int (field) RefPositions {#11@12 #15@21} physReg:NA Preferences=[eax] Aversions=[]
Interval 3: (V04) int (field) RefPositions {#13@14 #17@21} physReg:NA Preferences=[edx] Aversions=[]
Interval 4: int RefPositions {#7@10 #10@11} physReg:NA Preferences=[eax] Aversions=[] RelatedInterval <V03/L2>
Interval 5: int RefPositions {#9@10 #12@13} physReg:NA Preferences=[edx] Aversions=[] RelatedInterval <V04/L3>
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #4 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
<RefPosition #5 @10 RefTypeKill BB01 regmask=[eax edx] minReg=1>
<RefPosition #6 @10 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #7 @10 RefTypeDef <Ivl:4> MUL_LONG[0] BB01 regmask=[eax] minReg=1 fixed wt=400.00>
<RefPosition #8 @10 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #9 @10 RefTypeDef <Ivl:5> MUL_LONG[1] BB01 regmask=[edx] minReg=1 fixed wt=400.00>
<RefPosition #10 @11 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #11 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #12 @13 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #13 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #14 @21 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #15 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
<RefPosition #16 @21 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #17 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
------------
REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval)
------------
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
-----------------
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
-----------------
<RefPosition #11 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #15 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
-----------------
<RefPosition #13 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #17 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00 V01
BB01 [0000] [000..006) (return), preds={} succs={}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V00(L0)
N007. V01(L1)
N009. MUL_LONG
Use:<V00/L0>(#3) *
Use:<V01/L1>(#4) *
Kill: [eax edx]
Def:<I4>(#7) eax Pref:<V03/L2>
Def:<I5>(#9) edx Pref:<V04/L3>
N011. V02 MEM
Use:<I4>(#10) *
Def:<V03/L2>(#11)
N015. V03(L2)
N017. V04(L3)
N019. LONG
N021. RETURN
Linear scan intervals after buildIntervals:
Interval 0: (V00) int RefPositions {#0@0 #3@9} physReg:ecx Preferences=[ecx] Aversions=[] RelatedInterval <I4>
Interval 1: (V01) int RefPositions {#1@0 #4@9} physReg:edx Preferences=[edx] Aversions=[] RelatedInterval <I4>
Interval 2: (V03) int (field) RefPositions {#11@12 #15@21} physReg:NA Preferences=[eax] Aversions=[]
Interval 3: (V04) int (field) RefPositions {#13@14 #17@21} physReg:NA Preferences=[edx] Aversions=[]
Interval 4: int RefPositions {#7@10 #10@11} physReg:NA Preferences=[eax] Aversions=[] RelatedInterval <V03/L2>
Interval 5: int RefPositions {#9@10 #12@13} physReg:NA Preferences=[edx] Aversions=[] RelatedInterval <V04/L3>
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) int RefPositions {#0@0 #3@9} physReg:ecx Preferences=[ecx] Aversions=[] RelatedInterval <I4>
Interval 1: (V01) int RefPositions {#1@0 #4@9} physReg:edx Preferences=[edx] Aversions=[] RelatedInterval <I4>
Interval 2: (V03) int (field) RefPositions {#11@12 #15@21} physReg:NA Preferences=[eax] Aversions=[]
Interval 3: (V04) int (field) RefPositions {#13@14 #17@21} physReg:NA Preferences=[edx] Aversions=[]
Interval 4: int RefPositions {#7@10 #10@11} physReg:NA Preferences=[eax] Aversions=[] RelatedInterval <V03/L2>
Interval 5: int RefPositions {#9@10 #12@13} physReg:NA Preferences=[edx] Aversions=[] RelatedInterval <V04/L3>
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
<RefPosition #4 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
<RefPosition #5 @10 RefTypeKill BB01 regmask=[eax edx] minReg=1>
<RefPosition #6 @10 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #7 @10 RefTypeDef <Ivl:4> MUL_LONG[0] BB01 regmask=[eax] minReg=1 fixed wt=400.00>
<RefPosition #8 @10 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #9 @10 RefTypeDef <Ivl:5> MUL_LONG[1] BB01 regmask=[edx] minReg=1 fixed wt=400.00>
<RefPosition #10 @11 RefTypeUse <Ivl:4> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #11 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #12 @13 RefTypeUse <Ivl:5> BB01 regmask=[allInt] minReg=1 last wt=100.00>
<RefPosition #13 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #14 @21 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #15 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
<RefPosition #16 @21 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #17 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional wt=300.00>
--- V02
--- V03 (Interval 2)
<RefPosition #11 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #15 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
--- V04 (Interval 3)
<RefPosition #13 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[allInt] minReg=1 wt=400.00>
<RefPosition #17 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.
------------------------------------------+----+----+----+----+
TreeID LocRP# Name Type Action Reg |eax |ecx |edx |edi |
------------------------------------------+----+----+----+----+
| |V00a|V01a| |
0.#0 V00 Parm Keep ecx | |V00a|V01a| |
0.#1 V01 Parm Keep edx | |V00a|V01a| |
1.#2 BB1 PredBB0 | |V00a|V01a| |
[000004] 9.#3 V00 Use * Keep ecx | |V00a|V01a| |
9.#4 V01 Use * Keep edx | |V00a|V01a| |
10.#5 Kill None [eax edx]
| | | | |
10.#6 eax Fixd Keep eax | | | | |
10.#7 I4 Def Alloc eax |I4 a| | | |
10.#8 edx Fixd Keep edx |I4 a| | | |
10.#9 I5 Def Alloc edx |I4 a| |I5 a| |
[000007] 11.#10 I4 Use * Keep eax |I4 a| |I5 a| |
12.#11 V03 Def COVRS(A) eax |V03a| |I5 a| |
13.#12 I5 Use * Keep edx |V03a| |I5 a| |
14.#13 V04 Def COVRS(A) edx |V03a| |V04a| |
[000005] 21.#14 eax Fixd Keep eax |V03a| |V04a| |
21.#15 V03 Use * Keep eax |V03a| |V04a| |
21.#16 edx Fixd Keep edx |V03a| |V04a| |
21.#17 V04 Use * Keep edx | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #2 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ecx] minReg=1 last wt=300.00>
<RefPosition #4 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[edx] minReg=1 last regOptional wt=300.00>
<RefPosition #5 @10 RefTypeKill BB01 regmask=[eax edx] minReg=1>
<RefPosition #6 @10 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #7 @10 RefTypeDef <Ivl:4> MUL_LONG[0] BB01 regmask=[eax] minReg=1 fixed wt=400.00>
<RefPosition #8 @10 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #9 @10 RefTypeDef <Ivl:5> MUL_LONG[1] BB01 regmask=[edx] minReg=1 fixed wt=400.00>
<RefPosition #10 @11 RefTypeUse <Ivl:4> BB01 regmask=[eax] minReg=1 last wt=100.00>
<RefPosition #11 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[eax] minReg=1 wt=400.00>
<RefPosition #12 @13 RefTypeUse <Ivl:5> BB01 regmask=[edx] minReg=1 last wt=100.00>
<RefPosition #13 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[edx] minReg=1 wt=400.00>
<RefPosition #14 @21 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax] minReg=1 wt=100.00>
<RefPosition #15 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
<RefPosition #16 @21 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx] minReg=1 wt=100.00>
<RefPosition #17 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #3 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ecx] minReg=1 last wt=300.00>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[edx] minReg=1 fixed regOptional wt=100.00>
<RefPosition #4 @9 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[edx] minReg=1 last regOptional wt=300.00>
--- V02
--- V03 (Interval 2)
<RefPosition #11 @12 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR[0] BB01 regmask=[eax] minReg=1 wt=400.00>
<RefPosition #15 @21 RefTypeUse <Ivl:2 V03> LCL_VAR BB01 regmask=[eax] minReg=1 last fixed wt=300.00>
--- V04 (Interval 3)
<RefPosition #13 @14 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR[1] BB01 regmask=[edx] minReg=1 wt=400.00>
<RefPosition #17 @21 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[edx] minReg=1 last fixed wt=300.00>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V01}
Has No Critical Edges
Prior to Resolution
BB01
use: {V00 V01}
def: {V03 V04}
in: {V00 V01}
out: {}
Var=Reg beg of BB01: V00=ecx V01=edx
Var=Reg end of BB01: none
RESOLVING EDGES
Set V00 argument initial register to ecx
Set V01 argument initial register to edx
Trees after linear scan register allocator (LSRA)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
N003 (???,???) [000006] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 ecx (last use) REG ecx $80
N007 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 edx (last use) REG edx $81
/--* t0 int
+--* t2 int
N009 ( 15, 12) [000004] L----+----- t4 = * MUL_LONG long REG eax,edx
/--* t4 long
N011 (???,???) [000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0 eax
* int field V02.lo (fldOffset=0x0) -> V03 rat1 eax
* int field V02.hi (fldOffset=0x4) -> V04 rat2 edx REG eax,edx
N015 (???,???) [000008] ----------- t8 = LCL_VAR int V03 rat1 eax (last use) REG eax
N017 (???,???) [000009] ----------- t9 = LCL_VAR int V04 rat2 edx (last use) REG edx
/--* t8 int
+--* t9 int
N019 (???,???) [000010] -c--------- t10 = * LONG long REG NA
/--* t10 long
N021 ( 16, 13) [000005] -----+----- * RETURN long REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------------------+----+----+----+----+
TreeID LocRP# Name Type Action Reg |eax |ecx |edx |edi |
------------------------------------------+----+----+----+----+
0.#0 V00 Parm Alloc ecx | |V00a| | |
0.#1 V01 Parm Alloc edx | |V00a|V01a| |
1.#2 BB1 PredBB0 | |V00a|V01a| |
[000004] 9.#3 V00 Use * Keep ecx | |V00i|V01a| |
9.#4 V01 Use * Keep edx | | |V01i| |
10.#5 Kill None [eax edx]
| | | | |
10.#6 eax Fixd Keep eax | | | | |
10.#7 I4 Def Alloc eax |I4 a| | | |
10.#8 edx Fixd Keep edx |I4 a| | | |
10.#9 I5 Def Alloc edx |I4 a| |I5 a| |
[000007] 11.#10 I4 Use * Keep eax |I4 i| |I5 a| |
12.#11 V03 Def Alloc eax |V03a| |I5 a| |
13.#12 I5 Use * Keep edx |V03a| |I5 i| |
14.#13 V04 Def Alloc edx |V03a| |V04a| |
[000005] 21.#14 eax Fixd Keep eax |V03a| |V04a| |
21.#15 V03 Use * Keep eax |V03i| |V04a| |
21.#16 edx Fixd Keep edx | | |V04a| |
21.#17 V04 Use * Keep edx | | |V04i| |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars: 4
Total Reg Cand Vars: 4
Total number of Intervals: 5
Total number of RefPositions: 17
Total Number of spill temps created: 0
..........
BB01 [ 100.00]: COVERS = 2
..........
Total SpillCount : 0 Weighted: 0.000000
Total CopyReg : 0 Weighted: 0.000000
Total ResolutionMovs : 0 Weighted: 0.000000
Total SplitEdges : 0 Weighted: 0.000000
..........
Total COVERS [# 4] : 2 Weighted: 200.000000
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(ecx) V01(edx)
BB01 [0000] [000..006) (return), preds={} succs={}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. V00(ecx*)
N007. V01(edx*)
N009. eax,edx = MUL_LONG ; ecx*,edx*
* N011. eax,edx = V02 MEM; eax,edx
N015. V03(eax*)
N017. V04(edx*)
N019. STK = LONG ; eax*,edx*
N021. RETURN ; STK
Var=Reg end of BB01: none
*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..006) (return), preds={} succs={}
N003 (???,???) [000006] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 ecx (last use) REG ecx $80
N007 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 edx (last use) REG edx $81
/--* t0 int
+--* t2 int
N009 ( 15, 12) [000004] L----+----- t4 = * MUL_LONG long REG eax,edx
/--* t4 long
N011 (???,???) [000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0 eax
* int field V02.lo (fldOffset=0x0) -> V03 rat1 eax
* int field V02.hi (fldOffset=0x4) -> V04 rat2 edx REG eax,edx
N015 (???,???) [000008] ----------- t8 = LCL_VAR int V03 rat1 eax (last use) REG eax
N017 (???,???) [000009] ----------- t9 = LCL_VAR int V04 rat2 edx (last use) REG edx
/--* t8 int
+--* t9 int
N019 (???,???) [000010] -c--------- t10 = * LONG long REG NA
/--* t10 long
N021 ( 16, 13) [000005] -----+----- * RETURN long REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]
*************** Starting PHASE Optimize layout
*************** In fgSearchImprovedLayout()
Initial BasicBlocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Not enough blocks to partition anything. Skipping reordering.
Reordering block list
*************** Finishing PHASE Optimize layout [no changes]
*************** Starting PHASE Optimize post-layout
*************** Finishing PHASE Optimize post-layout [no changes]
*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block [no changes]
*************** Starting PHASE Place 'align' instructions
*************** In placeLoopAlignInstructions()
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
Not checking for any loops as fgMightHaveNaturalLoops is false
*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(ecx) V01(edx)
Modified regs: [eax ecx edx]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V02 rat0, size=8, stkOffs=-0xc
--- delta bump 4 for RA
--- delta bump 8 for RSP frame
--- virtual stack offset to actual stack offset delta is 12
-- V02 was -12, now 0
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 3, 3 ) int -> ecx single-def
; V01 arg1 [V01,T01] ( 3, 3 ) int -> edx single-def
; V02 rat0 [V02 ] ( 1, 2 ) long -> [esp+0x00] multireg-ret multireg-dest "ReplaceWithLclVar is creating a new local variable"
; V03 rat1 [V03,T02] ( 2, 3 ) int -> eax "field V02.lo (fldOffset=0x0)" P-INDEP
; V04 rat2 [V04,T03] ( 2, 3 ) int -> edx "field V02.hi (fldOffset=0x4)" P-INDEP
;
; Lcl frame size = 8
Created:
G_M46882_IG02: ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=00000000 {}
Mark labels for codegen
BB01 : first block
*************** After genMarkLabelsForCodegen()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..006) (return) i LIR label
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
=============== Generating BB01 [0000] [000..006) (return), preds={} succs={} flags=0x00000000.00001011: i LIR label
BB01 IN (2)={V00 V01}
OUT(0)={ }
Recording Var Locations at start of BB01
V00(ecx) V01(edx)
Change life 0000000000000000 {} -> 0000000000000003 {V00 V01}
V00 in reg ecx is becoming live [------]
Live regs: 00000000 {} + {ecx} => 00000002 {ecx}
Debug: New V00 debug range: first
V01 in reg edx is becoming live [------]
Live regs: 00000002 {ecx} + {edx} => 00000006 {ecx edx}
Debug: New V01 debug range: first
Live regs: (unchanged) 00000006 {ecx edx}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M46882_BB01:
Label: G_M46882_IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB01, IL range [000..006)
Added IP mapping: 0x0000 STACK_EMPTY (G_M46882_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000006] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N005 ( 1, 1) [000000] -----+----- t0 = LCL_VAR int V00 arg0 u:1 ecx (last use) REG ecx $80
Generating: N007 ( 1, 1) [000002] -----+----- t2 = LCL_VAR int V01 arg1 u:1 edx (last use) REG edx $81
/--* t0 int
+--* t2 int
Generating: N009 ( 15, 12) [000004] L----+----- t4 = * MUL_LONG long REG eax,edx
V00 in reg ecx is becoming dead [000000]
Live regs: 00000006 {ecx edx} - {ecx} => 00000004 {edx}
Debug: Closing V00 debug range.
Live vars after [000000]: {V00 V01} -{V00} => {V01}
V01 in reg edx is becoming dead [000002]
Live regs: 00000004 {edx} - {edx} => 00000000 {}
Debug: Closing V01 debug range.
Live vars after [000002]: {V01} -{V01} => {}
Mapped BB01 to G_M46882_IG02
IN0001: mov eax, ecx
IN0002: imul edx:eax, edx
/--* t4 long
Generating: N011 (???,???) [000007] MA--------- * STORE_LCL_VAR long (P) V02 rat0 eax
* int field V02.lo (fldOffset=0x0) -> V03 rat1 eax
* int field V02.hi (fldOffset=0x4) -> V04 rat2 edx REG eax,edx
V03 in reg eax is becoming live [000007]
Live regs: 00000000 {} + {eax} => 00000001 {eax}
V04 in reg edx is becoming live [000007]
Live regs: 00000001 {eax} + {edx} => 00000005 {eax edx}
Live vars after [000007]: {} +{V03 V04} => {V03 V04}
Generating: N015 (???,???) [000008] ----------- t8 = LCL_VAR int V03 rat1 eax (last use) REG eax
Generating: N017 (???,???) [000009] ----------- t9 = LCL_VAR int V04 rat2 edx (last use) REG edx
/--* t8 int
+--* t9 int
Generating: N019 (???,???) [000010] -c--------- t10 = * LONG long REG NA
/--* t10 long
Generating: N021 ( 16, 13) [000005] -----+----- * RETURN long REG NA $VN.Void
V03 in reg eax is becoming dead [000008]
Live regs: 00000005 {eax edx} - {eax} => 00000004 {edx}
Live vars after [000008]: {V03 V04} -{V03} => {V04}
V04 in reg edx is becoming dead [000009]
Live regs: 00000004 {edx} - {edx} => 00000000 {}
Live vars after [000009]: {V04} -{V04} => {}
Added IP mapping: EPILOG (G_M46882_IG02,ins#2,ofs#4) label
Reserving epilog IG for block BB01
Saved:
G_M46882_IG02: ; offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
Created:
G_M46882_IG03: ; offs=0x000004, size=0x0000, bbWeight=1, gcrefRegs=00000000 {}
*************** After placeholder IG creation
G_M46882_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=00000000 {} <-- Prolog IG
G_M46882_IG02: ; offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M46882_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Variable Live Range History Dump for BB01
V00 arg0: ecx [(G_M46882_IG02,ins#0,ofs#0), (G_M46882_IG02,ins#0,ofs#0)]
V01 arg1: edx [(G_M46882_IG02,ins#0,ofs#0), (G_M46882_IG02,ins#0,ofs#0)]
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 16, compSizeEstimate = 13 Program:<<Main>$>g__mul2s|0_14(int,int):long
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 3, 3 ) int -> ecx single-def
; V01 arg1 [V01,T01] ( 3, 3 ) int -> edx single-def
; V02 rat0 [V02 ] ( 1, 2 ) long -> [esp+0x00] multireg-ret multireg-dest "ReplaceWithLclVar is creating a new local variable"
; V03 rat1 [V03,T02] ( 2, 3 ) int -> eax "field V02.lo (fldOffset=0x0)" P-INDEP
; V04 rat2 [V04,T03] ( 2, 3 ) int -> edx "field V02.hi (fldOffset=0x4)" P-INDEP
;
; Lcl frame size = 8
*************** Before prolog / epilog generation
G_M46882_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=00000000 {} <-- Prolog IG
G_M46882_IG02: ; offs=0x000000, size=0x0004, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M46882_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
V00(ecx) V01(edx)
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M46882_IG01,ins#0,ofs#0) label
__prolog:
Debug: New V00 debug range: first
Debug: New V01 debug range: first
IN0003: sub esp, 8
*************** In genHomeRegisterParams()
2 registers in register parameter interference graph
ecx
edx
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Saved:
G_M46882_IG01: ; offs=0x000000, size=0x0003, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN0004: add esp, 8
IN0005: ret
Saved:
G_M46882_IG03: ; offs=0x000004, size=0x0004, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M46882_IG01: ; func=00, offs=0x000000, size=0x0003, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M46882_IG02: ; offs=0x000003, size=0x0004, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
G_M46882_IG03: ; offs=0x000007, size=0x0004, bbWeight=1, epilog, nogc, extend
*************** In emitJumpDistBind()
Emitter Jump List:
total jump count: 0
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0xB bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x4)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M46882_IG01: ; offs=0x000000, size=0x0003, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0003: 000000 sub esp, 8
;; size=3 bbWeight=1 PerfScore 0.25
G_M46882_IG02: ; offs=0x000003, size=0x0004, bbWeight=1, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
IN0001: 000003 mov eax, ecx
IN0002: 000005 imul edx:eax, edx
;; size=4 bbWeight=1 PerfScore 3.25
G_M46882_IG03: ; offs=0x000007, size=0x0004, bbWeight=1, epilog, nogc, extend
IN0004: 000007 add esp, 8
IN0005: 00000A ret
;; size=4 bbWeight=1 PerfScore 1.25
Allocated method code size = 11 , actual size = 11, unused size = 0
; Total bytes of code 11, prolog size 3, PerfScore 4.75, instruction count 5, allocated bytes for code 11 (MethodHash=2bf748dd) for method Program:<<Main>$>g__mul2s|0_14(int,int):long (FullOpts)
; ============================================================
*************** After end code gen, before unwindEmit()
G_M46882_IG01: ; func=00, offs=0x000000, size=0x0003, bbWeight=1, PerfScore 0.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0003: 000000 sub esp, 8
G_M46882_IG02: ; offs=0x000003, size=0x0004, bbWeight=1, PerfScore 3.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, BB01 [0000], byref
IN0001: 000003 mov eax, ecx
IN0002: 000005 imul edx:eax, edx
G_M46882_IG03: ; offs=0x000007, size=0x0004, bbWeight=1, PerfScore 1.25, epilog, nogc, extend
IN0004: 000007 add esp, 8
IN0005: 00000A ret
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
allocUnwindInfo(pHotCode=0x00007FFA293F45B0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0xb, unwindSize=0x4, pUnwindBlock=0x0000007DB0B7B630, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 3
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000003 ( STACK_EMPTY )
IL offs EPILOG : 0x00000007 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 4
; Variable debug info: 2 live ranges, 2 vars for method Program:<<Main>$>g__mul2s|0_14(int,int):long
(V00 arg0) : From 00000000h to 00000003h, in ecx
(V01 arg1) : From 00000000h to 00000003h, in edx
*************** In gcInfoBlockHdrSave()
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
*************** In gcInfoBlockHdrSave()
GCINFO: methodSize = 000B
GCINFO: prologSize = 0003
GCINFO: epilogSize = 0004
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
GC Info for method Program:<<Main>$>g__mul2s|0_14(int,int):long
GC info size = 6
Method info block:
method size = 000B
prolog size = 3
epilog size = 4
epilog count = 1
epilog end = yes
callee-saved regs =
ebp frame = no
fully interruptible= no
double align = no
arguments size = 0 DWORDs
stack frame size = 2 DWORDs
untracked count = 0
var ptr tab count = 0
epilog at 0007
0B B0 82 BB 3C |
Pointer table:
FF 00 06 ...|
*************** Finishing PHASE Emit GC+EH tables
Method code size: 11
Allocations for Program:<<Main>$>g__mul2s|0_14(int,int):long (MethodHash=2bf748dd)
count: 329, size: 41056, max = 3208
allocateMemory: 65536, nraUsed: 44192
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
ABI | 152 | 0.37%
AssertionProp | 6500 | 15.83%
ASTNode | 1744 | 4.25%
InstDesc | 2272 | 5.53%
ImpStack | 384 | 0.94%
BasicBlock | 336 | 0.82%
CallArgs | 0 | 0.00%
FlowEdge | 0 | 0.00%
DepthFirstSearch | 224 | 0.55%
Loops | 260 | 0.63%
TreeStatementList | 0 | 0.00%
SiScope | 0 | 0.00%
DominatorMemory | 128 | 0.31%
LSRA | 4708 | 11.47%
LSRA_Interval | 528 | 1.29%
LSRA_RefPosition | 1440 | 3.51%
Reachability | 40 | 0.10%
SSA | 320 | 0.78%
ValueNumber | 5424 | 13.21%
LvaTable | 1612 | 3.93%
UnwindInfo | 0 | 0.00%
hashBv | 40 | 0.10%
bitset | 32 | 0.08%
FixedBitVect | 16 | 0.04%
Generic | 686 | 1.67%
LocalAddressVisitor | 32 | 0.08%
FieldSeqStore | 0 | 0.00%
MemorySsaMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 1256 | 3.06%
GC | 24 | 0.06%
CorTailCallInfo | 0 | 0.00%
Inlining | 472 | 1.15%
ArrayStack | 0 | 0.00%
DebugInfo | 224 | 0.55%
DebugOnly | 8688 | 21.16%
Codegen | 2176 | 5.30%
LoopOpt | 0 | 0.00%
LoopClone | 0 | 0.00%
LoopUnroll | 0 | 0.00%
LoopHoist | 0 | 0.00%
LoopIVOpts | 0 | 0.00%
Unknown | 42 | 0.10%
RangeCheck | 0 | 0.00%
CopyProp | 424 | 1.03%
Promotion | 120 | 0.29%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 648 | 1.58%
ClassLayout | 0 | 0.00%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 104 | 0.25%
Pgo | 0 | 0.00%
MaskConversionOpt | 0 | 0.00%
TryRegionClone | 0 | 0.00%
Async | 0 | 0.00%
RangeCheckCloning | 0 | 0.00%
Final metrics:
ActualCodeBytes : 11
AllocatedHotCodeBytes : 11
AllocatedColdCodeBytes : 0
ReadOnlyDataBytes : 0
GCInfoBytes : 6
EHClauseCount : 0
PhysicallyPromotedFields : 0
LoopsFoundDuringOpts : 0
LoopsInverted : 0
LoopsCloned : 0
LoopsUnrolled : 0
LoopAlignmentCandidates : 0
LoopsAligned : 0
LoopsIVWidened : 0
WidenedIVs : 0
UnusedIVsRemoved : 0
LoopsMadeDownwardsCounted : 0
LoopsStrengthReduced : 0
VarsInSsa : 2
HoistedExpressions : 0
RedundantBranchesEliminated : 0
JumpThreadingsPerformed : 0
CseCount : 0
BasicBlocksAtCodegen : 1
PerfScore : 4.750000
BytesAllocated : 44192
ImporterBranchFold : 0
ImporterSwitchFold : 0
DevirtualizedCall : 0
DevirtualizedCallUnboxedEntry : 0
DevirtualizedCallRemovedBox : 0
GDV : 0
ClassGDV : 0
MethodGDV : 0
MultiGuessGDV : 0
ChainedGDV : 0
EnumeratorGDV : 0
InlinerBranchFold : 0
InlineAttempt : 0
InlineCount : 0
ProfileConsistentBeforeInline : 0
ProfileConsistentAfterInline : 0
ProfileConsistentBeforeMorph : 0
ProfileConsistentAfterMorph : 0
ProfileSynthesizedBlendedOrRepaired : 0
ProfileInconsistentInitially : 0
ProfileInconsistentResetLeave : 0
ProfileInconsistentImporterBranchFold : 0
ProfileInconsistentImporterSwitchFold : 0
ProfileInconsistentChainedGDV : 0
ProfileInconsistentScratchBB : 0
ProfileInconsistentInlinerBranchFold : 0
ProfileInconsistentInlineeScale : 0
ProfileInconsistentInlinee : 0
ProfileInconsistentNoReturnInlinee : 0
ProfileInconsistentMayThrowInlinee : 0
NewRefClassHelperCalls : 0
StackAllocatedRefClasses : 0
NewBoxedValueClassHelperCalls : 0
StackAllocatedBoxedValueClasses : 0
NewArrayHelperCalls : 0
StackAllocatedArrays : 0
LocalAssertionCount : 0
LocalAssertionOverflow : 0
MorphTrackedLocals : 2
MorphLocals : 2
EnumeratorGDVProvisionalNoEscape : 0
EnumeratorGDVCanCloneToEnsureNoEscape : 0
****** DONE compiling Program:<<Main>$>g__mul2s|0_14(int,int):long