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#![no_std] | |
#![no_main] | |
#![feature(type_alias_impl_trait)] | |
#[path = "../example_common.rs"] | |
mod example_common; | |
use embassy::executor::Spawner; | |
use embassy_nrf::gpio::{Level, Output, OutputDrive}; | |
use embassy_nrf::Peripherals; | |
use embassy_nrf::{interrupt, spim}; | |
use embedded_hal_1::spi::ErrorType; | |
use embedded_hal_async::spi::{ExclusiveDevice, SpiBus, SpiBusWrite, SpiDevice}; | |
use example_common::*; | |
#[embassy::main] | |
async fn main(_spawner: Spawner, p: Peripherals) { | |
info!("running!"); | |
let eth_rst = p.P0_13; | |
let eth_int = p.P0_12; | |
let eth_cs = p.P0_15; | |
let eth_sck = p.P0_20; | |
let eth_mosi = p.P0_22; | |
let eth_miso = p.P0_24; | |
let mut config = spim::Config::default(); | |
config.frequency = spim::Frequency::M1; | |
let irq = interrupt::take!(SPIM3); | |
let spim = spim::Spim::new(p.SPI3, irq, eth_sck, eth_miso, eth_mosi, config); | |
let cs = Output::new(eth_cs, Level::High, OutputDrive::Standard); | |
let spim = ExclusiveDevice::new(spim, cs); | |
let mut enc = Enc28j60 { spi: spim }; | |
enc.do_it().await.unwrap(); | |
} | |
#[derive(Debug, Clone, Copy)] | |
enum Enc28j60Error<SPI> { | |
Spi(SPI), | |
} | |
struct Enc28j60<SPI> { | |
spi: SPI, | |
} | |
impl<SPI> Enc28j60<SPI> | |
where | |
SPI: SpiDevice, | |
SPI::Bus: SpiBus, | |
{ | |
pub async fn do_it(&mut self) -> Result<(), Enc28j60Error<SPI::Error>> { | |
// Soft-reset | |
let mut tx = [0xFF]; | |
let res: Result<(), SPI::Error> = self | |
.spi | |
.transaction(|bus| async { | |
let res = bus.write(&tx).await; | |
(bus, res) | |
}) | |
.await; | |
res.map_err(Enc28j60Error::Spi)?; | |
cortex_m::asm::delay(100000); | |
let mut buf = [0b000_11101, 0]; | |
let res: Result<(), SPI::Error> = self | |
.spi | |
.transaction(|bus| async { | |
let res = bus.transfer_in_place(&mut buf).await; | |
(bus, res) | |
}) | |
.await; | |
res.map_err(Enc28j60Error::Spi)?; | |
info!("estat: {=[u8]:02x}", buf); | |
// Switch to bank 3 | |
let mut tx = [0b100_11111, 0b11]; | |
let res: Result<(), SPI::Error> = self | |
.spi | |
.transaction(|bus| async { | |
let res = bus.write(&tx).await; | |
(bus, res) | |
}) | |
.await; | |
res.map_err(Enc28j60Error::Spi)?; | |
// read EREVID | |
let mut buf = [0b000_10010, 0]; | |
let res: Result<(), SPI::Error> = self | |
.spi | |
.transaction(|bus| async { | |
let res = bus.transfer_in_place(&mut buf).await; | |
(bus, res) | |
}) | |
.await; | |
res.map_err(Enc28j60Error::Spi)?; | |
info!("erevid: {=[u8]:02x}", buf); | |
Ok(()) | |
} | |
} |
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