HD3Cube.c

#include <stdlib.h>
#include "stm32f1xx.h"

void TIM2_IRQHandler() {
	if (TIM2->SR & TIM_SR_UIF) {
		TIM2->SR &= ~TIM_SR_UIF;
		GPIOC->BSRR = GPIOC->ODR & GPIO_ODR_ODR13 ? GPIO_BSRR_BR13 : GPIO_BSRR_BS13;
	}
}

void hd3cTimerInit() {
	RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
	NVIC_EnableIRQ(TIM2_IRQn);
	
	TIM2->SR = 0;
	//Interrupt every 10 seconds
	TIM2->PSC = 36 * 1024 - 1;
	TIM2->ARR = 10 * 1024;
	TIM2->CR1 = TIM_CR1_CEN; //Enable Counter
	TIM2->DIER = TIM_DIER_UIE; //Enable Update Interrupt
}

void hd3cSysClockInit() {
	RCC->CR |= RCC_CR_HSEON; //Enable HSE
	while(!(RCC->CR & RCC_CR_HSERDY));
	
	RCC->CFGR = RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL9; //Config PLL
	RCC->CR |= RCC_CR_PLLON; //Enable PLL
	while (!(RCC->CR & RCC_CR_PLLRDY));
	
	FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY) | FLASH_ACR_LATENCY_2; //Flash Access Latency
	
	RCC->CFGR |= (RCC->CFGR & ~RCC_CFGR_HPRE) | RCC_CFGR_HPRE_DIV1; //AHB Clock Divider
	RCC->CFGR |= (RCC->CFGR & ~RCC_CFGR_PPRE1) | RCC_CFGR_PPRE1_DIV2; //APB1 Clock Divider
	RCC->CFGR |= (RCC->CFGR & ~RCC_CFGR_PPRE2) | RCC_CFGR_PPRE2_DIV1; //APB2 Clock Divider
	
	RCC->CFGR |= RCC_CFGR_SW_PLL; //PLL as System Clock Source
	while (!(RCC->CFGR & RCC_CFGR_SWS_PLL));
}

int main() {
	hd3cSysClockInit();
	hd3cTimerInit();
	while (1);
}