u-boot porting [Beagle Bone]

Template2

File Name: arch/arm/cpu/armv7/am33xx/emif4.c


int dram_init(void)
{
        /* dram_init must store complete ramsize in gd->ram_size */
        gd->ram_size = get_ram_size(
                        (void *)CONFIG_SYS_SDRAM_BASE,
                        CONFIG_MAX_RAM_BANK_SIZE);
        return 0;
}

-> DRAM (Dynamic Ram) Intilization.

#define CONFIG_MAX_RAM_BANK_SIZE        (1024 << 20)    /* 1GB */

//include/configs/am335x_evm.h:274:#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1

#define PHYS_DRAM_1                     0x80000000      /* DRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE           PHYS_DRAM_1
Reference : include/configs/am335x_evm.h


void dram_init_banksize(void)
{
        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
        gd->bd->bi_dram[0].size = gd->ram_size;
}

#define CONFIG_SYS_SDRAM_BASE           PHYS_DRAM_1
#define PHYS_DRAM_1                     0x80000000      /* DRAM Bank #1 */

->dram init banksize 


#if defined(CONFIG_SPL_BUILD)
static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;

static void config_vtp(void)
{
        writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
                        &vtpreg->vtp0ctrlreg);
        writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
                        &vtpreg->vtp0ctrlreg);
        writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
                        &vtpreg->vtp0ctrlreg);

        /* Poll for READY */
        while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
                        VTP_CTRL_READY)
                ;
                                                                                                                     48,67         54%
}

void config_ddr(unsigned int pll, unsigned int ioctrl,
                const struct ddr_data *data, const struct cmd_control *ctrl,
                const struct emif_regs *regs)
{
        enable_emif_clocks();
        ddr_pll_config(pll);
        config_vtp();
        config_cmd_ctrl(ctrl);

        config_ddr_data(0, data);
        config_ddr_data(1, data);

        config_io_ctrl(ioctrl);

        /* Set CKE to be controlled by EMIF/DDR PHY */
        writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);

        /* Program EMIF instance */
        config_ddr_phy(regs);
        set_sdram_timings(regs);
        config_sdram(regs);
}
#endif

-> arch/arm/include/asm/arch-am33xx/hardware.h:69:#define VTP0_CTRL_ADDR
  arch/arm/include/asm/arch-am33xx/hardware.h:72:#define DDR_CTRL_ADDR

  arch/arm/cpu/armv7/am33xx/emif4.c:69:	enable_emif_clocks();
  arch/arm/include/asm/arch-am33xx/sys_proto.h:34:void ddr_pll_config(unsigned int ddrpll_M);
  arch/arm/cpu/armv7/am33xx/emif4.c:50:static void config_vtp(void)
  arch/arm/cpu/armv7/am33xx/ddr.c:109:void config_ddr_data(int macrono, const struct ddr_data *data)

DDR initilization done in template2 file