add_pipe.v

module add_pipe #(
	parameter WIDTH = 64,
	parameter SLICE_WIDTH = 16,
) (
	input clk,
	input carry_in,
	input [0 +: WIDTH] x, y,
	output [0 +: WIDTH] z,
	output carry_out,
);

	/* round up */
	localparam SLICES = (WIDTH + SLICE_WIDTH - 1) / SLICE_WIDTH;
	localparam EXTRA_WIDTH = WIDTH - (SLICE_WIDTH * (SLICES - 1));
	
	reg [0 +: SLICE_WIDTH + 1] sum[0 +: SLICES - 1][0 +: SLICES - 1];
	reg [0 +: EXTRA_WIDTH + 1] extra[0 +: SLICES - 1];

	genvar i, j;
	for (j = 0; j < SLICES - 1; j = j + 1) begin: add_slice
		if (j == 0) begin: add_carry
			always @(posedge clk)
				sum[0][j] <= x[j * SLICE_WIDTH +: SLICE_WIDTH] + y[j * SLICE_WIDTH +: SLICE_WIDTH] + carry_in;
		end else begin: add
			always @(posedge clk)
				sum[0][j] <= x[j * SLICE_WIDTH +: SLICE_WIDTH] + y[j * SLICE_WIDTH +: SLICE_WIDTH];
		end
	end

	always @(posedge clk)
		extra[0] <= x[WIDTH - 1 -: EXTRA_WIDTH] + y[WIDTH - 1 -: EXTRA_WIDTH];

	for (i = 1; i < SLICES - 1; i = i + 1) begin: stage
		for (j = 0; j < SLICES - 1; j = j + 1) begin: slice
			if (i == j) begin: carry
				always @(posedge clk)
					sum[i][j] <= sum[i - 1][j] + sum[i - 1][j - 1][SLICE_WIDTH];
			end else begin: store
				always @(posedge clk)
					sum[i][j] <= sum[i - 1][j];
			end
		end
		always @(posedge clk)
			extra[i] <= extra[i - 1];
	end

	/* Assign output */
	for (j = 0; j < SLICES - 1; j = j + 1) begin: out_slice
		assign z[j * SLICE_WIDTH +: SLICE_WIDTH] = sum[SLICES - 2][j][0 +: SLICE_WIDTH];
	end

	if (SLICES == 1) begin: extra_carry
		assign { carry_out, z } = x + y + carry_in;
	end else begin: extra_out
		assign { carry_out, z[WIDTH - 1 -: EXTRA_WIDTH] } = extra[SLICES - 2] + sum[SLICES - 2][SLICES - 2][SLICE_WIDTH];
	end
endmodule