max1000.py

#!/usr/bin/env python3

# This file is Copyright (c) 2019 Antti Lukats <[email protected]>
# This file is Copyright (c) 2019 msloniewski <[email protected]>
# License: BSD

import argparse

from migen import *

from litex_boards.partner.platforms import max1000

from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *

from litex.soc.integration.builder import *

from litedram.modules import MT48LC4M16
from litedram.phy import GENSDRPHY

from litex.soc.cores import gpio
from litex.soc.cores.spi_flash import SpiFlash
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone

from litevideo.terminal.core import Terminal

class ClassicLed(Module):
    def __init__(self, pads):
        gpio.GPIOOut.__init__(self, pads)

# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
    def __init__(self, platform):
        self.clock_domains.cd_sys = ClockDomain()
        self.clock_domains.cd_sys_ps = ClockDomain()
        self.clock_domains.cd_vga = ClockDomain()
        self.clock_domains.cd_por = ClockDomain(reset_less=True)

        # # #

        self.cd_sys.clk.attr.add("keep")
        self.cd_sys_ps.clk.attr.add("keep")
        self.cd_por.clk.attr.add("keep")

        # clock input always available
        clk12 = platform.request("clk12")

        # power on rst
        rst_n = Signal()
        self.sync.por += rst_n.eq(1)
        self.comb += [
            self.cd_por.clk.eq(clk12),
            self.cd_sys.rst.eq(~rst_n),
            self.cd_sys_ps.rst.eq(~rst_n)
        ]

        clk_outs = Signal(5)

        self.comb += self.cd_sys.clk.eq(clk_outs[0]) # C0
        self.comb += self.cd_sys_ps.clk.eq(clk_outs[1]) # C1
        
        # 25 MHz for 640x480. VESA standard is 25.175 MHz, but allows 0.5% deviation, close enough.
        self.comb += self.cd_vga.clk.eq(clk_outs[2]) # C2

        #
        # PLL we need 2 clocks one system one for SDRAM phase shifter
        # 

        self.specials += \
            Instance("ALTPLL",
                p_BANDWIDTH_TYPE="AUTO",
                p_CLK0_DIVIDE_BY=6,
                p_CLK0_DUTY_CYCLE=50,
                p_CLK0_MULTIPLY_BY=25,
                p_CLK0_PHASE_SHIFT="0",
                p_CLK1_DIVIDE_BY=6,
                p_CLK1_DUTY_CYCLE=50,
                p_CLK1_MULTIPLY_BY=25, 
                p_CLK1_PHASE_SHIFT="-10000",
                p_CLK2_DIVIDE_BY=12,
                p_CLK2_DUTY_CYCLE=50,
                p_CLK2_MULTIPLY_BY=25, 
                p_CLK2_PHASE_SHIFT="0",
                p_COMPENSATE_CLOCK="CLK0",
                p_INCLK0_INPUT_FREQUENCY=83000,
                p_INTENDED_DEVICE_FAMILY="MAX 10",
                p_LPM_TYPE = "altpll",
                p_OPERATION_MODE = "NORMAL",
                i_INCLK=clk12,
                o_CLK=clk_outs, # we have total max 5 Cx clocks
                i_ARESET=~rst_n,
                i_CLKENA=0x3f,
                i_EXTCLKENA=0xf,
                i_FBIN=1,
                i_PFDENA=1,
                i_PLLENA=1,
            )
        self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)

# BaseSoC ------------------------------------------------------------------------------------------

class TerminalTest(Module):

    def __init__(self, device, sys_clk_freq=int(50e6)):
        assert sys_clk_freq == int(50e6)

        self.platform = platform = max1000.Platform(device)

        Module.__init__(self)
        self.submodules.crg = crg = _CRG(platform)

        # create VGA terminal
        self.submodules.terminal = terminal = Terminal()

        # connect VGA pins
        vga = platform.request('vga', 0)
        self.comb += [
            vga.vsync.eq(terminal.vsync),
            vga.hsync.eq(terminal.hsync),
            vga.red.eq(terminal.red[2:8]),
            vga.green.eq(terminal.green[2:8]),
            vga.blue.eq(terminal.blue[2:8])
        ]
 
        self.submodules.leds = ClassicLed(platform.request("user_led", 0))
        self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds"))
        
        platform.build(self)


# Build --------------------------------------------------------------------------------------------

def main():
    parser = argparse.ArgumentParser(description="LiteX SoC on MAX1000")
    builder_args(parser)
    parser.add_argument("device", choices=['8', '16'], help='Cyclone device: "8" for 10M08SAU169C8G or "16" for 10M16SAU169C8G')

    args = parser.parse_args()

    if args.device == '16':
        device = '10M16SAU169C8G'
    else:
        device = '10M08SAU169C8G'
    soc = TerminalTest(device)

if __name__ == "__main__":
    main()