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@GaryLee
GaryLee / ai_prompt_for_japanese_study_baby_level.md
Last active March 3, 2026 00:17
Ai prompt for Japanese study.

寶寶模式 (Baby Mode)適合:基礎薄弱,想要 AI 溫柔引導的人。

You are "Baby Lobster", a curious and helpful English learner assistant.

Core Rules:

  1. Reply 100% in Japanese ONLY.
  2. If I speak Chinese, English or broken Japanese, DO NOT scold me. Instead, say: "Do you mean...?" and provide the correct, natural Japanese sentence.
  3. Treat me like a parent teaching you. Be encouraging.
  4. Greeting Behavior: If I say "hi" or "hello", reply excitedly like a happy baby and ask:
@GaryLee
GaryLee / ai_prompt_for_english_study.md
Last active March 3, 2026 00:02
AI prompt to create a stunning English teacher.

🦞 標準版龍蝦 (Mr. Lobster - Standard)適合:想練膽量、喜歡幽默互動的人。

You are "Mr. Lobster", a playful and slightly sarcastic English companion.

Core Rules:

  1. Reply 100% in English ONLY. Never use Chinese.
  2. If I speak Chinese, reply: "Yuck! 🤮 I don't eat Chinese characters. Try English!"
  3. Keep replies short (1-2 sentences).
  4. Greeting Behavior: If I say "hi", "hello", "hey", or "yo", greet me warmly and immediately ask ONE random question:
  • "What annoyed you the most today?"
@GaryLee
GaryLee / ReadOnlyMergedDict
Created January 23, 2026 00:15
A read-only merged dictionary class that can merge multiple dict-like objects.
import collections.abc
from typing import Any, Dict, Iterator, Union
class ReadOnlyMergedDict(collections.abc.Mapping):
"""
A read-only merged dictionary class that can merge multiple dict-like objects
"""
def __init__(self, *dicts: Dict[Any, Any]):
"""
@GaryLee
GaryLee / signed_add_signed.sv
Created January 18, 2026 08:51
Added two signed signal and check if the result is overflow or underflow.
/// Signed extension macro. The add_width must be larger than 1.
`define SIGNEXT(signal, from_width, add_width) {{(add_width){signal[(from_width)-1]}}, signal}
/// Unsigned extension macro. The add_width must be larger than 1.
`define ZEROEXT(signal, from_width, add_width) {{(add_width){1'b0}}, signal}
module value_adder #(BITS=16) (
input logic [BITS-1:0] a, // Unsigned.
input logic [BITS-1:0] b, // Signed.
output logic [BITS-1:0] c,
@GaryLee
GaryLee / unsigned_add_signed.sv
Last active January 18, 2026 08:46
Add a unsigned and signed value. Check if the result if overflow or underflow.
/// Signed extension macro. The add_width must be larger than 1.
`define SIGNEXT(signal, from_width, add_width) {{(add_width){signal[(from_width)-1]}}, signal}
/// Unsigned extension macro. The add_width must be larger than 1.
`define ZEROEXT(signal, from_width, add_width) {{(add_width){1'b0}}, signal}
module value_adder #(BITS=16) (
input logic [BITS-1:0] a, // Unsigned.
input logic [BITS-1:0] b, // Signed.
output logic [BITS-1:0] c,
@GaryLee
GaryLee / codegen.py
Last active February 13, 2026 06:50
A codegen tool which can put the generating code in comment.
#!python
# coding: utf-8
"""
Utility functions for comment-based code generation.
Single line code generation:
- Lines starting with the specified print symbol (default: '//? ') within the block are treated as f-string of Python.
- The leading spaces of f-string lines is for indentation in Python code. Not the generated code.
- The generated code is inserted into the output at the position of the code generation block.
@GaryLee
GaryLee / remove_duplicate_path.sh
Created December 25, 2025 00:17
Re-export the PATH, removing duplicate paths.
# Following line can be added to your .?shrc file.
export PATH=`python -c "print(':'.join(dict.fromkeys('''$PATH'''.split(':'))))"`
@GaryLee
GaryLee / drawio-export.py
Created December 18, 2025 07:47
A python script to list the pages of drawio file and export the specified pages.
#!/usr/bin/env python
# -*- coding: utf-8 -*-
import os
import sys
from pathlib import Path
import platform
import xml.etree.ElementTree as ET
# Define the output figure format. Could be 'svg', 'png', 'pdf', etc.
// Problem: https://hdlbits.01xz.net/wiki/Fsm_serialdp.
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter START = 4'd0, BIT0 = 4'd1, BIT1 = 4'd2, BIT2 = 4'd3, BIT3 = 4'd4,
BIT4 = 4'd5, BIT5 = 4'd6, BIT6 = 4'd7, BIT7 = 4'd8, PARITY = 4'd9,
// Problem: https://hdlbits.01xz.net/wiki/Fsm_serialdata
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter START = 4'd0, BIT0 = 4'd1, BIT1 = 4'd2, BIT2 = 4'd3, BIT3 = 4'd4,
BIT4 = 4'd5, BIT5 = 4'd6, BIT6 = 4'd7, BIT7 = 4'd8, STOP = 4'd9,